[llvm] [RISCV] Add support for Zibi experimental extension in RISCVRedundantCopyElimination (PR #174920)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Boyao Wang (BoyaoWang430)

<details>
<summary>Changes</summary>

This patch is like what Xqcibi did in https://github.com/llvm/llvm-project/pull/174358.

---
Full diff: https://github.com/llvm/llvm-project/pull/174920.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp (+4-2) 
- (added) llvm/test/CodeGen/RISCV/redundant-copy-elim.ll (+62) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
index 291af619105a4..9e39708d3c570 100644
--- a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
@@ -93,11 +93,11 @@ guaranteesRegEqualsImmInBlock(MachineBasicBlock &MBB,
   assert(TBB != nullptr && "Expected branch target basic block");
   auto Opc = Cond[0].getImm();
   if ((Opc == RISCV::QC_BEQI || Opc == RISCV::QC_E_BEQI ||
-       Opc == RISCV::NDS_BEQC) &&
+       Opc == RISCV::NDS_BEQC || Opc == RISCV::BEQI) &&
       Cond[2].isImm() && Cond[2].getImm() != 0 && TBB == &MBB)
     return true;
   if ((Opc == RISCV::QC_BNEI || Opc == RISCV::QC_E_BNEI ||
-       Opc == RISCV::NDS_BNEC) &&
+       Opc == RISCV::NDS_BNEC || Opc == RISCV::BNEI) &&
       Cond[2].isImm() && Cond[2].getImm() != 0 && TBB != &MBB)
     return true;
   return false;
@@ -189,6 +189,8 @@ bool RISCVRedundantCopyElimination::optimizeBlock(MachineBasicBlock &MBB) {
   MachineBasicBlock::iterator CondBr = PredMBB->getFirstTerminator();
   assert((CondBr->getOpcode() == RISCV::BEQ ||
           CondBr->getOpcode() == RISCV::BNE ||
+          CondBr->getOpcode() == RISCV::BEQI ||
+          CondBr->getOpcode() == RISCV::BNEI ||
           CondBr->getOpcode() == RISCV::QC_BEQI ||
           CondBr->getOpcode() == RISCV::QC_BNEI ||
           CondBr->getOpcode() == RISCV::QC_E_BEQI ||
diff --git a/llvm/test/CodeGen/RISCV/redundant-copy-elim.ll b/llvm/test/CodeGen/RISCV/redundant-copy-elim.ll
new file mode 100644
index 0000000000000..a93514dfaedc6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/redundant-copy-elim.ll
@@ -0,0 +1,62 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=RV32I
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=RV32IZIBI
+
+define i32 @test_beqi(i32 %a) nounwind {
+; RV32I-LABEL: test_beqi:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    li a1, 7
+; RV32I-NEXT:    bne a0, a1, .LBB0_2
+; RV32I-NEXT:  # %bb.1: # %if.end
+; RV32I-NEXT:    li a0, 7
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB0_2: # %if.then
+; RV32I-NEXT:    li a0, 1
+; RV32I-NEXT:    ret
+;
+; RV32IZIBI-LABEL: test_beqi:
+; RV32IZIBI:       # %bb.0: # %entry
+; RV32IZIBI-NEXT:    beqi a0, 7, .LBB0_2
+; RV32IZIBI-NEXT:  # %bb.1: # %if.then
+; RV32IZIBI-NEXT:    li a0, 1
+; RV32IZIBI-NEXT:  .LBB0_2: # %if.end
+; RV32IZIBI-NEXT:    ret
+entry:
+  %cmp = icmp eq i32 %a, 7
+  br i1 %cmp, label %if.end, label %if.then
+if.then:
+  ret i32 1
+if.end:
+  ret i32 7
+}
+
+define i32 @test_bnei(i32 %a) nounwind {
+; RV32I-LABEL: test_bnei:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    li a1, 7
+; RV32I-NEXT:    beq a0, a1, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %if.end
+; RV32I-NEXT:    li a0, 1
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB1_2: # %if.then
+; RV32I-NEXT:    li a0, 7
+; RV32I-NEXT:    ret
+;
+; RV32IZIBI-LABEL: test_bnei:
+; RV32IZIBI:       # %bb.0: # %entry
+; RV32IZIBI-NEXT:    beqi a0, 7, .LBB1_2
+; RV32IZIBI-NEXT:  # %bb.1: # %if.end
+; RV32IZIBI-NEXT:    li a0, 1
+; RV32IZIBI-NEXT:    ret
+; RV32IZIBI-NEXT:  .LBB1_2: # %if.then
+; RV32IZIBI-NEXT:    ret
+entry:
+  %cmp = icmp ne i32 %a, 7
+  br i1 %cmp, label %if.end, label %if.then
+if.then:
+  ret i32 7
+if.end:
+  ret i32 1
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/174920