[llvm] 0b819a6 - [RISCV] Simplify the RUN lines for ZVFH/ZVFHMIN. NFC.
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 7 23:16:35 PST 2026
Author: Jim Lin
Date: 2026-01-08T15:09:02+08:00
New Revision: 0b819a62be41c4acabc5f097c085512dc1827143
URL: https://github.com/llvm/llvm-project/commit/0b819a62be41c4acabc5f097c085512dc1827143
DIFF: https://github.com/llvm/llvm-project/commit/0b819a62be41c4acabc5f097c085512dc1827143.diff
LOG: [RISCV] Simplify the RUN lines for ZVFH/ZVFHMIN. NFC.
ZVFH and ZVFHMIN have the same code generation here.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
index 2774aba974a29..671da89366041 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
@@ -1,33 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
define <2 x bfloat> @vfabs_vv_v2bf16(<2 x bfloat> %va, <2 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_v2bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_v2bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_v2bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_v2bf16:
; ZVFBFA: # %bb.0:
@@ -39,21 +31,13 @@ define <2 x bfloat> @vfabs_vv_v2bf16(<2 x bfloat> %va, <2 x i1> %m, i32 zeroext
}
define <2 x bfloat> @vfabs_vv_v2bf16_unmasked(<2 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_v2bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_v2bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_v2bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_v2bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -65,21 +49,13 @@ define <2 x bfloat> @vfabs_vv_v2bf16_unmasked(<2 x bfloat> %va, i32 zeroext %evl
}
define <4 x bfloat> @vfabs_vv_v4bf16(<4 x bfloat> %va, <4 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_v4bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_v4bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_v4bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_v4bf16:
; ZVFBFA: # %bb.0:
@@ -91,21 +67,13 @@ define <4 x bfloat> @vfabs_vv_v4bf16(<4 x bfloat> %va, <4 x i1> %m, i32 zeroext
}
define <4 x bfloat> @vfabs_vv_v4bf16_unmasked(<4 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_v4bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_v4bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_v4bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_v4bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -117,21 +85,13 @@ define <4 x bfloat> @vfabs_vv_v4bf16_unmasked(<4 x bfloat> %va, i32 zeroext %evl
}
define <8 x bfloat> @vfabs_vv_v8bf16(<8 x bfloat> %va, <8 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_v8bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_v8bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_v8bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_v8bf16:
; ZVFBFA: # %bb.0:
@@ -143,21 +103,13 @@ define <8 x bfloat> @vfabs_vv_v8bf16(<8 x bfloat> %va, <8 x i1> %m, i32 zeroext
}
define <8 x bfloat> @vfabs_vv_v8bf16_unmasked(<8 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_v8bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_v8bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_v8bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_v8bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -169,21 +121,13 @@ define <8 x bfloat> @vfabs_vv_v8bf16_unmasked(<8 x bfloat> %va, i32 zeroext %evl
}
define <16 x bfloat> @vfabs_vv_v16bf16(<16 x bfloat> %va, <16 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_v16bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_v16bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_v16bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_v16bf16:
; ZVFBFA: # %bb.0:
@@ -195,21 +139,13 @@ define <16 x bfloat> @vfabs_vv_v16bf16(<16 x bfloat> %va, <16 x i1> %m, i32 zero
}
define <16 x bfloat> @vfabs_vv_v16bf16_unmasked(<16 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_v16bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_v16bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_v16bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_v16bf16_unmasked:
; ZVFBFA: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
index 84a89b23bc3b5..e94c8278f511a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
@@ -1,31 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+experimental-zvfbfa,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
define <2 x bfloat> @vfneg_vv_v2bf16(<2 x bfloat> %va, <2 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_v2bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_v2bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_v2bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_v2bf16:
; ZVFBFA: # %bb.0:
@@ -37,19 +30,12 @@ define <2 x bfloat> @vfneg_vv_v2bf16(<2 x bfloat> %va, <2 x i1> %m, i32 zeroext
}
define <2 x bfloat> @vfneg_vv_v2bf16_unmasked(<2 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_v2bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_v2bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_v2bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_v2bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -61,19 +47,12 @@ define <2 x bfloat> @vfneg_vv_v2bf16_unmasked(<2 x bfloat> %va, i32 zeroext %evl
}
define <4 x bfloat> @vfneg_vv_v4bf16(<4 x bfloat> %va, <4 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_v4bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_v4bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_v4bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_v4bf16:
; ZVFBFA: # %bb.0:
@@ -85,19 +64,12 @@ define <4 x bfloat> @vfneg_vv_v4bf16(<4 x bfloat> %va, <4 x i1> %m, i32 zeroext
}
define <4 x bfloat> @vfneg_vv_v4bf16_unmasked(<4 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_v4bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_v4bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_v4bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_v4bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -109,19 +81,12 @@ define <4 x bfloat> @vfneg_vv_v4bf16_unmasked(<4 x bfloat> %va, i32 zeroext %evl
}
define <8 x bfloat> @vfneg_vv_v8bf16(<8 x bfloat> %va, <8 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_v8bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_v8bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_v8bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_v8bf16:
; ZVFBFA: # %bb.0:
@@ -133,19 +98,12 @@ define <8 x bfloat> @vfneg_vv_v8bf16(<8 x bfloat> %va, <8 x i1> %m, i32 zeroext
}
define <8 x bfloat> @vfneg_vv_v8bf16_unmasked(<8 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_v8bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_v8bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_v8bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_v8bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -157,19 +115,12 @@ define <8 x bfloat> @vfneg_vv_v8bf16_unmasked(<8 x bfloat> %va, i32 zeroext %evl
}
define <16 x bfloat> @vfneg_vv_v16bf16(<16 x bfloat> %va, <16 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_v16bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_v16bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_v16bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_v16bf16:
; ZVFBFA: # %bb.0:
@@ -181,19 +132,12 @@ define <16 x bfloat> @vfneg_vv_v16bf16(<16 x bfloat> %va, <16 x i1> %m, i32 zero
}
define <16 x bfloat> @vfneg_vv_v16bf16_unmasked(<16 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_v16bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_v16bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_v16bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_v16bf16_unmasked:
; ZVFBFA: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
index b6ebe3ff2556e..e50f24f9307b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
@@ -1,37 +1,27 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
define <vscale x 1 x bfloat> @vfsgnj_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv1bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vand.vx v9, v9, a1, v0.t
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: vor.vv v8, v8, v9, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv1bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv1bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv1bf16:
; ZVFBFA: # %bb.0:
@@ -43,25 +33,15 @@ define <vscale x 1 x bfloat> @vfsgnj_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vsc
}
define <vscale x 1 x bfloat> @vfsgnj_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv1bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vand.vx v9, v9, a1
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: vor.vv v8, v8, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv1bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v9, v9, a1
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: vor.vv v8, v8, v9
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv1bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v9, v9, a1
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v9
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv1bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -73,25 +53,15 @@ define <vscale x 1 x bfloat> @vfsgnj_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat>
}
define <vscale x 2 x bfloat> @vfsgnj_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv2bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vand.vx v9, v9, a1, v0.t
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: vor.vv v8, v8, v9, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv2bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv2bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv2bf16:
; ZVFBFA: # %bb.0:
@@ -103,25 +73,15 @@ define <vscale x 2 x bfloat> @vfsgnj_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vsc
}
define <vscale x 2 x bfloat> @vfsgnj_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv2bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vand.vx v9, v9, a1
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: vor.vv v8, v8, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv2bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v9, v9, a1
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: vor.vv v8, v8, v9
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv2bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v9, v9, a1
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v9
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv2bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -133,25 +93,15 @@ define <vscale x 2 x bfloat> @vfsgnj_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat>
}
define <vscale x 4 x bfloat> @vfsgnj_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv4bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vand.vx v9, v9, a1, v0.t
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: vor.vv v8, v8, v9, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv4bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv4bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv4bf16:
; ZVFBFA: # %bb.0:
@@ -163,25 +113,15 @@ define <vscale x 4 x bfloat> @vfsgnj_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vsc
}
define <vscale x 4 x bfloat> @vfsgnj_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv4bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vand.vx v9, v9, a1
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: vor.vv v8, v8, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv4bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vand.vx v9, v9, a1
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: vor.vv v8, v8, v9
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv4bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v9, v9, a1
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v9
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv4bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -193,25 +133,15 @@ define <vscale x 4 x bfloat> @vfsgnj_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat>
}
define <vscale x 8 x bfloat> @vfsgnj_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv8bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vand.vx v10, v10, a1, v0.t
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: vor.vv v8, v8, v10, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv8bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v10, v10, a1, v0.t
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: vor.vv v8, v8, v10, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv8bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v10, v10, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v10, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv8bf16:
; ZVFBFA: # %bb.0:
@@ -223,25 +153,15 @@ define <vscale x 8 x bfloat> @vfsgnj_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vsc
}
define <vscale x 8 x bfloat> @vfsgnj_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv8bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vand.vx v10, v10, a1
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: vor.vv v8, v8, v10
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv8bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v10, v10, a1
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: vor.vv v8, v8, v10
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv8bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v10, v10, a1
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v10
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv8bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -253,25 +173,15 @@ define <vscale x 8 x bfloat> @vfsgnj_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat>
}
define <vscale x 16 x bfloat> @vfsgnj_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv16bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vand.vx v12, v12, a1, v0.t
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: vor.vv v8, v8, v12, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv16bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v12, v12, a1, v0.t
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: vor.vv v8, v8, v12, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv16bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v12, v12, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v12, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv16bf16:
; ZVFBFA: # %bb.0:
@@ -283,25 +193,15 @@ define <vscale x 16 x bfloat> @vfsgnj_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <
}
define <vscale x 16 x bfloat> @vfsgnj_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv16bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vand.vx v12, v12, a1
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: vor.vv v8, v8, v12
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv16bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v12, v12, a1
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: vor.vv v8, v8, v12
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv16bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v12, v12, a1
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v12
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv16bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -313,25 +213,15 @@ define <vscale x 16 x bfloat> @vfsgnj_vv_nxv16bf16_unmasked(<vscale x 16 x bfloa
}
define <vscale x 32 x bfloat> @vfsgnj_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv32bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vand.vx v16, v16, a1, v0.t
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: vor.vv v8, v8, v16, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv32bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vand.vx v16, v16, a1, v0.t
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: vor.vv v8, v8, v16, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv32bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v16, v16, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v16, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv32bf16:
; ZVFBFA: # %bb.0:
@@ -343,25 +233,15 @@ define <vscale x 32 x bfloat> @vfsgnj_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <
}
define <vscale x 32 x bfloat> @vfsgnj_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, i32 zeroext %evl) {
-; ZVFH-LABEL: vfsgnj_vv_nxv32bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vand.vx v16, v16, a1
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: vor.vv v8, v8, v16
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfsgnj_vv_nxv32bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vand.vx v16, v16, a1
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: vor.vv v8, v8, v16
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfsgnj_vv_nxv32bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v16, v16, a1
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v16
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfsgnj_vv_nxv32bf16_unmasked:
; ZVFBFA: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
index a7874d1f519fd..5fcc5b102d082 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
; RUN: --check-prefixes=CHECK,ZVFBFA
@@ -19,21 +19,13 @@
; RUN: --check-prefixes=CHECK,ZVFBFA
define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %v) {
-; ZVFH-LABEL: nxv1bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv1bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv1bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv1bf16:
; ZVFBFA: # %bb.0:
@@ -45,21 +37,13 @@ define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %v) {
}
define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %v) {
-; ZVFH-LABEL: nxv2bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv2bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv2bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv2bf16:
; ZVFBFA: # %bb.0:
@@ -71,21 +55,13 @@ define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %v) {
}
define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %v) {
-; ZVFH-LABEL: nxv4bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv4bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv4bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv4bf16:
; ZVFBFA: # %bb.0:
@@ -97,21 +73,13 @@ define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %v) {
}
define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %v) {
-; ZVFH-LABEL: nxv8bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv8bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv8bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv8bf16:
; ZVFBFA: # %bb.0:
@@ -123,21 +91,13 @@ define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %v) {
}
define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %v) {
-; ZVFH-LABEL: nxv16bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv16bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv16bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv16bf16:
; ZVFBFA: # %bb.0:
@@ -149,21 +109,13 @@ define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %v) {
}
define <vscale x 32 x bfloat> @nxv32bf16(<vscale x 32 x bfloat> %v) {
-; ZVFH-LABEL: nxv32bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv32bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv32bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv32bf16:
; ZVFBFA: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
index e0fcd4009ad2e..54f1f324dafa4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
@@ -1,33 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v,+experimental-zvfbfa -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v,+experimental-zvfbfa -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
define <vscale x 1 x bfloat> @vfabs_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv1bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv1bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv1bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv1bf16:
; ZVFBFA: # %bb.0:
@@ -39,21 +31,13 @@ define <vscale x 1 x bfloat> @vfabs_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
}
define <vscale x 1 x bfloat> @vfabs_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv1bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv1bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv1bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv1bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -65,21 +49,13 @@ define <vscale x 1 x bfloat> @vfabs_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %
}
define <vscale x 2 x bfloat> @vfabs_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv2bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv2bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv2bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv2bf16:
; ZVFBFA: # %bb.0:
@@ -91,21 +67,13 @@ define <vscale x 2 x bfloat> @vfabs_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
}
define <vscale x 2 x bfloat> @vfabs_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv2bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv2bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv2bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv2bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -117,21 +85,13 @@ define <vscale x 2 x bfloat> @vfabs_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %
}
define <vscale x 4 x bfloat> @vfabs_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv4bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv4bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv4bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv4bf16:
; ZVFBFA: # %bb.0:
@@ -143,21 +103,13 @@ define <vscale x 4 x bfloat> @vfabs_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vsca
}
define <vscale x 4 x bfloat> @vfabs_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv4bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv4bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv4bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv4bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -169,21 +121,13 @@ define <vscale x 4 x bfloat> @vfabs_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %
}
define <vscale x 8 x bfloat> @vfabs_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv8bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv8bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv8bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv8bf16:
; ZVFBFA: # %bb.0:
@@ -195,21 +139,13 @@ define <vscale x 8 x bfloat> @vfabs_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vsca
}
define <vscale x 8 x bfloat> @vfabs_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv8bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv8bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv8bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv8bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -221,21 +157,13 @@ define <vscale x 8 x bfloat> @vfabs_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %
}
define <vscale x 16 x bfloat> @vfabs_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv16bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv16bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv16bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv16bf16:
; ZVFBFA: # %bb.0:
@@ -247,21 +175,13 @@ define <vscale x 16 x bfloat> @vfabs_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <v
}
define <vscale x 16 x bfloat> @vfabs_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv16bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv16bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv16bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv16bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -273,21 +193,13 @@ define <vscale x 16 x bfloat> @vfabs_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat
}
define <vscale x 32 x bfloat> @vfabs_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv32bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv32bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv32bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv32bf16:
; ZVFBFA: # %bb.0:
@@ -299,21 +211,13 @@ define <vscale x 32 x bfloat> @vfabs_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
}
define <vscale x 32 x bfloat> @vfabs_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfabs_vv_nxv32bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: addi a1, a1, -1
-; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vand.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfabs_vv_nxv32bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: addi a1, a1, -1
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vand.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv32bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: addi a1, a1, -1
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv32bf16_unmasked:
; ZVFBFA: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
index 3a3fdbe59e6c9..f4af593780a5c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
; RUN: --check-prefixes=CHECK,ZVFBFA
@@ -19,25 +19,15 @@
; RUN: --check-prefixes=CHECK,ZVFBFA
define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %vm, <vscale x 1 x bfloat> %vs) {
-; ZVFH-LABEL: nxv1bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFH-NEXT: vand.vx v9, v9, a0
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: vor.vv v8, v8, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv1bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v9, v9, a0
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: vor.vv v8, v8, v9
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv1bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v9, v9, a0
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v9
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv1bf16:
; ZVFBFA: # %bb.0:
@@ -49,25 +39,15 @@ define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %vm, <vscale x 1 x
}
define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %vm, <vscale x 2 x bfloat> %vs) {
-; ZVFH-LABEL: nxv2bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZVFH-NEXT: vand.vx v9, v9, a0
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: vor.vv v8, v8, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv2bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v9, v9, a0
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: vor.vv v8, v8, v9
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv2bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v9, v9, a0
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v9
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv2bf16:
; ZVFBFA: # %bb.0:
@@ -79,25 +59,15 @@ define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %vm, <vscale x 2 x
}
define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %vm, <vscale x 4 x bfloat> %vs) {
-; ZVFH-LABEL: nxv4bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFH-NEXT: vand.vx v9, v9, a0
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: vor.vv v8, v8, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv4bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vand.vx v9, v9, a0
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: vor.vv v8, v8, v9
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv4bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v9, v9, a0
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v9
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv4bf16:
; ZVFBFA: # %bb.0:
@@ -109,25 +79,15 @@ define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %vm, <vscale x 4 x
}
define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %vm, <vscale x 8 x bfloat> %vs) {
-; ZVFH-LABEL: nxv8bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vand.vx v10, v10, a0
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: vor.vv v8, v8, v10
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv8bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vand.vx v10, v10, a0
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: vor.vv v8, v8, v10
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv8bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v10, v10, a0
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v10
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv8bf16:
; ZVFBFA: # %bb.0:
@@ -139,25 +99,15 @@ define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %vm, <vscale x 8 x
}
define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %vm, <vscale x 16 x bfloat> %vs) {
-; ZVFH-LABEL: nxv16bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; ZVFH-NEXT: vand.vx v12, v12, a0
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: vor.vv v8, v8, v12
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv16bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vand.vx v12, v12, a0
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: vor.vv v8, v8, v12
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv16bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v12, v12, a0
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v12
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv16bf16:
; ZVFBFA: # %bb.0:
@@ -169,25 +119,15 @@ define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %vm, <vscale x 1
}
define <vscale x 32 x bfloat> @nxv32bf32(<vscale x 32 x bfloat> %vm, <vscale x 32 x bfloat> %vs) {
-; ZVFH-LABEL: nxv32bf32:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFH-NEXT: vand.vx v16, v16, a0
-; ZVFH-NEXT: addi a0, a0, -1
-; ZVFH-NEXT: vand.vx v8, v8, a0
-; ZVFH-NEXT: vor.vv v8, v8, v16
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv32bf32:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vand.vx v16, v16, a0
-; ZVFHMIN-NEXT: addi a0, a0, -1
-; ZVFHMIN-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN-NEXT: vor.vv v8, v8, v16
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv32bf32:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vand.vx v16, v16, a0
+; ZVFH-ZVFHMIN-NEXT: addi a0, a0, -1
+; ZVFH-ZVFHMIN-NEXT: vand.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: vor.vv v8, v8, v16
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv32bf32:
; ZVFBFA: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
index c0b4916a54e51..3a20dee50bbe3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
+; RUN: --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v \
; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
; RUN: --check-prefixes=CHECK,ZVFBFA
@@ -19,19 +19,12 @@
; RUN: --check-prefixes=CHECK,ZVFBFA
define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %va) {
-; ZVFH-LABEL: nxv1bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv1bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv1bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv1bf16:
; ZVFBFA: # %bb.0:
@@ -43,19 +36,12 @@ define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %va) {
}
define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %va) {
-; ZVFH-LABEL: nxv2bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv2bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv2bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv2bf16:
; ZVFBFA: # %bb.0:
@@ -67,19 +53,12 @@ define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %va) {
}
define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %va) {
-; ZVFH-LABEL: nxv4bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv4bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv4bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv4bf16:
; ZVFBFA: # %bb.0:
@@ -91,19 +70,12 @@ define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %va) {
}
define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %va) {
-; ZVFH-LABEL: nxv8bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv8bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv8bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv8bf16:
; ZVFBFA: # %bb.0:
@@ -115,19 +87,12 @@ define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %va) {
}
define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %va) {
-; ZVFH-LABEL: nxv16bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv16bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv16bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv16bf16:
; ZVFBFA: # %bb.0:
@@ -139,19 +104,12 @@ define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %va) {
}
define <vscale x 32 x bfloat> @nxv32bf16(<vscale x 32 x bfloat> %va) {
-; ZVFH-LABEL: nxv32bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a0, 8
-; ZVFH-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: nxv32bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a0
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: nxv32bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a0, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a0
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: nxv32bf16:
; ZVFBFA: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
index 96fbe3f6ff025..5f372772b289d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
@@ -1,31 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
define <vscale x 1 x bfloat> @vfneg_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv1bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv1bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv1bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv1bf16:
; ZVFBFA: # %bb.0:
@@ -37,19 +30,12 @@ define <vscale x 1 x bfloat> @vfneg_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
}
define <vscale x 1 x bfloat> @vfneg_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv1bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv1bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv1bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv1bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -61,19 +47,12 @@ define <vscale x 1 x bfloat> @vfneg_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %
}
define <vscale x 2 x bfloat> @vfneg_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv2bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv2bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv2bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv2bf16:
; ZVFBFA: # %bb.0:
@@ -85,19 +64,12 @@ define <vscale x 2 x bfloat> @vfneg_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
}
define <vscale x 2 x bfloat> @vfneg_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv2bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv2bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv2bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv2bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -109,19 +81,12 @@ define <vscale x 2 x bfloat> @vfneg_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %
}
define <vscale x 4 x bfloat> @vfneg_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv4bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv4bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv4bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv4bf16:
; ZVFBFA: # %bb.0:
@@ -133,19 +98,12 @@ define <vscale x 4 x bfloat> @vfneg_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vsca
}
define <vscale x 4 x bfloat> @vfneg_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv4bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv4bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv4bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv4bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -157,19 +115,12 @@ define <vscale x 4 x bfloat> @vfneg_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %
}
define <vscale x 8 x bfloat> @vfneg_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv8bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv8bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv8bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv8bf16:
; ZVFBFA: # %bb.0:
@@ -181,19 +132,12 @@ define <vscale x 8 x bfloat> @vfneg_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vsca
}
define <vscale x 8 x bfloat> @vfneg_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv8bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv8bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv8bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv8bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -205,19 +149,12 @@ define <vscale x 8 x bfloat> @vfneg_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %
}
define <vscale x 16 x bfloat> @vfneg_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv16bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv16bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv16bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv16bf16:
; ZVFBFA: # %bb.0:
@@ -229,19 +166,12 @@ define <vscale x 16 x bfloat> @vfneg_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <v
}
define <vscale x 16 x bfloat> @vfneg_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv16bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv16bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv16bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv16bf16_unmasked:
; ZVFBFA: # %bb.0:
@@ -253,19 +183,12 @@ define <vscale x 16 x bfloat> @vfneg_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat
}
define <vscale x 32 x bfloat> @vfneg_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv32bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv32bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv32bf16:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv32bf16:
; ZVFBFA: # %bb.0:
@@ -277,19 +200,12 @@ define <vscale x 32 x bfloat> @vfneg_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
}
define <vscale x 32 x bfloat> @vfneg_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, i32 zeroext %evl) {
-; ZVFH-LABEL: vfneg_vv_nxv32bf16_unmasked:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: lui a1, 8
-; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vxor.vx v8, v8, a1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vfneg_vv_nxv32bf16_unmasked:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: ret
+; ZVFH-ZVFHMIN-LABEL: vfneg_vv_nxv32bf16_unmasked:
+; ZVFH-ZVFHMIN: # %bb.0:
+; ZVFH-ZVFHMIN-NEXT: lui a1, 8
+; ZVFH-ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFH-ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFH-ZVFHMIN-NEXT: ret
;
; ZVFBFA-LABEL: vfneg_vv_nxv32bf16_unmasked:
; ZVFBFA: # %bb.0:
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