[llvm] [NVPTX] Validate user-specified PTX version against SM version (PR #174834)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 7 11:04:04 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-nvptx
Author: Justin Fargnoli (justinfargnoli)
<details>
<summary>Changes</summary>
When users explicitly specify a PTX version via `-mattr=+ptxNN` that's insufficient for their target SM, we now emit a fatal error. Previously, we silently upgraded the PTX version to the minimum required for the target SM.
When no SM or PTX version is specified, we now use PTX 3.2 (the minimum for the default SM 3.0) instead of PTX 6.0.
---
Patch is 21.81 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/174834.diff
16 Files Affected:
- (modified) llvm/lib/Target/NVPTX/NVPTX.td (+42-41)
- (modified) llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp (+88-2)
- (modified) llvm/lib/Target/NVPTX/NVPTXSubtarget.h (+3-2)
- (modified) llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll (+4-4)
- (modified) llvm/test/CodeGen/NVPTX/convert-sm100a.ll (+2-2)
- (modified) llvm/test/CodeGen/NVPTX/convert-sm103a.ll (+2-2)
- (modified) llvm/test/CodeGen/NVPTX/f32-ex2.ll (+2-2)
- (modified) llvm/test/CodeGen/NVPTX/fexp2.ll (+2-2)
- (modified) llvm/test/CodeGen/NVPTX/flog2.ll (+2-2)
- (modified) llvm/test/CodeGen/NVPTX/i128.ll (+2-2)
- (modified) llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll (+1-1)
- (added) llvm/test/CodeGen/NVPTX/ptx-version-validation.ll (+51)
- (modified) llvm/test/CodeGen/NVPTX/rsqrt.ll (+2-2)
- (modified) llvm/test/CodeGen/NVPTX/sm-version.ll (+1-1)
- (modified) llvm/test/CodeGen/NVPTX/surf-tex.py (+2-2)
- (removed) llvm/test/CodeGen/NVPTX/wmma-ptx86-sm120a.py (-14)
``````````diff
diff --git a/llvm/lib/Target/NVPTX/NVPTX.td b/llvm/lib/Target/NVPTX/NVPTX.td
index d41a43de95098..bc2d67c9769dc 100644
--- a/llvm/lib/Target/NVPTX/NVPTX.td
+++ b/llvm/lib/Target/NVPTX/NVPTX.td
@@ -68,10 +68,11 @@ class FeaturePTX<int version>:
// represents 'z'), sm_103f, and sm_103 architecture variants. The sm_103 is
// compatible with sm_103a and sm_103f, and sm_103f is compatible with sm_103a.
//
-// Encoding := Arch * 10 + 2 (for 'f') + 1 (for 'a')
+// Encoding := Arch * 10 + suffix_offset
// Arch := X * 10 + Y
+// suffix_offset := 0 (base), 2 ('f'), or 3 ('a')
//
-// For example, sm_103a is encoded as 1033 (103 * 10 + 2 + 1) and sm_103f is
+// For example, sm_103a is encoded as 1033 (103 * 10 + 3) and sm_103f is
// encoded as 1032 (103 * 10 + 2).
//
// This encoding allows simple partial ordering of the architectures.
@@ -109,46 +110,46 @@ foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 62, 63, 64, 65, 70, 71, 72,
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
-def : Proc<"sm_20", [SM20, PTX32]>;
-def : Proc<"sm_21", [SM21, PTX32]>;
+def : Proc<"sm_20", [SM20]>;
+def : Proc<"sm_21", [SM21]>;
def : Proc<"sm_30", [SM30]>;
-def : Proc<"sm_32", [SM32, PTX40]>;
-def : Proc<"sm_35", [SM35, PTX32]>;
-def : Proc<"sm_37", [SM37, PTX41]>;
-def : Proc<"sm_50", [SM50, PTX40]>;
-def : Proc<"sm_52", [SM52, PTX41]>;
-def : Proc<"sm_53", [SM53, PTX42]>;
-def : Proc<"sm_60", [SM60, PTX50]>;
-def : Proc<"sm_61", [SM61, PTX50]>;
-def : Proc<"sm_62", [SM62, PTX50]>;
-def : Proc<"sm_70", [SM70, PTX60]>;
-def : Proc<"sm_72", [SM72, PTX61]>;
-def : Proc<"sm_75", [SM75, PTX63]>;
-def : Proc<"sm_80", [SM80, PTX70]>;
-def : Proc<"sm_86", [SM86, PTX71]>;
-def : Proc<"sm_87", [SM87, PTX74]>;
-def : Proc<"sm_88", [SM88, PTX90]>;
-def : Proc<"sm_89", [SM89, PTX78]>;
-def : Proc<"sm_90", [SM90, PTX78]>;
-def : Proc<"sm_90a", [SM90a, PTX80]>;
-def : Proc<"sm_100", [SM100, PTX86]>;
-def : Proc<"sm_100a", [SM100a, PTX86]>;
-def : Proc<"sm_100f", [SM100f, PTX88]>;
-def : Proc<"sm_101", [SM101, PTX86]>;
-def : Proc<"sm_101a", [SM101a, PTX86]>;
-def : Proc<"sm_101f", [SM101f, PTX88]>;
-def : Proc<"sm_103", [SM103, PTX88]>;
-def : Proc<"sm_103a", [SM103a, PTX88]>;
-def : Proc<"sm_103f", [SM103f, PTX88]>;
-def : Proc<"sm_110", [SM110, PTX90]>;
-def : Proc<"sm_110a", [SM110a, PTX90]>;
-def : Proc<"sm_110f", [SM110f, PTX90]>;
-def : Proc<"sm_120", [SM120, PTX87]>;
-def : Proc<"sm_120a", [SM120a, PTX87]>;
-def : Proc<"sm_120f", [SM120f, PTX88]>;
-def : Proc<"sm_121", [SM121, PTX88]>;
-def : Proc<"sm_121a", [SM121a, PTX88]>;
-def : Proc<"sm_121f", [SM121f, PTX88]>;
+def : Proc<"sm_32", [SM32]>;
+def : Proc<"sm_35", [SM35]>;
+def : Proc<"sm_37", [SM37]>;
+def : Proc<"sm_50", [SM50]>;
+def : Proc<"sm_52", [SM52]>;
+def : Proc<"sm_53", [SM53]>;
+def : Proc<"sm_60", [SM60]>;
+def : Proc<"sm_61", [SM61]>;
+def : Proc<"sm_62", [SM62]>;
+def : Proc<"sm_70", [SM70]>;
+def : Proc<"sm_72", [SM72]>;
+def : Proc<"sm_75", [SM75]>;
+def : Proc<"sm_80", [SM80]>;
+def : Proc<"sm_86", [SM86]>;
+def : Proc<"sm_87", [SM87]>;
+def : Proc<"sm_88", [SM88]>;
+def : Proc<"sm_89", [SM89]>;
+def : Proc<"sm_90", [SM90]>;
+def : Proc<"sm_90a", [SM90a]>;
+def : Proc<"sm_100", [SM100]>;
+def : Proc<"sm_100a", [SM100a]>;
+def : Proc<"sm_100f", [SM100f]>;
+def : Proc<"sm_101", [SM101]>;
+def : Proc<"sm_101a", [SM101a]>;
+def : Proc<"sm_101f", [SM101f]>;
+def : Proc<"sm_103", [SM103]>;
+def : Proc<"sm_103a", [SM103a]>;
+def : Proc<"sm_103f", [SM103f]>;
+def : Proc<"sm_110", [SM110]>;
+def : Proc<"sm_110a", [SM110a]>;
+def : Proc<"sm_110f", [SM110f]>;
+def : Proc<"sm_120", [SM120]>;
+def : Proc<"sm_120a", [SM120a]>;
+def : Proc<"sm_120f", [SM120f]>;
+def : Proc<"sm_121", [SM121]>;
+def : Proc<"sm_121a", [SM121a]>;
+def : Proc<"sm_121f", [SM121f]>;
def Is64Bit : Predicate<"Subtarget->getTargetTriple().getArch() == Triple::nvptx64">;
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
index 989be50d45554..00b21c0ef21ea 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
@@ -38,6 +38,82 @@ static cl::opt<bool> NoF32x2("nvptx-no-f32x2", cl::Hidden,
// Pin the vtable to this file.
void NVPTXSubtarget::anchor() {}
+// Returns the minimum PTX version required for a given SM target.
+// This must be kept in sync with the "Supported Targets" column of the
+// "PTX Release History" table in the PTX ISA documentation:
+// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#release-notes-ptx-release-history
+//
+// Note: LLVM's minimum supported PTX version is 3.2 (see FeaturePTX in
+// NVPTX.td), so older SMs that supported earlier PTX versions instead use 3.2
+// as their effective minimum.
+//
+// The FullSmVersion encoding is: SM * 10 + suffix_offset
+// where suffix_offset is: 0 (base), 2 ('f' suffix), or 3 ('a' suffix)
+// For example: sm_100 = 1000, sm_100f = 1002, sm_100a = 1003
+static unsigned getMinPTXVersionForSM(unsigned FullSmVersion) {
+ switch (FullSmVersion) {
+ case 200: // sm_20
+ case 210: // sm_21
+ case 300: // sm_30
+ case 350: // sm_35
+ return 32;
+ case 320: // sm_32
+ case 500: // sm_50
+ return 40;
+ case 370: // sm_37
+ case 520: // sm_52
+ return 41;
+ case 530: // sm_53
+ return 42;
+ case 600: // sm_60
+ case 610: // sm_61
+ case 620: // sm_62
+ return 50;
+ case 700: // sm_70
+ return 60;
+ case 720: // sm_72
+ return 61;
+ case 750: // sm_75
+ return 63;
+ case 800: // sm_80
+ return 70;
+ case 860: // sm_86
+ return 71;
+ case 870: // sm_87
+ return 74;
+ case 890: // sm_89
+ case 900: // sm_90
+ return 78;
+ case 903: // sm_90a
+ return 80;
+ case 1000: // sm_100
+ case 1003: // sm_100a
+ case 1010: // sm_101
+ case 1013: // sm_101a
+ return 86;
+ case 1200: // sm_120
+ case 1203: // sm_120a
+ return 87;
+ case 1002: // sm_100f
+ case 1012: // sm_101f
+ case 1030: // sm_103
+ case 1032: // sm_103f
+ case 1033: // sm_103a
+ case 1202: // sm_120f
+ case 1210: // sm_121
+ case 1212: // sm_121f
+ case 1213: // sm_121a
+ return 88;
+ case 880: // sm_88
+ case 1100: // sm_110
+ case 1102: // sm_110f
+ case 1103: // sm_110a
+ return 90;
+ default:
+ llvm_unreachable("Unknown SM version");
+ }
+}
+
NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
TargetName = std::string(CPU);
@@ -49,9 +125,19 @@ NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
// sm_90a, which would *not* be a subset of sm_91.
SmVersion = getSmVersion();
- // Set default to PTX 6.0 (CUDA 9.0)
+ unsigned MinPTX = getMinPTXVersionForSM(FullSmVersion);
+
if (PTXVersion == 0) {
- PTXVersion = 60;
+ // User didn't request a specific PTX version; use the minimum for this SM.
+ PTXVersion = MinPTX;
+ } else if (PTXVersion < MinPTX) {
+ // User explicitly requested an insufficient PTX version.
+ report_fatal_error(formatv(
+ "PTX version {0}.{1} does not support target '{2}'. "
+ "Minimum required PTX version is {3}.{4}. "
+ "Either remove the PTX version to use the default, "
+ "or increase it to at least {3}.{4}.",
+ PTXVersion / 10, PTXVersion % 10, CPU, MinPTX / 10, MinPTX % 10));
}
return *this;
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
index 6f6057b3689e6..66a9fae7c6fce 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
@@ -35,8 +35,9 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
// PTX version x.y is represented as 10*x+y, e.g. 3.1 == 31
unsigned PTXVersion;
- // Full SM version x.y is represented as 100*x+10*y+feature, e.g. 3.1 == 310
- // sm_90a == 901
+ // FullSmVersion is SM * 10 + suffix_offset
+ // where suffix_offset is: 0 (base), 2 ('f'), or 3 ('a')
+ // e.g. sm_30 == 300, sm_90a == 903, sm_100f == 1002
unsigned int FullSmVersion;
// SM version x.y is represented as 10*x+y, e.g. 3.1 == 31. Derived from
diff --git a/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll b/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
index d930d1842a1d4..eb36c6f09edeb 100644
--- a/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
+++ b/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
@@ -7,10 +7,10 @@
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_101a -mattr=+ptx86 --nvptx-short-ptr | FileCheck --check-prefixes=CHECK,CHECK-PTX-SHARED32 %s
; RUN: %if ptxas-sm_101a && ptxas-isa-8.6 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_101a -mattr=+ptx86 | %ptxas-verify -arch=sm_101a %}
; RUN: %if ptxas-sm_101a && ptxas-isa-8.6 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_101a -mattr=+ptx86 --nvptx-short-ptr | %ptxas-verify -arch=sm_101a %}
-; RUN: llc -o - -mcpu=sm_120a -march=nvptx64 -mattr=+ptx86 %s | FileCheck %s --check-prefixes=CHECK,CHECK-PTX-SHARED64
-; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx86 --nvptx-short-ptr | FileCheck --check-prefixes=CHECK,CHECK-PTX-SHARED32 %s
-; RUN: %if ptxas-sm_120a && ptxas-isa-8.6 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx86 | %ptxas-verify -arch=sm_120a %}
-; RUN: %if ptxas-sm_120a && ptxas-isa-8.6 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx86 --nvptx-short-ptr | %ptxas-verify -arch=sm_120a %}
+; RUN: llc -o - -mcpu=sm_120a -march=nvptx64 -mattr=+ptx87 %s | FileCheck %s --check-prefixes=CHECK,CHECK-PTX-SHARED64
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx87 --nvptx-short-ptr | FileCheck --check-prefixes=CHECK,CHECK-PTX-SHARED32 %s
+; RUN: %if ptxas-sm_120a && ptxas-isa-8.7 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx87 | %ptxas-verify -arch=sm_120a %}
+; RUN: %if ptxas-sm_120a && ptxas-isa-8.7 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx87 --nvptx-short-ptr | %ptxas-verify -arch=sm_120a %}
define void @nvvm_clusterlaunchcontrol_try_cancel_multicast(
; CHECK-PTX-SHARED64-LABEL: nvvm_clusterlaunchcontrol_try_cancel_multicast(
diff --git a/llvm/test/CodeGen/NVPTX/convert-sm100a.ll b/llvm/test/CodeGen/NVPTX/convert-sm100a.ll
index 16bd0da8c6a0c..cbf7c114b06ca 100644
--- a/llvm/test/CodeGen/NVPTX/convert-sm100a.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-sm100a.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_100a -mattr=+ptx86 | FileCheck %s
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_101a -mattr=+ptx86 | FileCheck %s
-; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx86 | FileCheck %s
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx87 | FileCheck %s
; RUN: %if ptxas-sm_100a && ptxas-isa-8.6 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_100a -mattr=+ptx86 | %ptxas-verify -arch=sm_100a %}
; RUN: %if ptxas-sm_101a && ptxas-isa-8.6 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_101a -mattr=+ptx86 | %ptxas-verify -arch=sm_101a %}
-; RUN: %if ptxas-sm_120a && ptxas-isa-8.6 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx86 | %ptxas-verify -arch=sm_120a %}
+; RUN: %if ptxas-sm_120a && ptxas-isa-8.7 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx87 | %ptxas-verify -arch=sm_120a %}
define i16 @cvt_rn_sf_e2m3x2_f32(float %f1, float %f2) {
; CHECK-LABEL: cvt_rn_sf_e2m3x2_f32(
diff --git a/llvm/test/CodeGen/NVPTX/convert-sm103a.ll b/llvm/test/CodeGen/NVPTX/convert-sm103a.ll
index 54b4dd88867ed..b58c8b3e7abc5 100644
--- a/llvm/test/CodeGen/NVPTX/convert-sm103a.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-sm103a.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_100a -mattr=+ptx87 | FileCheck %s
-; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_103a -mattr=+ptx87 | FileCheck %s
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_103a -mattr=+ptx88 | FileCheck %s
; RUN: %if ptxas-sm_100a && ptxas-isa-8.7 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_100a -mattr=+ptx87 | %ptxas-verify -arch=sm_100a %}
-; RUN: %if ptxas-sm_103a && ptxas-isa-8.7 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_103a -mattr=+ptx87 | %ptxas-verify -arch=sm_103a %}
+; RUN: %if ptxas-sm_103a && ptxas-isa-8.8 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_103a -mattr=+ptx88 | %ptxas-verify -arch=sm_103a %}
; F16X2 conversions
diff --git a/llvm/test/CodeGen/NVPTX/f32-ex2.ll b/llvm/test/CodeGen/NVPTX/f32-ex2.ll
index 97b9d35be371e..db3dd4a9e6011 100644
--- a/llvm/test/CodeGen/NVPTX/f32-ex2.ll
+++ b/llvm/test/CodeGen/NVPTX/f32-ex2.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mcpu=sm_50 -mattr=+ptx32 | FileCheck --check-prefixes=CHECK %s
-; RUN: %if ptxas-sm_50 && ptxas-isa-3.2 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_50 -mattr=+ptx32 | %ptxas-verify -arch=sm_50 %}
+; RUN: llc < %s -mcpu=sm_50 | FileCheck --check-prefixes=CHECK %s
+; RUN: %if ptxas-sm_50 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_50 | %ptxas-verify -arch=sm_50 %}
target triple = "nvptx-nvidia-cuda"
declare float @llvm.nvvm.ex2.approx.f32(float)
diff --git a/llvm/test/CodeGen/NVPTX/fexp2.ll b/llvm/test/CodeGen/NVPTX/fexp2.ll
index d9e82cc372e24..047e4bbc3fa32 100644
--- a/llvm/test/CodeGen/NVPTX/fexp2.ll
+++ b/llvm/test/CodeGen/NVPTX/fexp2.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mcpu=sm_50 -mattr=+ptx32 | FileCheck --check-prefixes=CHECK %s
+; RUN: llc < %s -mcpu=sm_50 | FileCheck --check-prefixes=CHECK %s
; RUN: llc < %s -mcpu=sm_75 -mattr=+ptx70 | FileCheck --check-prefixes=CHECK-FP16 %s
; RUN: llc < %s -mcpu=sm_90 -mattr=+ptx78 | FileCheck --check-prefixes=CHECK-BF16 %s
-; RUN: %if ptxas-sm_50 && ptxas-isa-3.2 %{ llc < %s -mcpu=sm_50 -mattr=+ptx32 | %ptxas-verify -arch=sm_50 %}
+; RUN: %if ptxas-sm_50 %{ llc < %s -mcpu=sm_50 | %ptxas-verify -arch=sm_50 %}
; RUN: %if ptxas-sm_75 && ptxas-isa-7.0 %{ llc < %s -mcpu=sm_75 -mattr=+ptx70 | %ptxas-verify -arch=sm_75 %}
; RUN: %if ptxas-sm_90 && ptxas-isa-7.8 %{ llc < %s -mcpu=sm_90 -mattr=+ptx78 | %ptxas-verify -arch=sm_90 %}
target triple = "nvptx64-nvidia-cuda"
diff --git a/llvm/test/CodeGen/NVPTX/flog2.ll b/llvm/test/CodeGen/NVPTX/flog2.ll
index 4aafc986db1d9..66e92e3428ff9 100644
--- a/llvm/test/CodeGen/NVPTX/flog2.ll
+++ b/llvm/test/CodeGen/NVPTX/flog2.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mcpu=sm_50 -mattr=+ptx32 -nvptx-approx-log2f32 | FileCheck --check-prefixes=CHECK %s
-; RUN: %if ptxas-sm_50 && ptxas-isa-3.2 %{ llc < %s -mcpu=sm_50 -mattr=+ptx32 -nvptx-approx-log2f32 | %ptxas-verify -arch=sm_50 %}
+; RUN: llc < %s -mcpu=sm_50 -nvptx-approx-log2f32 | FileCheck --check-prefixes=CHECK %s
+; RUN: %if ptxas-sm_50 %{ llc < %s -mcpu=sm_50 -nvptx-approx-log2f32 | %ptxas-verify -arch=sm_50 %}
target triple = "nvptx64-nvidia-cuda"
; CHECK-LABEL: log2_test
diff --git a/llvm/test/CodeGen/NVPTX/i128.ll b/llvm/test/CodeGen/NVPTX/i128.ll
index 5726c2a5bbb16..9d82292852d84 100644
--- a/llvm/test/CodeGen/NVPTX/i128.ll
+++ b/llvm/test/CodeGen/NVPTX/i128.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=nvptx64-- 2>&1 | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64-- | %ptxas-verify %}
+; RUN: llc < %s -mtriple=nvptx64-- -mattr=+ptx60 2>&1 | FileCheck %s
+; RUN: %if ptxas-isa-6.0 %{ llc < %s -mtriple=nvptx64-- -mattr=+ptx60 | %ptxas-verify %}
define i128 @srem_i128(i128 %lhs, i128 %rhs) {
; CHECK-LABEL: srem_i128(
diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
index a7f3103e5fcbb..cdbf3c3305305 100644
--- a/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
+++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_52 -mattr=+ptx64 -O0 | FileCheck %s --check-prefixes=SM_52,COMMON
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_70 -mattr=+ptx64 -O0 | FileCheck %s --check-prefixes=SM_70,COMMON
-; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx72 -O0 | FileCheck %s --check-prefixes=SM_90,COMMON
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90 -O0 | FileCheck %s --check-prefixes=SM_90,COMMON
@.str = private unnamed_addr constant [12 x i8] c"__CUDA_ARCH\00"
@.str1 = constant [11 x i8] c"__CUDA_FTZ\00"
diff --git a/llvm/test/CodeGen/NVPTX/ptx-version-validation.ll b/llvm/test/CodeGen/NVPTX/ptx-version-validation.ll
new file mode 100644
index 0000000000000..12614e3ef848f
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/ptx-version-validation.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_103a -mattr=+ptx90 2>&1 | FileCheck %s --check-prefix=CHECK-SM103A-HIGH
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_103a 2>&1 | FileCheck %s --check-prefix=CHECK-SM103A
+; RUN: not llc < %s -mtriple=nvptx64 -mcpu=sm_103a -mattr=+ptx87 2>&1 | FileCheck %s --check-prefix=CHECK-SM103A-LOW
+; RUN: %if ptxas-sm_103a && ptxas-isa-9.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_103a -mattr=+ptx90 | %ptxas-verify -arch=sm_103a %}
+; RUN: %if ptxas-sm_103a %{ llc < %s -mtriple=nvptx64 -mcpu=sm_103a | %ptxas-verify -arch=sm_103a %}
+
+; Test that sm_120a defaults/requires PTX 8.7
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_120a 2>&1 | FileCheck %s --check-prefix=CHECK-SM120A
+; RUN: not llc < %s -mtriple=nvptx64 -mcpu=sm_120a -mattr=+ptx86 2>&1 | FileCheck %s --check-prefix=CHECK-SM120A-LOW
+; RUN: %if ptxas-sm_120a %{ llc < %s -mtriple=nvptx64 -mcpu=sm_120a | %ptxas-verify -arch=sm_120a %}
+
+; Test that sm_90a defaults/requires PTX 8.0
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90a 2>&1 | FileCheck %s --check-prefix=CHECK-SM90A
+; RUN: not llc < %s -mtriple=nvptx64 -mcpu=sm_90a -mattr=+ptx78 2>&1 | FileCheck %s --check-prefix=CHECK-SM90A-LOW
+; RUN: %if ptxas-sm_90a %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90a | %ptxas-verify -arch=sm_90a %}
+
+; Test older SM targets
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_80 2>&1 | FileCheck %s --check-prefix=CHECK-SM80
+; RUN: not llc < %s -mtriple=nvptx64 -mcpu=sm_80 -mattr=+ptx63 2>&1 | FileCheck %s --check-prefix=CHECK-SM80-LOW
+; RUN: %if ptxas-sm_80 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
+
+; CHECK-SM103A-HIGH: .version 9.0
+; CHECK-SM103A-HIGH: .target sm_103a
+
+; CHECK-SM103A: .version 8.8
+; CHECK-SM103A: .target sm_103a
+
+; CHECK-SM103A-LOW: LLVM ERROR: PTX version 8.7 does not support target 'sm_103a'.
+; CHECK-SM103A-LOW: Minimum required PTX version is 8.8.
+
+; CHECK-SM120A: .version 8.7
+; CHECK-SM120A: .target sm_120a
+
+; CHECK-SM120A-LOW: LLVM ERROR: PTX version 8.6 does not support target 'sm_120a'.
+; CHECK-SM120A-LOW: Minimum required PTX version is 8.7.
+
+; CHECK-SM90A: .version 8.0
+; CHECK-SM90A: .target sm_90a
+
+; CHECK-SM90A-LOW: LLVM ERROR: PTX version 7.8 does not support target 'sm_90a'.
+; CHECK-SM90A-LOW: Minimum required PTX version is 8.0.
+
+; CHECK-SM80: .version 7.0
+; CHECK-SM80: .target sm_80
+
+; CHECK-SM80-LOW: LLVM ERROR: PTX version 6.3 does not support target 'sm_80'.
+; CHECK-SM80-LOW: Minimum required PTX version is 7.0.
+
+define void @foo() {
+ ret void
+}
diff --git a/llvm/test/CodeGen/NVPTX/rsqrt.ll b/llvm/test/CodeGen/NVPTX/rsqrt.ll
index 0e19dc11021c7..65bcf8d9f404b 100644
--- a/llvm/test/CodeGen/NVPTX/rsqrt.ll
+++ b/llvm/test/CodeGen/NVPTX/rsqrt.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=nvptx64 | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 | %ptxas-verify %}
+; RUN: llc < %s -mtriple=nvptx64 -mattr=+ptx40 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mattr=+ptx40 | %ptxas-verify %}
; CHECK-LABEL: .func{{.*}}test1
define float @test1(float %in) local_unnamed_addr {
diff --git a/llvm/test/CodeGen/NVPTX/sm-version.ll b/llvm/test/CodeGen/NVPTX/sm-version.ll
index c90c086e8b96c..620bfebd12037 100644
--- a/llvm/test/CodeGen/NVPTX/sm-version.ll
+++ b/llvm/test/CodeGen/NVPTX/sm-version.ll
@@ -76,7 +76,7 @@
; SM20: .version 3.2
; SM21: .version 3.2
-; SM30: .version 6.0
+; SM30: .version 3.2
; SM32: .version 4.0
; SM35: .version 3.2
; SM37: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/174834
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