[llvm] [AArch64][llvm] Add codegen for simd fpcvt intrinsics (PR #173272)

[via llvm-commits]

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@@ -0,0 +1,246 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+neon,+fullfp16,+fprcvt | FileCheck %s --check-prefixes=CHECK
+
+define double @scvtf_bitcast_f32_to_f64(float %f) nounwind {
+; CHECK-LABEL: scvtf_bitcast_f32_to_f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    scvtf d0, s0
+; CHECK-NEXT:    ret
+  %i = bitcast float %f to i32
+  %r = sitofp i32 %i to double
+  ret double %r
+}
+
+define double @ucvtf_bitcast_f32_to_f64(float %f) nounwind {
+; CHECK-LABEL: ucvtf_bitcast_f32_to_f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ucvtf d0, s0
+; CHECK-NEXT:    ret
+  %i = bitcast float %f to i32
+  %r = uitofp i32 %i to double
+  ret double %r
+}
+
+define half @scvtf_bitcast_f32_to_f16(float %f) nounwind {
+; CHECK-LABEL: scvtf_bitcast_f32_to_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    scvtf h0, s0
+; CHECK-NEXT:    ret
+  %i = bitcast float %f to i32
+  %r = sitofp i32 %i to half
+  ret half %r
+}
+
+define half @ucvtf_bitcast_f32_to_f16(float %f) nounwind {
+; CHECK-LABEL: ucvtf_bitcast_f32_to_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ucvtf h0, s0
+; CHECK-NEXT:    ret
+  %i = bitcast float %f to i32
+  %r = uitofp i32 %i to half
+  ret half %r
+}
+
+define float @scvtf_bitcast_f64_to_f32(double %d) nounwind {
+; CHECK-LABEL: scvtf_bitcast_f64_to_f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    scvtf s0, d0
+; CHECK-NEXT:    ret
+  %i = bitcast double %d to i64
+  %r = sitofp i64 %i to float
+  ret float %r
+}
+
+define float @ucvtf_bitcast_f64_to_f32(double %d) nounwind {
+; CHECK-LABEL: ucvtf_bitcast_f64_to_f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ucvtf s0, d0
+; CHECK-NEXT:    ret
+  %i = bitcast double %d to i64
+  %r = uitofp i64 %i to float
+  ret float %r
+}
+
+define half @scvtf_bitcast_f64_to_f16(double %d) nounwind {
+; CHECK-LABEL: scvtf_bitcast_f64_to_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    scvtf h0, d0
+; CHECK-NEXT:    ret
+  %i = bitcast double %d to i64
+  %r = sitofp i64 %i to half
+  ret half %r
+}
+
+define half @ucvtf_bitcast_f64_to_f16(double %d) nounwind {
+; CHECK-LABEL: ucvtf_bitcast_f64_to_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ucvtf h0, d0
+; CHECK-NEXT:    ret
+  %i = bitcast double %d to i64
+  %r = uitofp i64 %i to half
+  ret half %r
+}
+
+define float @scvtf_bitcast_f32_to_f32(float %f) nounwind {
+; CHECK-LABEL: scvtf_bitcast_f32_to_f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    scvtf s0, s0
+; CHECK-NEXT:    ret
+  %i = bitcast float %f to i32
+  %r = sitofp i32 %i to float
+  ret float %r
+}
+
+define float @ucvtf_bitcast_f32_to_f32(float %f) nounwind {
+; CHECK-LABEL: ucvtf_bitcast_f32_to_f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ucvtf s0, s0
+; CHECK-NEXT:    ret
+  %i = bitcast float %f to i32
+  %r = uitofp i32 %i to float
+  ret float %r
+}
+
+define double @scvtf_bitcast_f64_to_f64(double %d) nounwind {
+; CHECK-LABEL: scvtf_bitcast_f64_to_f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    scvtf d0, d0
+; CHECK-NEXT:    ret
+  %i = bitcast double %d to i64
+  %r = sitofp i64 %i to double
+  ret double %r
+}
+
+define double @ucvtf_bitcast_f64_to_f64(double %d) nounwind {
+; CHECK-LABEL: ucvtf_bitcast_f64_to_f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ucvtf d0, d0
+; CHECK-NEXT:    ret
+  %i = bitcast double %d to i64
+  %r = uitofp i64 %i to double
+  ret double %r
+}
+
+;
+; Also test `strictfp` nodes
+;
+
+define double @scvtf_bitcast_f32_to_f64_strict(float %f) nounwind strictfp {
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Lukacma wrote:

This is lowered to normal sint_to_fp node not strict one. To test strict one you need to use @llvm.experimental.constrained.sitofp intrinsics.

https://github.com/llvm/llvm-project/pull/173272