[llvm] [AMDGPU] Definitions of new gfx1250 HW_REG_MODE fields. NFC. (PR #156527)

[Shilei Tian via llvm-commits]

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@@ -572,7 +572,17 @@ enum ModeRegisterMasks : uint32_t {
 
   GPR_IDX_EN_MASK = 1 << 27,
   VSKIP_MASK = 1 << 28,
-  CSP_MASK = 0x7u << 29 // Bits 29..31
+  CSP_MASK = 0x7u << 29, // Bits 29..31
+
+  // GFX1250
+  DST_VGPR_MSB = 1 << 12,
+  SRC0_VGPR_MSB = 1 << 13,
+  SRC1_VGPR_MSB = 1 << 14,
+  SRC2_VGPR_MSB = 1 << 15,
+  VGPR_MSB_MASK = 0xf << 12, // Bits 12..15
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shiltian wrote:

It seems like SPG says it is `bits[12:19]`?

https://github.com/llvm/llvm-project/pull/156527