[llvm] SelectionDAG: Do not propagate divergence through glue (PR #174766)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 7 05:02:40 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-llvm-selectiondag
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
Glue does not carry any value (in the LLVM IR Value sense) that could be
considered uniform or divergent.
---
Patch is 168.04 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/174766.diff
6 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+4-21)
- (modified) llvm/test/CodeGen/AMDGPU/dag-divergence.ll (+4-3)
- (modified) llvm/test/CodeGen/AMDGPU/div_i128.ll (+167-163)
- (modified) llvm/test/CodeGen/AMDGPU/div_v2i128.ll (+336-328)
- (modified) llvm/test/CodeGen/AMDGPU/fptoi.i128.ll (+262-256)
- (modified) llvm/test/CodeGen/AMDGPU/rem_i128.ll (+206-202)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 15f86cb94f958..a94a34b10a3f0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -12501,19 +12501,6 @@ class RAUOVWUpdateListener : public SelectionDAG::DAGUpdateListener {
} // end anonymous namespace
-/// Return true if a glue output should propagate divergence information.
-static bool gluePropagatesDivergence(const SDNode *Node) {
- switch (Node->getOpcode()) {
- case ISD::CopyFromReg:
- case ISD::CopyToReg:
- return false;
- default:
- return true;
- }
-
- llvm_unreachable("covered opcode switch");
-}
-
bool SelectionDAG::calculateDivergence(SDNode *N) {
if (TLI->isSDNodeAlwaysUniform(N)) {
assert(!TLI->isSDNodeSourceOfDivergence(N, FLI, UA) &&
@@ -12525,9 +12512,8 @@ bool SelectionDAG::calculateDivergence(SDNode *N) {
for (const auto &Op : N->ops()) {
EVT VT = Op.getValueType();
- // Skip Chain. It does not carry divergence.
- if (VT != MVT::Other && Op.getNode()->isDivergent() &&
- (VT != MVT::Glue || gluePropagatesDivergence(Op.getNode())))
+ // Skip Chain and Glue. They do not carry divergence.
+ if (VT != MVT::Other && VT != MVT::Glue && Op.getNode()->isDivergent())
return true;
}
return false;
@@ -14159,12 +14145,9 @@ void SelectionDAG::createOperands(SDNode *Node, ArrayRef<SDValue> Vals) {
Ops[I].setInitial(Vals[I]);
EVT VT = Ops[I].getValueType();
- // Skip Chain. It does not carry divergence.
- if (VT != MVT::Other &&
- (VT != MVT::Glue || gluePropagatesDivergence(Ops[I].getNode())) &&
- Ops[I].getNode()->isDivergent()) {
+ // Skip Chain and Glue. They do not carry divergence.
+ if (VT != MVT::Other && VT != MVT::Glue && Ops[I].getNode()->isDivergent())
IsDivergent = true;
- }
}
Node->NumOperands = Vals.size();
Node->OperandList = Ops;
diff --git a/llvm/test/CodeGen/AMDGPU/dag-divergence.ll b/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
index 39af6a05d2725..1669ac28a01cb 100644
--- a/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
+++ b/llvm/test/CodeGen/AMDGPU/dag-divergence.ll
@@ -80,12 +80,13 @@ define <2 x i128> @wide_carry_divergence_error(i128 %arg) {
; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3]
; GCN-NEXT: v_min_u32_e32 v4, v4, v5
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GCN-NEXT: s_subb_u32 s4, 0, 0
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GCN-NEXT: v_sub_u32_e32 v0, vcc, 0, v0
-; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: s_subb_u32 s5, 0, 0
; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_subb_u32_e32 v2, vcc, 0, v3, vcc
-; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT: v_mov_b32_e32 v2, s4
+; GCN-NEXT: v_mov_b32_e32 v3, s5
; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: v_mov_b32_e32 v5, 0
; GCN-NEXT: v_mov_b32_e32 v6, 0
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index d5b5ab6e457f9..798c88cf95585 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -24,7 +24,7 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, 0, v6, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, 0, v7, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[6:7]
-; GFX9-NEXT: v_ashrrev_i32_e32 v18, 31, v7
+; GFX9-NEXT: s_mov_b64 s[8:9], 0x7f
; GFX9-NEXT: v_cndmask_b32_e32 v21, v5, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v22, v4, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc
@@ -43,57 +43,60 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_u32_e32 v3, 32, v3
; GFX9-NEXT: v_ffbh_u32_e32 v4, v21
; GFX9-NEXT: v_min_u32_e32 v3, v3, v4
-; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: s_or_b64 s[6:7], vcc, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, 64, v3
-; GFX9-NEXT: v_addc_co_u32_e64 v4, s[6:7], 0, 0, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v4, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; GFX9-NEXT: v_ffbh_u32_e32 v6, v11
+; GFX9-NEXT: v_ffbh_u32_e32 v5, v11
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT: v_ffbh_u32_e32 v3, v10
; GFX9-NEXT: v_add_u32_e32 v3, 32, v3
-; GFX9-NEXT: v_min_u32_e32 v3, v3, v6
-; GFX9-NEXT: v_ffbh_u32_e32 v6, v8
-; GFX9-NEXT: v_add_u32_e32 v6, 32, v6
-; GFX9-NEXT: v_ffbh_u32_e32 v7, v9
-; GFX9-NEXT: v_min_u32_e32 v6, v6, v7
+; GFX9-NEXT: v_min_u32_e32 v3, v3, v5
+; GFX9-NEXT: v_ffbh_u32_e32 v5, v8
+; GFX9-NEXT: v_add_u32_e32 v5, 32, v5
+; GFX9-NEXT: v_ffbh_u32_e32 v6, v9
+; GFX9-NEXT: v_min_u32_e32 v5, v5, v6
; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 64, v6
-; GFX9-NEXT: v_addc_co_u32_e64 v7, s[6:7], 0, 0, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, 64, v5
+; GFX9-NEXT: v_addc_co_u32_e64 v6, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11]
-; GFX9-NEXT: v_mov_b32_e32 v5, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc
+; GFX9-NEXT: s_subb_u32 s4, 0, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v3
-; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v4, v7, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, 0, v5, vcc
-; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v19, v17
-; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v4, v6, vcc
+; GFX9-NEXT: s_subb_u32 s5, 0, 0
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3]
+; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9-NEXT: s_cselect_b64 s[8:9], -1, 0
+; GFX9-NEXT: s_cmp_eq_u64 s[4:5], 0
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[8:9]
+; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
+; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX9-NEXT: v_xor_b32_e32 v4, 0x7f, v2
+; GFX9-NEXT: v_or_b32_e32 v5, s5, v3
+; GFX9-NEXT: v_or_b32_e32 v4, s4, v4
+; GFX9-NEXT: s_or_b64 s[6:7], s[6:7], vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT: v_ashrrev_i32_e32 v18, 31, v7
+; GFX9-NEXT: s_xor_b64 s[8:9], s[6:7], -1
+; GFX9-NEXT: v_mov_b32_e32 v19, v17
; GFX9-NEXT: v_mov_b32_e32 v20, v18
-; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
-; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
-; GFX9-NEXT: v_xor_b32_e32 v6, 0x7f, v2
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v4
-; GFX9-NEXT: v_or_b32_e32 v7, v3, v5
-; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], vcc
-; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
-; GFX9-NEXT: s_xor_b64 s[6:7], s[4:5], -1
-; GFX9-NEXT: v_cndmask_b32_e64 v13, v11, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v12, v10, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, 0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5]
-; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], vcc
-; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v13, v11, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v10, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v9, 0, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, 0, s[6:7]
+; GFX9-NEXT: s_and_b64 s[6:7], s[8:9], vcc
+; GFX9-NEXT: s_and_saveexec_b64 s[8:9], s[6:7]
; GFX9-NEXT: s_cbranch_execz .LBB0_6
; GFX9-NEXT: ; %bb.1: ; %udiv-bb1
; GFX9-NEXT: v_add_co_u32_e32 v23, vcc, 1, v2
+; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_addc_co_u32_e32 v24, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v5, s5
; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, 0, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v7, 0x7f, v2
; GFX9-NEXT: v_addc_co_u32_e32 v26, vcc, 0, v5, vcc
@@ -197,20 +200,20 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[4:5]
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 31, v5
; GFX9-NEXT: v_or_b32_e32 v12, v12, v2
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v1
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v0
+; GFX9-NEXT: v_or_b32_e32 v4, v7, v1
+; GFX9-NEXT: v_or_b32_e32 v5, v6, v0
; GFX9-NEXT: .LBB0_6: ; %Flow3
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT: v_xor_b32_e32 v2, v18, v17
; GFX9-NEXT: v_xor_b32_e32 v3, v20, v19
-; GFX9-NEXT: v_xor_b32_e32 v0, v6, v2
-; GFX9-NEXT: v_xor_b32_e32 v1, v7, v3
+; GFX9-NEXT: v_xor_b32_e32 v0, v5, v2
+; GFX9-NEXT: v_xor_b32_e32 v1, v4, v3
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2
-; GFX9-NEXT: v_xor_b32_e32 v5, v12, v2
+; GFX9-NEXT: v_xor_b32_e32 v7, v12, v2
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
-; GFX9-NEXT: v_xor_b32_e32 v4, v13, v3
-; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v5, v2, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v4, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v6, v13, v3
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v7, v2, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v6, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-O0-LABEL: v_sdiv_i128_vv:
@@ -240,9 +243,7 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: v_writelane_b32 v30, s6, 0
; GFX9-O0-NEXT: v_writelane_b32 v30, s7, 1
; GFX9-O0-NEXT: s_mov_b32 s10, s6
-; GFX9-O0-NEXT: v_writelane_b32 v30, s10, 2
; GFX9-O0-NEXT: s_mov_b32 s11, s7
-; GFX9-O0-NEXT: v_writelane_b32 v30, s11, 3
; GFX9-O0-NEXT: v_sub_co_u32_e32 v5, vcc, s10, v1
; GFX9-O0-NEXT: v_mov_b32_e32 v0, s11
; GFX9-O0-NEXT: v_subb_co_u32_e32 v3, vcc, v0, v2, vcc
@@ -416,49 +417,49 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 killed $vgpr5_vgpr6 killed $exec
; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9
; GFX9-O0-NEXT: v_sub_co_u32_e32 v4, vcc, v4, v7
-; GFX9-O0-NEXT: v_subb_co_u32_e32 v8, vcc, v5, v6, vcc
-; GFX9-O0-NEXT: v_mov_b32_e32 v6, s10
-; GFX9-O0-NEXT: v_mov_b32_e32 v5, s10
-; GFX9-O0-NEXT: v_subb_co_u32_e32 v7, vcc, v5, v6, vcc
-; GFX9-O0-NEXT: v_mov_b32_e32 v6, s11
-; GFX9-O0-NEXT: v_mov_b32_e32 v5, s11
; GFX9-O0-NEXT: v_subb_co_u32_e32 v6, vcc, v5, v6, vcc
+; GFX9-O0-NEXT: s_subb_u32 s12, s10, s10
+; GFX9-O0-NEXT: s_subb_u32 s8, s11, s11
+; GFX9-O0-NEXT: ; kill: def $sgpr12 killed $sgpr12 def $sgpr12_sgpr13
+; GFX9-O0-NEXT: s_mov_b32 s13, s8
; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec
-; GFX9-O0-NEXT: v_mov_b32_e32 v5, v8
+; GFX9-O0-NEXT: v_mov_b32_e32 v5, v6
; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_nop 0
; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec
-; GFX9-O0-NEXT: v_mov_b32_e32 v8, v6
-; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: v_mov_b32_e32 v6, s12
+; GFX9-O0-NEXT: v_mov_b32_e32 v7, s13
+; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_nop 0
-; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: v_cmp_eq_u64_e64 s[8:9], v[7:8], s[6:7]
-; GFX9-O0-NEXT: s_mov_b64 s[12:13], 0x7f
-; GFX9-O0-NEXT: v_cmp_gt_u64_e64 s[14:15], v[4:5], s[12:13]
-; GFX9-O0-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[14:15]
-; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[14:15], v[7:8], s[6:7]
-; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[14:15]
-; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[8:9]
+; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: s_mov_b64 s[14:15], 0x7f
+; GFX9-O0-NEXT: v_cmp_gt_u64_e64 s[8:9], v[4:5], s[14:15]
+; GFX9-O0-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[8:9]
+; GFX9-O0-NEXT: s_cmp_lg_u64 s[12:13], s[6:7]
+; GFX9-O0-NEXT: s_cselect_b64 s[8:9], -1, 0
+; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[8:9]
+; GFX9-O0-NEXT: s_cmp_eq_u64 s[12:13], s[6:7]
+; GFX9-O0-NEXT: s_cselect_b64 s[8:9], -1, 0
+; GFX9-O0-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[8:9]
; GFX9-O0-NEXT: v_and_b32_e64 v6, 1, v6
; GFX9-O0-NEXT: v_cmp_eq_u32_e64 s[8:9], v6, 1
; GFX9-O0-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9]
-; GFX9-O0-NEXT: s_mov_b64 s[14:15], -1
+; GFX9-O0-NEXT: s_mov_b64 s[16:17], -1
; GFX9-O0-NEXT: s_mov_b64 s[4:5], s[8:9]
-; GFX9-O0-NEXT: s_xor_b64 s[4:5], s[4:5], s[14:15]
+; GFX9-O0-NEXT: s_xor_b64 s[4:5], s[4:5], s[16:17]
; GFX9-O0-NEXT: v_mov_b32_e32 v6, v5
-; GFX9-O0-NEXT: s_mov_b32 s14, s13
-; GFX9-O0-NEXT: v_xor_b32_e64 v6, v6, s14
-; GFX9-O0-NEXT: ; kill: def $sgpr12 killed $sgpr12 killed $sgpr12_sgpr13
-; GFX9-O0-NEXT: v_xor_b32_e64 v4, v4, s12
+; GFX9-O0-NEXT: s_mov_b32 s16, s15
+; GFX9-O0-NEXT: v_xor_b32_e64 v6, v6, s16
+; GFX9-O0-NEXT: ; kill: def $sgpr14 killed $sgpr14 killed $sgpr14_sgpr15
+; GFX9-O0-NEXT: v_xor_b32_e64 v4, v4, s14
; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec
; GFX9-O0-NEXT: v_mov_b32_e32 v5, v6
; GFX9-O0-NEXT: v_mov_b32_e32 v6, v5
-; GFX9-O0-NEXT: v_mov_b32_e32 v9, v8
-; GFX9-O0-NEXT: v_or_b32_e64 v6, v6, v9
+; GFX9-O0-NEXT: s_mov_b32 s14, s13
+; GFX9-O0-NEXT: v_or_b32_e64 v6, v6, s14
; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec
-; GFX9-O0-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-O0-NEXT: v_or_b32_e64 v4, v4, v5
+; GFX9-O0-NEXT: ; kill: def $sgpr12 killed $sgpr12 killed $sgpr12_sgpr13
+; GFX9-O0-NEXT: v_or_b32_e64 v4, v4, s12
; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec
; GFX9-O0-NEXT: v_mov_b32_e32 v5, v6
; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[6:7], v[4:5], s[6:7]
@@ -485,8 +486,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: s_nop 0
; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_mov_b64 s[4:5], exec
-; GFX9-O0-NEXT: v_writelane_b32 v30, s4, 4
-; GFX9-O0-NEXT: v_writelane_b32 v30, s5, 5
+; GFX9-O0-NEXT: v_writelane_b32 v30, s4, 2
+; GFX9-O0-NEXT: v_writelane_b32 v30, s5, 3
; GFX9-O0-NEXT: s_or_saveexec_b64 s[20:21], -1
; GFX9-O0-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_mov_b64 exec, s[20:21]
@@ -499,8 +500,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-O0-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-O0-NEXT: v_readlane_b32 s4, v30, 6
-; GFX9-O0-NEXT: v_readlane_b32 s5, v30, 7
+; GFX9-O0-NEXT: v_readlane_b32 s4, v30, 4
+; GFX9-O0-NEXT: v_readlane_b32 s5, v30, 5
; GFX9-O0-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-O0-NEXT: ; %bb.2: ; %Flow
; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -533,8 +534,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-O0-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-O0-NEXT: v_readlane_b32 s4, v30, 4
-; GFX9-O0-NEXT: v_readlane_b32 s5, v30, 5
+; GFX9-O0-NEXT: v_readlane_b32 s4, v30, 2
+; GFX9-O0-NEXT: v_readlane_b32 s5, v30, 3
; GFX9-O0-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -593,8 +594,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-O0-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-O0-NEXT: v_readlane_b32 s4, v30, 8
-; GFX9-O0-NEXT: v_readlane_b32 s5, v30, 9
+; GFX9-O0-NEXT: v_readlane_b32 s4, v30, 6
+; GFX9-O0-NEXT: v_readlane_b32 s5, v30, 7
; GFX9-O0-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
@@ -624,8 +625,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-O0-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-O0-NEXT: v_readlane_b32 s6, v30, 10
-; GFX9-O0-NEXT: v_readlane_b32 s7, v30, 11
+; GFX9-O0-NEXT: v_readlane_b32 s6, v30, 8
+; GFX9-O0-NEXT: v_readlane_b32 s7, v30, 9
; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
@@ -799,11 +800,11 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: s_nop 0
; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GFX9-O0-NEXT: v_writelane_b32 v30, s6, 6
-; GFX9-O0-NEXT: v_writelane_b32 v30, s7, 7
+; GFX9-O0-NEXT: v_writelane_b32 v30, s6, 4
+; GFX9-O0-NEXT: v_writelane_b32 v30, s7, 5
; GFX9-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GFX9-O0-NEXT: v_writelane_b32 v30, s6, 10
-; GFX9-O0-NEXT: v_writelane_b32 v30, s7, 11
+; GFX9-O0-NEXT: v_writelane_b32 v30, s6, 8
+; GFX9-O0-NEXT: v_writelane_b32 v30, s7, 9
; GFX9-O0-NEXT: s_or_saveexec_b64 s[20:21], -1
; GFX9-O0-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_mov_b64 exec, s[20:21]
@@ -927,8 +928,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_nop 0
; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: v_writelane_b32 v30, s4, 10
-; GFX9-O0-NEXT: v_writelane_b32 v30, s5, 11
+; GFX9-O0-NEXT: v_writelane_b32 v30, s4, 8
+; GFX9-O0-NEXT: v_writelane_b32 v30, s5, 9
; GFX9-O0-NEXT: s_or_saveexec_b64 s[20:21], -1
; GFX9-O0-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_mov_b64 exec, s[20:21]
@@ -1077,8 +1078,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-O0-NEXT: s_mov_b64 s[6:7], exec
; GFX9-O0-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
; GFX9-O0-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GFX9-O0-NEXT: v_writelane_b32 v30, s6, 8
-; GFX9-O0-NEXT: v_writelane_b32 v30, s7, 9
+; GFX9-O0-NEXT: v_writelane_b32 v30, s6, 6
+; GFX9-O0-NEXT: v_writelane_b32 v30, s7, 7
; GFX9-O0-NEXT: s_or_saveexec_b64 s[20:21], -1
; GFX9-O0-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_mov_b64 exec, s[20:21]
@@ -2239,9 +2240,9 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_add_u32_e32 v9, 32, v9
; GFX9-NEXT: v_ffbh_u32_e32 v10, v5
; GFX9-NEXT: v_min_u32_e32 v9, v9, v10
-; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: s_or_b64 s[6:7], vcc, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, 64, v9
-; GFX9-NEXT: v_addc_co_u32_e64 v10, s[6:7], 0, 0, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v10, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GFX9-NEXT: v_ffbh_u32_e32 v11, v3
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
@@ -2254,42 +2255,45 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-NEXT: v_min_u32_e32 v11, v11, v12
; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, 6...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/174766
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