[llvm] Revert "[llvm-exegesis] Add AArch64 operand initializers, SetRegTo" (PR #174729)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 7 01:51:43 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Cullen Rhodes (c-rhodes)
<details>
<summary>Changes</summary>
Reverts llvm/llvm-project#<!-- -->169912
Broke https://lab.llvm.org/buildbot/#/builders/24/builds/16298
---
Patch is 47.62 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/174729.diff
5 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64InstrFormats.td (-126)
- (modified) llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h (-2)
- (modified) llvm/test/tools/llvm-exegesis/AArch64/all-opcodes.test (+2-12)
- (modified) llvm/test/tools/llvm-exegesis/AArch64/setReg_init_check.s (-105)
- (modified) llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp (-127)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index a38eac6682567..d6221855a7962 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -389,14 +389,12 @@ def simm10Scaled : Operand<i64> {
let ParserMatchClass = SImm10s8Operand;
let DecoderMethod = "DecodeSImm<10>";
let PrintMethod = "printImmScale<8>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm9s16 : Operand<i64> {
let ParserMatchClass = SImmScaledMemoryIndexed<9, 16>;
let DecoderMethod = "DecodeSImm<9>";
let PrintMethod = "printImmScale<16>";
- let OperandType = "OPERAND_IMMEDIATE";
}
// uimm6 predicate - True if the immediate is in the range [0, 63].
@@ -407,22 +405,18 @@ def UImm6Operand : AsmOperandClass {
def uimm6 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = UImm6Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm16 : Operand<i16>, ImmLeaf<i16, [{return Imm >= 0 && Imm < 65536;}]>{
let ParserMatchClass = AsmImmRange<0, 65535>;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = UImm6Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = UImm6Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def CmpBranchUImm6Operand_32b
@@ -459,29 +453,24 @@ def UImm6Minus1Operand : AsmOperandClass {
def uimm6p1_32b : Operand<i32> {
let ParserMatchClass = UImm6Plus1Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6p1_64b : Operand<i64> {
let ParserMatchClass = UImm6Plus1Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6m1_32b : Operand<i32> {
let ParserMatchClass = UImm6Minus1Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6m1_64b : Operand<i64> {
let ParserMatchClass = UImm6Minus1Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def SImm9Operand : SImmOperand<9>;
def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
let ParserMatchClass = SImm9Operand;
let DecoderMethod = "DecodeSImm<9>";
- let OperandType = "OPERAND_IMMEDIATE";
}
// imm0_255 predicate - True if the immediate is in the range [0,255].
@@ -489,57 +478,48 @@ def Imm0_255Operand : AsmImmRange<0,255>;
def uimm8_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
let ParserMatchClass = Imm0_255Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm8_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 256; }]> {
let ParserMatchClass = Imm0_255Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def SImm8Operand : SImmOperand<8>;
def simm8_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -128 && Imm < 128; }]> {
let ParserMatchClass = SImm8Operand;
let DecoderMethod = "DecodeSImm<8>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm8_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -128 && Imm < 128; }]> {
let ParserMatchClass = SImm8Operand;
let DecoderMethod = "DecodeSImm<8>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def SImm6Operand : SImmOperand<6>;
def simm6_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -32 && Imm < 32; }]> {
let ParserMatchClass = SImm6Operand;
let DecoderMethod = "DecodeSImm<6>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def SImm5Operand : SImmOperand<5>;
def simm5_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -16 && Imm < 16; }]> {
let ParserMatchClass = SImm5Operand;
let DecoderMethod = "DecodeSImm<5>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm5_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -16 && Imm < 16; }]> {
let ParserMatchClass = SImm5Operand;
let DecoderMethod = "DecodeSImm<5>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm5_8b : Operand<i32>, ImmLeaf<i32, [{ return (int8_t)Imm >= -16 && (int8_t)Imm < 16; }]> {
let ParserMatchClass = SImm5Operand;
let DecoderMethod = "DecodeSImm<5>";
let PrintMethod = "printSImm<8>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm5_16b : Operand<i32>, ImmLeaf<i32, [{ return (int16_t)Imm >= -16 && (int16_t)Imm < 16; }]> {
let ParserMatchClass = SImm5Operand;
let DecoderMethod = "DecodeSImm<5>";
let PrintMethod = "printSImm<16>";
- let OperandType = "OPERAND_IMMEDIATE";
}
// simm7sN predicate - True if the immediate is a multiple of N in the range
@@ -552,19 +532,16 @@ def SImm7s16Operand : SImmScaledMemoryIndexed<7, 16>;
def simm7s4 : Operand<i32> {
let ParserMatchClass = SImm7s4Operand;
let PrintMethod = "printImmScale<4>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm7s8 : Operand<i32> {
let ParserMatchClass = SImm7s8Operand;
let PrintMethod = "printImmScale<8>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm7s16 : Operand<i32> {
let ParserMatchClass = SImm7s16Operand;
let PrintMethod = "printImmScale<16>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def am_sve_fi : ComplexPattern<iPTR, 2, "SelectAddrModeFrameIndexSVE", []>;
@@ -614,21 +591,18 @@ def uimm5s2 : Operand<i64>, ImmLeaf<i64,
UImmS2XForm> {
let ParserMatchClass = UImm5s2Operand;
let PrintMethod = "printImmScale<2>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm5s4 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); }],
UImmS4XForm> {
let ParserMatchClass = UImm5s4Operand;
let PrintMethod = "printImmScale<4>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm5s8 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); }],
UImmS8XForm> {
let ParserMatchClass = UImm5s8Operand;
let PrintMethod = "printImmScale<8>";
- let OperandType = "OPERAND_IMMEDIATE";
}
// tuimm5sN predicate - similar to uimm5sN, but use TImmLeaf (TargetConstant)
@@ -638,21 +612,18 @@ def tuimm5s2 : Operand<i64>, TImmLeaf<i64,
UImmS2XForm> {
let ParserMatchClass = UImm5s2Operand;
let PrintMethod = "printImmScale<2>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def tuimm5s4 : Operand<i64>, TImmLeaf<i64,
[{ return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); }],
UImmS4XForm> {
let ParserMatchClass = UImm5s4Operand;
let PrintMethod = "printImmScale<4>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def tuimm5s8 : Operand<i64>, TImmLeaf<i64,
[{ return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); }],
UImmS8XForm> {
let ParserMatchClass = UImm5s8Operand;
let PrintMethod = "printImmScale<8>";
- let OperandType = "OPERAND_IMMEDIATE";
}
// uimm6sN predicate - True if the immediate is a multiple of N in the range
@@ -665,31 +636,26 @@ def UImm6s16Operand : UImmScaledMemoryIndexed<6, 16>;
def uimm6s1 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = UImm6s1Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6s2 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); }]> {
let PrintMethod = "printImmScale<2>";
let ParserMatchClass = UImm6s2Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6s4 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); }]> {
let PrintMethod = "printImmScale<4>";
let ParserMatchClass = UImm6s4Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6s8 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); }]> {
let PrintMethod = "printImmScale<8>";
let ParserMatchClass = UImm6s8Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6s16 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); }]> {
let PrintMethod = "printImmScale<16>";
let ParserMatchClass = UImm6s16Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def SImmS2XForm : SDNodeXForm<imm, [{
@@ -714,7 +680,6 @@ def SImm6s1Operand : SImmScaledMemoryIndexed<6, 1>;
def simm6s1 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -32 && Imm < 32; }]> {
let ParserMatchClass = SImm6s1Operand;
let DecoderMethod = "DecodeSImm<6>";
- let OperandType = "OPERAND_IMMEDIATE";
}
// simm4sN predicate - True if the immediate is a multiple of N in the range
@@ -730,7 +695,6 @@ def simm4s1 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-8 && Imm <= 7; }]> {
let ParserMatchClass = SImm4s1Operand;
let DecoderMethod = "DecodeSImm<4>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm4s2 : Operand<i64>, ImmLeaf<i64,
@@ -738,7 +702,6 @@ def simm4s2 : Operand<i64>, ImmLeaf<i64,
let PrintMethod = "printImmScale<2>";
let ParserMatchClass = SImm4s2Operand;
let DecoderMethod = "DecodeSImm<4>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm4s3 : Operand<i64>, ImmLeaf<i64,
@@ -746,7 +709,6 @@ def simm4s3 : Operand<i64>, ImmLeaf<i64,
let PrintMethod = "printImmScale<3>";
let ParserMatchClass = SImm4s3Operand;
let DecoderMethod = "DecodeSImm<4>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm4s4 : Operand<i64>, ImmLeaf<i64,
@@ -754,21 +716,18 @@ def simm4s4 : Operand<i64>, ImmLeaf<i64,
let PrintMethod = "printImmScale<4>";
let ParserMatchClass = SImm4s4Operand;
let DecoderMethod = "DecodeSImm<4>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm4s16 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-128 && Imm <= 112 && (Imm % 16) == 0x0; }], SImmS16XForm> {
let PrintMethod = "printImmScale<16>";
let ParserMatchClass = SImm4s16Operand;
let DecoderMethod = "DecodeSImm<4>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def simm4s32 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-256 && Imm <= 224 && (Imm % 32) == 0x0; }], SImmS32XForm> {
let PrintMethod = "printImmScale<32>";
let ParserMatchClass = SImm4s32Operand;
let DecoderMethod = "DecodeSImm<4>";
- let OperandType = "OPERAND_IMMEDIATE";
}
def Imm1_8Operand : AsmImmRange<1, 8>;
@@ -798,7 +757,6 @@ def MovWSymbolG3AsmOperand : AsmOperandClass {
def movw_symbol_g3 : Operand<i32> {
let ParserMatchClass = MovWSymbolG3AsmOperand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def MovWSymbolG2AsmOperand : AsmOperandClass {
@@ -808,7 +766,6 @@ def MovWSymbolG2AsmOperand : AsmOperandClass {
def movw_symbol_g2 : Operand<i32> {
let ParserMatchClass = MovWSymbolG2AsmOperand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def MovWSymbolG1AsmOperand : AsmOperandClass {
@@ -818,7 +775,6 @@ def MovWSymbolG1AsmOperand : AsmOperandClass {
def movw_symbol_g1 : Operand<i32> {
let ParserMatchClass = MovWSymbolG1AsmOperand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def MovWSymbolG0AsmOperand : AsmOperandClass {
@@ -828,7 +784,6 @@ def MovWSymbolG0AsmOperand : AsmOperandClass {
def movw_symbol_g0 : Operand<i32> {
let ParserMatchClass = MovWSymbolG0AsmOperand;
- let OperandType = "OPERAND_IMMEDIATE";
}
class fixedpoint_i32<ValueType FloatVT>
@@ -837,7 +792,6 @@ class fixedpoint_i32<ValueType FloatVT>
let EncoderMethod = "getFixedPointScaleOpValue";
let DecoderMethod = "DecodeFixedPointScaleImm32";
let ParserMatchClass = Imm1_32Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
class fixedpoint_i64<ValueType FloatVT>
@@ -846,7 +800,6 @@ class fixedpoint_i64<ValueType FloatVT>
let EncoderMethod = "getFixedPointScaleOpValue";
let DecoderMethod = "DecodeFixedPointScaleImm64";
let ParserMatchClass = Imm1_64Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def fixedpoint_f16_i32 : fixedpoint_i32<f16>;
@@ -862,7 +815,6 @@ class fixedpoint_recip_i32<ValueType FloatVT>
ComplexPattern<FloatVT, 1, "SelectCVTFixedPosRecipOperand<32>", [fpimm, ld]> {
let EncoderMethod = "getFixedPointScaleOpValue";
let DecoderMethod = "DecodeFixedPointScaleImm32";
- let OperandType = "OPERAND_IMMEDIATE";
}
class fixedpoint_recip_i64<ValueType FloatVT>
@@ -870,7 +822,6 @@ class fixedpoint_recip_i64<ValueType FloatVT>
ComplexPattern<FloatVT, 1, "SelectCVTFixedPosRecipOperand<64>", [fpimm, ld]> {
let EncoderMethod = "getFixedPointScaleOpValue";
let DecoderMethod = "DecodeFixedPointScaleImm64";
- let OperandType = "OPERAND_IMMEDIATE";
}
def fixedpoint_recip_f16_i32 : fixedpoint_recip_i32<f16>;
@@ -887,7 +838,6 @@ def vecshiftR8 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR8OpValue";
let DecoderMethod = "DecodeVecShiftR8Imm";
let ParserMatchClass = Imm1_8Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR16 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
@@ -895,7 +845,6 @@ def vecshiftR16 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR16OpValue";
let DecoderMethod = "DecodeVecShiftR16Imm";
let ParserMatchClass = Imm1_16Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR16Narrow : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
@@ -903,7 +852,6 @@ def vecshiftR16Narrow : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR16OpValue";
let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
let ParserMatchClass = Imm1_8Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR32 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
@@ -911,7 +859,6 @@ def vecshiftR32 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR32OpValue";
let DecoderMethod = "DecodeVecShiftR32Imm";
let ParserMatchClass = Imm1_32Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR32Narrow : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
@@ -919,7 +866,6 @@ def vecshiftR32Narrow : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR32OpValue";
let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
let ParserMatchClass = Imm1_16Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR64 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
@@ -927,7 +873,6 @@ def vecshiftR64 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR64OpValue";
let DecoderMethod = "DecodeVecShiftR64Imm";
let ParserMatchClass = Imm1_64Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR64Narrow : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
@@ -935,7 +880,6 @@ def vecshiftR64Narrow : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR64OpValue";
let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
let ParserMatchClass = Imm1_32Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def Imm0_0Operand : AsmImmRange<0, 0>;
@@ -955,7 +899,6 @@ def vecshiftL8 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftL8OpValue";
let DecoderMethod = "DecodeVecShiftL8Imm";
let ParserMatchClass = Imm0_7Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftL16 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) < 16);
@@ -963,7 +906,6 @@ def vecshiftL16 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftL16OpValue";
let DecoderMethod = "DecodeVecShiftL16Imm";
let ParserMatchClass = Imm0_15Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftL32 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) < 32);
@@ -971,7 +913,6 @@ def vecshiftL32 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftL32OpValue";
let DecoderMethod = "DecodeVecShiftL32Imm";
let ParserMatchClass = Imm0_31Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftL64 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) < 64);
@@ -979,7 +920,6 @@ def vecshiftL64 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftL64OpValue";
let DecoderMethod = "DecodeVecShiftL64Imm";
let ParserMatchClass = Imm0_63Operand;
- let OperandType = "OPERAND_IMMEDIATE";
}
@@ -1279,8 +1219,6 @@ class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
let PrintMethod = "printShiftedRegister";
let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
- let OperandType = "OPERAND_SHIFTED_REGISTER";
- let OperandNamespace = "AArch64";
}
def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
@@ -1301,7 +1239,6 @@ class logical_shift<int width> : Operand<i32> {
let PrintMethod = "printShifter";
let ParserMatchClass = !cast<AsmOperandClass>(
"LogicalShifterOperand" # width);
- let OperandType = "OPERAND_IMMEDIATE";
}
def logical_shift32 : logical_shift<32>;
@@ -1312,8 +1249,6 @@ class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
let PrintMethod = "printShiftedRegister";
let MIOperandInfo = (ops regclass, shiftop);
- let OperandType = "OPERAND_SHIFTED_REGISTER";
- let OperandNamespace = "AArch64";
}
def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
@@ -1334,8 +1269,6 @@ def logical_vec_shift : Operand<i32> {
let PrintMethod = "printShifter";
let EncoderMethod = "getVecShifterOpValue";
let ParserMatchClass = LogicalVecShifterOperand;
- let OperandType = "OPERAND_SHIFTED_IMMEDIATE";
- let OperandNamespace = "AArch64";
}
// A logical vector half-word shifter operand:
@@ -1345,8 +1278,6 @@ def logical_vec_hw_shift : Operand<i32> {
let PrintMethod = "printShifter";
let EncoderMethod = "getVecShifterOpValue";
let ParserMatchClass = LogicalVecHalfWordShifterOperand;
- let OperandType = "OPERAND_SHIFTED_IMMEDIATE";
- let OperandNamespace = "AArch64";
}
// A vector move shifter operand:
@@ -1381,8 +1312,6 @@ class addsub_shifted_imm<ValueType Ty>
let EncoderMethod = "getAddSubImmOpValue";
let ParserMatchClass = AddSubImmOperand;
let MIOperandInfo = (ops i32imm, i32imm);
- let OperandType = "OPERAND_SHIFTED_IMMEDIATE";
- let OperandNamespace = "AArch64";
}
class addsub_shifted_imm_neg<ValueType Ty>
@@ -1390,8 +1319,6 @@ class addsub_shifted_imm_neg<ValueType Ty>
let EncoderMethod = "getAddSubImmOpValue";
let ParserMatchClass = AddSubImmNegOperand;
let MIOperandInfo = (ops i32imm, i32imm);
- let OperandType = "OPERAND_SHIFTED_IMMEDIATE";
- let OperandNamespace = "AArch64";
}
def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
@@ -1413,8 +1340,6 @@ class neg_addsub_shifted_imm<ValueType Ty>
let EncoderMethod = "getAddSubImmOpValue";
let ParserMatchClass = AddSubImmOperand;
let MIOperandInfo = (ops i32imm, i32imm);
- let OperandType = "OPERAND_SHIFTED_IMMEDIATE";
- let OperandNamespace = "AArch64";
}
def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
@@ -1434,35 +1359,28 @@ def gi_neg_addsub_shifted_imm64 :
def arith_extend : Operand<i32> {
let PrintMethod = "printArithExtend";
let ParserMatchClass = ExtendOperand;
- let OperandType = "OPERAND_IMMEDIATE";
}
def arith_extend64 : Operand<i32> {
let PrintMethod = "printArithExtend";
let ParserMatchClass = ExtendOperand64;
- let OperandType = "OPERAND_IMMEDIATE";
}
// 'extend' that's a lsl of a 64-bit register.
def arith_extendlsl64 : Operand<i32> {
let PrintMethod = "printArithExtend";
let ParserMatchClass = ExtendOperandLSL64;
- let OperandType = "OPERAND_IMMEDIATE";
}
class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
let PrintMethod = "printExtendedRegister";
let MIOperandInfo = (ops GPR32, arith_extend);
- let OperandType = "OPERAND_SHIFTED_REGISTER";
- let OperandNamespace = "AArch64";
}
class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
let PrintMethod = "printExtendedRegister";
let MIOperandInfo = (ops GPR32, arith_extend64);
- let OperandType = "OPERAND_SHIFTED_REGISTER";
- let OperandNamespace = "AArch64";
}
def arith_extended_reg32_i32 : ar...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/174729
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