[llvm] 01d34eb - [VPlan] Only use isAddressSCEVForCost in legacy getAddressAccSCEV (NFCI)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 6 11:18:37 PST 2026
Author: Florian Hahn
Date: 2026-01-06T19:18:13Z
New Revision: 01d34eb38fa0587cb95eedd3bada8257abc122f8
URL: https://github.com/llvm/llvm-project/commit/01d34eb38fa0587cb95eedd3bada8257abc122f8
DIFF: https://github.com/llvm/llvm-project/commit/01d34eb38fa0587cb95eedd3bada8257abc122f8.diff
LOG: [VPlan] Only use isAddressSCEVForCost in legacy getAddressAccSCEV (NFCI)
Follow-up to https://github.com/llvm/llvm-project/pull/171204 and
1f331e453f to only rely on isAddressSCEVForCost in legacy isAddressSCEVForCost,
completely aligning the decisions of VPlan and legacy cost model.
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 31c44fc46c973..1172908cb5d59 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5195,21 +5195,15 @@ InstructionCost LoopVectorizationCostModel::expectedCost(ElementCount VF) {
return Cost;
}
-/// Gets Address Access SCEV after verifying that the access pattern
-/// is loop invariant except the induction variable dependence.
+/// Gets the address access SCEV for Ptr, if it should be used for cost modeling
+/// according to isAddressSCEVForCost.
///
/// This SCEV can be sent to the Target in order to estimate the address
/// calculation cost.
static const SCEV *getAddressAccessSCEV(
Value *Ptr,
- LoopVectorizationLegality *Legal,
PredicatedScalarEvolution &PSE,
const Loop *TheLoop) {
-
- auto *Gep = dyn_cast<GetElementPtrInst>(Ptr);
- if (!Gep)
- return nullptr;
-
const SCEV *Addr = PSE.getSCEV(Ptr);
return vputils::isAddressSCEVForCost(Addr, *PSE.getSE(), TheLoop) ? Addr
: nullptr;
@@ -5234,7 +5228,7 @@ LoopVectorizationCostModel::getMemInstScalarizationCost(Instruction *I,
// Figure out whether the access is strided and get the stride value
// if it's known in compile time
- const SCEV *PtrSCEV = getAddressAccessSCEV(Ptr, Legal, PSE, TheLoop);
+ const SCEV *PtrSCEV = getAddressAccessSCEV(Ptr, PSE, TheLoop);
// Get the cost of the scalar memory instruction and address computation.
InstructionCost Cost = VF.getFixedValue() * TTI.getAddressComputationCost(
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
index 1ff6fe4b03c78..d6bf03e8e1d5e 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
@@ -426,31 +426,59 @@ define i32 @load_from_pointer_induction(ptr %start, ptr %end) {
; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[END1]], i64 [[START2]])
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], 1
; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 8
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 2
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 8
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]]
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]]
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP8:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP29:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP30:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 0
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 1
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 3
+; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 5
+; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 6
+; CHECK-NEXT: [[TMP32:%.*]] = add i64 [[INDEX]], 7
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP12]]
; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]]
+; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP31]]
+; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP6]]
+; CHECK-NEXT: [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP7]]
+; CHECK-NEXT: [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP8]]
+; CHECK-NEXT: [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP9]]
+; CHECK-NEXT: [[NEXT_GEP10:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP32]]
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[NEXT_GEP]], align 1
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[NEXT_GEP4]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP4]], 1
-; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP5]], 1
-; CHECK-NEXT: [[TMP8]] = or i32 [[VEC_PHI]], [[TMP6]]
-; CHECK-NEXT: [[TMP9]] = or i32 [[VEC_PHI3]], [[TMP7]]
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[NEXT_GEP5]], align 1
+; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[NEXT_GEP6]], align 1
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i32> [[TMP15]], i32 [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x i32> [[TMP16]], i32 [[TMP13]], i32 2
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x i32> [[TMP17]], i32 [[TMP14]], i32 3
+; CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[NEXT_GEP7]], align 1
+; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[NEXT_GEP8]], align 1
+; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[NEXT_GEP9]], align 1
+; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[NEXT_GEP10]], align 1
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i32> poison, i32 [[TMP19]], i32 0
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> [[TMP23]], i32 [[TMP20]], i32 1
+; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[TMP21]], i32 2
+; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP22]], i32 3
+; CHECK-NEXT: [[TMP27:%.*]] = and <4 x i32> [[TMP18]], splat (i32 1)
+; CHECK-NEXT: [[TMP28:%.*]] = and <4 x i32> [[TMP26]], splat (i32 1)
+; CHECK-NEXT: [[TMP29]] = or <4 x i32> [[VEC_PHI]], [[TMP27]]
+; CHECK-NEXT: [[TMP30]] = or <4 x i32> [[VEC_PHI3]], [[TMP28]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK: middle.block:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = or i32 [[TMP9]], [[TMP8]]
+; CHECK-NEXT: [[BIN_RDX1:%.*]] = or <4 x i32> [[TMP30]], [[TMP29]]
+; CHECK-NEXT: [[BIN_RDX:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[BIN_RDX1]])
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
@@ -504,5 +532,5 @@ exit:
; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]], [[META2]]}
; CHECK: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]]}
; CHECK: [[LOOP15]] = distinct !{[[LOOP15]], [[META1]], [[META2]]}
-; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]]}
+; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META2]], [[META1]]}
;.
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