[llvm] [X86] Don't check global nsz flag in x86ISel (PR #174627)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 6 09:39:31 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Mikołaj Piróg (mikolaj-pirog)
<details>
<summary>Changes</summary>
As in title. Tests are modified to rely only on the `nsz` IR flag
---
Patch is 121.47 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/174627.diff
13 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+12-16)
- (modified) llvm/test/CodeGen/X86/avx512-unsafe-fp-math.ll (+6-40)
- (modified) llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll (+49-74)
- (modified) llvm/test/CodeGen/X86/avx512fp16-fminimum-fmaximum.ll (+10-10)
- (modified) llvm/test/CodeGen/X86/avx512fp16-machine-combiner.ll (+18-18)
- (modified) llvm/test/CodeGen/X86/avx512fp16-unsafe-fp-math.ll (+9-9)
- (modified) llvm/test/CodeGen/X86/exedepsfix-broadcast.ll (+9-9)
- (modified) llvm/test/CodeGen/X86/fminimum-fmaximum.ll (+8-8)
- (modified) llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll (+8-8)
- (modified) llvm/test/CodeGen/X86/machine-combiner.ll (+38-38)
- (modified) llvm/test/CodeGen/X86/sse-minmax.ll (+426-962)
- (modified) llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll (+9-9)
- (modified) llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll (+9-9)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0883281edcf88..ddb11d7149e41 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -29674,8 +29674,7 @@ static SDValue LowerFMINIMUM_FMAXIMUM(SDValue Op, const X86Subtarget &Subtarget,
bool IsXNeverNaN = DAG.isKnownNeverNaN(X);
bool IsYNeverNaN = DAG.isKnownNeverNaN(Y);
- bool IgnoreSignedZero = DAG.getTarget().Options.NoSignedZerosFPMath ||
- Op->getFlags().hasNoSignedZeros() ||
+ bool IgnoreSignedZero = Op->getFlags().hasNoSignedZeros() ||
DAG.isKnownNeverZeroFloat(X) ||
DAG.isKnownNeverZeroFloat(Y);
SDValue NewX, NewY;
@@ -47937,6 +47936,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
SDValue Cond = N->getOperand(0);
SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2);
+ SelectionDAG::FlagInserter Inserter(DAG, N);
// Try simplification again because we use this function to optimize
// BLENDV nodes that are not handled by the generic combiner.
@@ -48054,7 +48054,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// the operands would cause it to handle comparisons between positive
// and negative zero incorrectly.
if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
- if (!DAG.getTarget().Options.NoSignedZerosFPMath &&
+ if (!(N->getFlags().hasNoSignedZeros()) &&
!(DAG.isKnownNeverZeroFloat(LHS) ||
DAG.isKnownNeverZeroFloat(RHS)))
break;
@@ -48065,7 +48065,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
case ISD::SETOLE:
// Converting this to a min would handle comparisons between positive
// and negative zero incorrectly.
- if (!DAG.getTarget().Options.NoSignedZerosFPMath &&
+ if (!N->getFlags().hasNoSignedZeros() &&
!DAG.isKnownNeverZeroFloat(LHS) && !DAG.isKnownNeverZeroFloat(RHS))
break;
Opcode = X86ISD::FMIN;
@@ -48084,7 +48084,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
case ISD::SETOGE:
// Converting this to a max would handle comparisons between positive
// and negative zero incorrectly.
- if (!DAG.getTarget().Options.NoSignedZerosFPMath &&
+ if (!N->getFlags().hasNoSignedZeros() &&
!DAG.isKnownNeverZeroFloat(LHS) && !DAG.isKnownNeverZeroFloat(RHS))
break;
Opcode = X86ISD::FMAX;
@@ -48094,7 +48094,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// the operands would cause it to handle comparisons between positive
// and negative zero incorrectly.
if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
- if (!DAG.getTarget().Options.NoSignedZerosFPMath &&
+ if (!N->getFlags().hasNoSignedZeros() &&
!(DAG.isKnownNeverZeroFloat(LHS) ||
DAG.isKnownNeverZeroFloat(RHS)))
break;
@@ -48121,7 +48121,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// Converting this to a min would handle comparisons between positive
// and negative zero incorrectly, and swapping the operands would
// cause it to handle NaNs incorrectly.
- if (!DAG.getTarget().Options.NoSignedZerosFPMath &&
+ if (!N->getFlags().hasNoSignedZeros() &&
!(DAG.isKnownNeverZeroFloat(LHS) ||
DAG.isKnownNeverZeroFloat(RHS))) {
if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
@@ -48157,7 +48157,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// Converting this to a max would handle comparisons between positive
// and negative zero incorrectly, and swapping the operands would
// cause it to handle NaNs incorrectly.
- if (!DAG.getTarget().Options.NoSignedZerosFPMath &&
+ if (!N->getFlags().hasNoSignedZeros() &&
!DAG.isKnownNeverZeroFloat(LHS) &&
!DAG.isKnownNeverZeroFloat(RHS)) {
if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
@@ -54613,10 +54613,6 @@ static SDValue combineFMulcFCMulc(SDNode *N, SelectionDAG &DAG,
// FADD(A, FMA(B, C, 0)) and FADD(A, FMUL(B, C)) to FMA(B, C, A)
static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
- auto HasNoSignedZero = [&DAG](const SDNodeFlags &Flags) {
- return DAG.getTarget().Options.NoSignedZerosFPMath ||
- Flags.hasNoSignedZeros();
- };
auto IsVectorAllNegativeZero = [&DAG](SDValue Op) {
APInt AI = APInt(32, 0x80008000);
KnownBits Bits = DAG.computeKnownBits(Op);
@@ -54636,8 +54632,8 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
SDValue RHS = N->getOperand(1);
bool IsConj;
SDValue FAddOp1, MulOp0, MulOp1;
- auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj, &IsVectorAllNegativeZero,
- &HasNoSignedZero](SDValue N) -> bool {
+ auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj,
+ &IsVectorAllNegativeZero](SDValue N) -> bool {
if (!N.hasOneUse() || N.getOpcode() != ISD::BITCAST)
return false;
SDValue Op0 = N.getOperand(0);
@@ -54651,7 +54647,7 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
}
if ((Opcode == X86ISD::VFMADDC || Opcode == X86ISD::VFCMADDC) &&
((ISD::isBuildVectorAllZeros(Op0->getOperand(2).getNode()) &&
- HasNoSignedZero(Op0->getFlags())) ||
+ Op0->getFlags().hasNoSignedZeros()) ||
IsVectorAllNegativeZero(Op0->getOperand(2)))) {
MulOp0 = Op0.getOperand(0);
MulOp1 = Op0.getOperand(1);
@@ -55802,7 +55798,7 @@ static SDValue combineFMinFMax(SDNode *N, SelectionDAG &DAG) {
// FMIN/FMAX are commutative if no NaNs and no negative zeros are allowed.
if (!DAG.getTarget().Options.NoNaNsFPMath ||
- !DAG.getTarget().Options.NoSignedZerosFPMath)
+ !N->getFlags().hasNoSignedZeros())
return SDValue();
// If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
diff --git a/llvm/test/CodeGen/X86/avx512-unsafe-fp-math.ll b/llvm/test/CodeGen/X86/avx512-unsafe-fp-math.ll
index eb9de8a9536d0..9ef4bc8887a07 100644
--- a/llvm/test/CodeGen/X86/avx512-unsafe-fp-math.ll
+++ b/llvm/test/CodeGen/X86/avx512-unsafe-fp-math.ll
@@ -1,16 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64 -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mattr=+avx512f | FileCheck %s --check-prefix=CHECK_UNSAFE
-; RUN: llc < %s -mtriple=x86_64 -enable-no-nans-fp-math -mattr=+avx512f | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64 -enable-no-signed-zeros-fp-math -mattr=+avx512f | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64 -mattr=+avx512f | FileCheck %s
; RUN: llc < %s -mtriple=x86_64 -mattr=+avx512f | FileCheck %s
define <16 x float> @test_max_v16f32(ptr %a_ptr, <16 x float> %b) {
-; CHECK_UNSAFE-LABEL: test_max_v16f32:
-; CHECK_UNSAFE: # %bb.0:
-; CHECK_UNSAFE-NEXT: vmaxps (%rdi), %zmm0, %zmm0
-; CHECK_UNSAFE-NEXT: retq
-;
; CHECK-LABEL: test_max_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %zmm1
@@ -18,16 +9,11 @@ define <16 x float> @test_max_v16f32(ptr %a_ptr, <16 x float> %b) {
; CHECK-NEXT: retq
%a = load <16 x float>, ptr %a_ptr
%tmp = fcmp fast ogt <16 x float> %a, %b
- %tmp4 = select <16 x i1> %tmp, <16 x float> %a, <16 x float> %b
+ %tmp4 = select fast <16 x i1> %tmp, <16 x float> %a, <16 x float> %b
ret <16 x float> %tmp4;
}
define <16 x float> @test_min_v16f32(ptr %a_ptr, <16 x float> %b) {
-; CHECK_UNSAFE-LABEL: test_min_v16f32:
-; CHECK_UNSAFE: # %bb.0:
-; CHECK_UNSAFE-NEXT: vminps (%rdi), %zmm0, %zmm0
-; CHECK_UNSAFE-NEXT: retq
-;
; CHECK-LABEL: test_min_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %zmm1
@@ -35,16 +21,11 @@ define <16 x float> @test_min_v16f32(ptr %a_ptr, <16 x float> %b) {
; CHECK-NEXT: retq
%a = load <16 x float>, ptr %a_ptr
%tmp = fcmp fast olt <16 x float> %a, %b
- %tmp4 = select <16 x i1> %tmp, <16 x float> %a, <16 x float> %b
+ %tmp4 = select fast <16 x i1> %tmp, <16 x float> %a, <16 x float> %b
ret <16 x float> %tmp4;
}
define <8 x double> @test_max_v8f64(ptr %a_ptr, <8 x double> %b) {
-; CHECK_UNSAFE-LABEL: test_max_v8f64:
-; CHECK_UNSAFE: # %bb.0:
-; CHECK_UNSAFE-NEXT: vmaxpd (%rdi), %zmm0, %zmm0
-; CHECK_UNSAFE-NEXT: retq
-;
; CHECK-LABEL: test_max_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %zmm1
@@ -52,16 +33,11 @@ define <8 x double> @test_max_v8f64(ptr %a_ptr, <8 x double> %b) {
; CHECK-NEXT: retq
%a = load <8 x double>, ptr %a_ptr
%tmp = fcmp fast ogt <8 x double> %a, %b
- %tmp4 = select <8 x i1> %tmp, <8 x double> %a, <8 x double> %b
+ %tmp4 = select fast <8 x i1> %tmp, <8 x double> %a, <8 x double> %b
ret <8 x double> %tmp4;
}
define <8 x double> @test_min_v8f64(ptr %a_ptr, <8 x double> %b) {
-; CHECK_UNSAFE-LABEL: test_min_v8f64:
-; CHECK_UNSAFE: # %bb.0:
-; CHECK_UNSAFE-NEXT: vminpd (%rdi), %zmm0, %zmm0
-; CHECK_UNSAFE-NEXT: retq
-;
; CHECK-LABEL: test_min_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %zmm1
@@ -69,16 +45,11 @@ define <8 x double> @test_min_v8f64(ptr %a_ptr, <8 x double> %b) {
; CHECK-NEXT: retq
%a = load <8 x double>, ptr %a_ptr
%tmp = fcmp fast olt <8 x double> %a, %b
- %tmp4 = select <8 x i1> %tmp, <8 x double> %a, <8 x double> %b
+ %tmp4 = select fast <8 x i1> %tmp, <8 x double> %a, <8 x double> %b
ret <8 x double> %tmp4;
}
define float @test_min_f32(float %a, ptr %ptr) {
-; CHECK_UNSAFE-LABEL: test_min_f32:
-; CHECK_UNSAFE: # %bb.0: # %entry
-; CHECK_UNSAFE-NEXT: vminss (%rdi), %xmm0, %xmm0
-; CHECK_UNSAFE-NEXT: retq
-;
; CHECK-LABEL: test_min_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
@@ -87,16 +58,11 @@ define float @test_min_f32(float %a, ptr %ptr) {
entry:
%0 = load float, ptr %ptr
%1 = fcmp fast olt float %0, %a
- %2 = select i1 %1, float %0, float %a
+ %2 = select fast i1 %1, float %0, float %a
ret float %2
}
define double @test_max_f64(double %a, ptr %ptr) {
-; CHECK_UNSAFE-LABEL: test_max_f64:
-; CHECK_UNSAFE: # %bb.0: # %entry
-; CHECK_UNSAFE-NEXT: vmaxsd (%rdi), %xmm0, %xmm0
-; CHECK_UNSAFE-NEXT: retq
-;
; CHECK-LABEL: test_max_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
@@ -105,6 +71,6 @@ define double @test_max_f64(double %a, ptr %ptr) {
entry:
%0 = load double, ptr %ptr
%1 = fcmp fast ogt double %0, %a
- %2 = select i1 %1, double %0, double %a
+ %2 = select fast i1 %1, double %0, double %a
ret double %2
}
diff --git a/llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll b/llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll
index f1477b57375c4..2dd9f115022f2 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll
@@ -1,129 +1,86 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown --enable-no-signed-zeros-fp-math -mattr=avx512fp16,avx512vl | FileCheck %s --check-prefixes=CHECK,NO-SZ
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl | FileCheck %s --check-prefixes=CHECK,HAS-SZ
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl | FileCheck %s
; FADD(acc, FMA(a, b, +0.0)) can be combined to FMA(a, b, acc) if the nsz flag set.
define dso_local <32 x half> @test1(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
-; NO-SZ-LABEL: test1:
-; NO-SZ: # %bb.0: # %entry
-; NO-SZ-NEXT: vfcmaddcph %zmm2, %zmm1, %zmm0
-; NO-SZ-NEXT: retq
-;
-; HAS-SZ-LABEL: test1:
-; HAS-SZ: # %bb.0: # %entry
-; HAS-SZ-NEXT: vxorps %xmm3, %xmm3, %xmm3
-; HAS-SZ-NEXT: vfcmaddcph %zmm2, %zmm1, %zmm3
-; HAS-SZ-NEXT: vaddph %zmm0, %zmm3, %zmm0
-; HAS-SZ-NEXT: retq
+; CHECK-LABEL: test1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vfcmaddcph %zmm2, %zmm1, %zmm0
+; CHECK-NEXT: retq
entry:
%0 = bitcast <32 x half> %a to <16 x float>
%1 = bitcast <32 x half> %b to <16 x float>
- %2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
+ %2 = tail call contract nsz <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
%3 = bitcast <16 x float> %2 to <32 x half>
%add.i = fadd contract <32 x half> %3, %acc
ret <32 x half> %add.i
}
define dso_local <32 x half> @test2(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
-; NO-SZ-LABEL: test2:
-; NO-SZ: # %bb.0: # %entry
-; NO-SZ-NEXT: vfmaddcph %zmm2, %zmm1, %zmm0
-; NO-SZ-NEXT: retq
-;
-; HAS-SZ-LABEL: test2:
-; HAS-SZ: # %bb.0: # %entry
-; HAS-SZ-NEXT: vxorps %xmm3, %xmm3, %xmm3
-; HAS-SZ-NEXT: vfmaddcph %zmm2, %zmm1, %zmm3
-; HAS-SZ-NEXT: vaddph %zmm0, %zmm3, %zmm0
-; HAS-SZ-NEXT: retq
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vfmaddcph %zmm2, %zmm1, %zmm0
+; CHECK-NEXT: retq
entry:
%0 = bitcast <32 x half> %a to <16 x float>
%1 = bitcast <32 x half> %b to <16 x float>
- %2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
+ %2 = tail call contract nsz <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
%3 = bitcast <16 x float> %2 to <32 x half>
%add.i = fadd contract <32 x half> %3, %acc
ret <32 x half> %add.i
}
define dso_local <16 x half> @test3(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
-; NO-SZ-LABEL: test3:
-; NO-SZ: # %bb.0: # %entry
-; NO-SZ-NEXT: vfcmaddcph %ymm2, %ymm1, %ymm0
-; NO-SZ-NEXT: retq
-;
-; HAS-SZ-LABEL: test3:
-; HAS-SZ: # %bb.0: # %entry
-; HAS-SZ-NEXT: vxorps %xmm3, %xmm3, %xmm3
-; HAS-SZ-NEXT: vfcmaddcph %ymm2, %ymm1, %ymm3
-; HAS-SZ-NEXT: vaddph %ymm0, %ymm3, %ymm0
-; HAS-SZ-NEXT: retq
+; CHECK-LABEL: test3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vfcmaddcph %ymm2, %ymm1, %ymm0
+; CHECK-NEXT: retq
entry:
%0 = bitcast <16 x half> %a to <8 x float>
%1 = bitcast <16 x half> %b to <8 x float>
- %2 = tail call contract <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
+ %2 = tail call contract nsz <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
%3 = bitcast <8 x float> %2 to <16 x half>
%add.i = fadd contract <16 x half> %3, %acc
ret <16 x half> %add.i
}
define dso_local <16 x half> @test4(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
-; NO-SZ-LABEL: test4:
-; NO-SZ: # %bb.0: # %entry
-; NO-SZ-NEXT: vfmaddcph %ymm2, %ymm1, %ymm0
-; NO-SZ-NEXT: retq
-;
-; HAS-SZ-LABEL: test4:
-; HAS-SZ: # %bb.0: # %entry
-; HAS-SZ-NEXT: vxorps %xmm3, %xmm3, %xmm3
-; HAS-SZ-NEXT: vfmaddcph %ymm2, %ymm1, %ymm3
-; HAS-SZ-NEXT: vaddph %ymm0, %ymm3, %ymm0
-; HAS-SZ-NEXT: retq
+; CHECK-LABEL: test4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vfmaddcph %ymm2, %ymm1, %ymm0
+; CHECK-NEXT: retq
entry:
%0 = bitcast <16 x half> %a to <8 x float>
%1 = bitcast <16 x half> %b to <8 x float>
- %2 = tail call contract <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
+ %2 = tail call contract nsz <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
%3 = bitcast <8 x float> %2 to <16 x half>
%add.i = fadd contract <16 x half> %3, %acc
ret <16 x half> %add.i
}
define dso_local <8 x half> @test5(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
-; NO-SZ-LABEL: test5:
-; NO-SZ: # %bb.0: # %entry
-; NO-SZ-NEXT: vfcmaddcph %xmm2, %xmm1, %xmm0
-; NO-SZ-NEXT: retq
-;
-; HAS-SZ-LABEL: test5:
-; HAS-SZ: # %bb.0: # %entry
-; HAS-SZ-NEXT: vxorps %xmm3, %xmm3, %xmm3
-; HAS-SZ-NEXT: vfcmaddcph %xmm2, %xmm1, %xmm3
-; HAS-SZ-NEXT: vaddph %xmm0, %xmm3, %xmm0
-; HAS-SZ-NEXT: retq
+; CHECK-LABEL: test5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vfcmaddcph %xmm2, %xmm1, %xmm0
+; CHECK-NEXT: retq
entry:
%0 = bitcast <8 x half> %a to <4 x float>
%1 = bitcast <8 x half> %b to <4 x float>
- %2 = tail call contract <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
+ %2 = tail call contract nsz <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
%3 = bitcast <4 x float> %2 to <8 x half>
%add.i = fadd contract <8 x half> %3, %acc
ret <8 x half> %add.i
}
define dso_local <8 x half> @test6(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
-; NO-SZ-LABEL: test6:
-; NO-SZ: # %bb.0: # %entry
-; NO-SZ-NEXT: vfmaddcph %xmm2, %xmm1, %xmm0
-; NO-SZ-NEXT: retq
-;
-; HAS-SZ-LABEL: test6:
-; HAS-SZ: # %bb.0: # %entry
-; HAS-SZ-NEXT: vxorps %xmm3, %xmm3, %xmm3
-; HAS-SZ-NEXT: vfmaddcph %xmm2, %xmm1, %xmm3
-; HAS-SZ-NEXT: vaddph %xmm0, %xmm3, %xmm0
-; HAS-SZ-NEXT: retq
+; CHECK-LABEL: test6:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vfmaddcph %xmm2, %xmm1, %xmm0
+; CHECK-NEXT: retq
entry:
%0 = bitcast <8 x half> %a to <4 x float>
%1 = bitcast <8 x half> %b to <4 x float>
- %2 = tail call contract <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
+ %2 = tail call contract nsz <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
%3 = bitcast <4 x float> %2 to <8 x half>
%add.i = fadd contract <8 x half> %3, %acc
ret <8 x half> %add.i
@@ -214,6 +171,24 @@ entry:
ret <8 x half> %add.i
}
+; Rewrite shouldn't happen without nsz
+
+define dso_local <32 x half> @test19(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
+; CHECK-LABEL: test19:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
+; CHECK-NEXT: vfcmaddcph %zmm2, %zmm1, %zmm3
+; CHECK-NEXT: vaddph %zmm0, %zmm3, %zmm0
+; CHECK-NEXT: retq
+entry:
+ %0 = bitcast <32 x half> %a to <16 x float>
+ %1 = bitcast <32 x half> %b to <16 x float>
+ %2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
+ %3 = bitcast <16 x float> %2 to <32 x half>
+ %add.i = fadd contract <32 x half> %3, %acc
+ ret <32 x half> %add.i
+}
+
declare <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32 immarg)
declare <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32 immarg)
declare <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)
diff --git a/llvm/test/CodeGen/X86/avx512fp16-fminimum-fmaximum.ll b/llvm/test/CodeGen/X86/avx512fp16-fminimum-fmaximum.ll
index 53ac283170a5f..8c1f58e8a1c48 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-fminimum-fmaximum.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-fminimum-fmaximum.ll
@@ -29,12 +29,12 @@ define half @test_fminimum(half %x, half %y) {
ret half %z
}
-define <8 x half> @test_fminimum_v8f16(<8 x half> %x, <8 x half> %y) "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" {
+define <8 x half> @test_fminimum_v8f16(<8 x half> %x, <8 x half> %y) "no-nans-fp-math"="true" {
; CHECK-LABEL: test_fminimum_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vminph %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
- %r = call <8 x half> @llvm.minimum.v8f16(<8 x half> %x, <8 x half> %y)
+ %r = call nsz <8 x half> @llvm.minimum.v8f16(<8 ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/174627
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