[llvm] [RISCV] AIFoundry.org ET extensions for RISCV (PR #174571)

[Craig Topper via llvm-commits]

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+//===-- RISCVInstrFormatXET.td -----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Instruction formats for RISC-V extensions from AIFoundry.org ET (formerly
+// known as the ET-SoC-1 extensions by Esperanto Technologies).
+//
+//===----------------------------------------------------------------------===//
+
+def OPC_ET_MEM_PS      : RISCVOpcode<"ET_MEM_PS",  0b0001011>;
+def OPC_ET_IMM_PS      : RISCVOpcode<"ET_IMM_PS",  0b0011111>;
+def OPC_ET_IMM10_PI    : RISCVOpcode<"ET_IMM1_PI", 0b0111111>;
+def OPC_ET_OP3_PS      : RISCVOpcode<"ET_OP3_PS",  0b1011011>;
+def OPC_ET_IMM_PI      : RISCVOpcode<"ET_IMM_PI",  0b1011111>;
+def OPC_ET_CVT_PS      : RISCVOpcode<"ET_CVT_PS",  0b1110111>;
+def OPC_ET_OP_PS       : RISCVOpcode<"ET_OP_PS",   0b1111011>; // OPC_CUSTOM_3
+
+// Custom instruction formats
+def InstFormatET1   : InstFormat<18>;
+def InstFormatET2   : InstFormat<19>;
+def InstFormatET3   : InstFormat<20>;
+def InstFormatET4   : InstFormat<21>;
+def InstFormatET5   : InstFormat<22>;
+def InstFormatET6   : InstFormat<23>;
+def InstFormatET7   : InstFormat<24>;
+def InstFormatET8   : InstFormat<25>;
+def InstFormatET9   : InstFormat<26>;
+def InstFormatET10  : InstFormat<27>;
+def InstFormatET11  : InstFormat<28>;
+def InstFormatET12  : InstFormat<29>;
+def InstFormatET13  : InstFormat<30>;
+def InstFormatET14  : InstFormat<31>;
+
+// Transforms used for converting intrinsics to machine instructions
+def LO3   : SDNodeXForm<imm, [{ return transform_LO<3>(N); }]>;
+def LO12s : SDNodeXForm<imm, [{ return transform_LOs<12>(N); }]>;
+def LO20  : SDNodeXForm<imm, [{ return transform_LO<20>(N); }]>;
+def LO20s  : SDNodeXForm<imm, [{ return transform_LOs<20>(N); }]>;
+
+// Example: FSWIZZ.PS
+class RVInstET1<bits<7> funct7,RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatET1> {
+  bits<5> rd;
+  bits<5> rs1;
+  bits<8> imm;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = imm{7-3};
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = imm{2-0};
+  let Inst{11-7} = rd;
+  let Inst{6-0} = opcode.Value;
+}
+
+// Example: FADDI.PS
+class RVInstET2<bits<3> funct3,RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatET3> {
+  bits<10> imm;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = imm{9-5};
+  let Inst{26-25} = 0b10;
+  let Inst{24-20} = imm{4-0};
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = opcode.Value;
+}
+
+// Example: FADD.PS
+class RVInstET3<bits<7> funct7,RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatET3> {
+  bits<5> rd;
+  bits<5> rs1;
+  bits<5> rs2;
+  bits<3> rm;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = rm;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = opcode.Value;
+}
+
+// Example: FMADD.PS
+class RVInstET4<bits<2> funct2,RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatET4> {
+  bits<5> rd;
+  bits<5> rs1;
+  bits<5> rs2;
+  bits<5> rs3;
+  bits<3> rm;
+
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = rm;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = opcode.Value;
+}
+
+// Example: FMVZ.X.PS
+class RVInstET5<bits<7> funct7,bits<3> funct3,
+              RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatET5> {
+  bits<5> rd;
+  bits<5> rs1;
+  bits<3> idx;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-23} = 0;
+  let Inst{22-20} = idx;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = opcode.Value;
+}
+
+// Example: FSLLI.PS
+class RVInstET6<bits<3> funct3,RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
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topperc wrote:

Indent 2 more spaces

https://github.com/llvm/llvm-project/pull/174571