[llvm] [RISCV] AIFoundry.org ET extensions for RISCV (PR #174571)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 6 08:21:04 PST 2026
================
@@ -0,0 +1,786 @@
+//===-- RISCVInstrInfoXET.td ------------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Instruction definitions for RISC-V extensions from AIFoundry.org ET (formerly
+// known as the ET-SoC-1 extensions by Esperanto Technologies).
+//
+// The following conventions are used
+//
+// 1. Specific instruction formats are named
+//
+// RVInstET<#>
+//
+// where <#> is a number from 1 to 14. Each number corresponds to a template
+// fitting a given instruction and other similar ones, as defined in
+// RISCVInstrFormatsXET.td
+//
+// 2. Each masked vector instruction <INST> is handled with an ETOps<Operands>
+// multiclass defining one instruction and two pseudo instructions:
+//
+// - <INST>: regular masked vector instructions as described in the manual,
+// implicitly using M0 register for masking out destination register
+// elements.
+//
+// - <INST>_EX: masked vector pseudo-instruction explictly accepting M0 as
+// its last operand, as opposed to <INST> where the register dependency
+// is just implicit. In addition to the explicit operands accepted by
+// <INST>, we must add m0 as the last operand.
+//
+// The purpose of this instruction variant is to explicit mark the
+// dependency of m0 register contents on MIR.
+//
+// - <INST>_PASSTHRU_EX: Similar to <INST_EX>, but also making explicit the
+// dependency on the previous contents of the destination register.
+// In addition to the explicit operands accepted by <INST_EX>, we must add
+// the destination register as the first operand.
+//
+// Destination and first source operands are constrained to be assinged
+// the same physical register during register allocation.
+//
+// This variant should be the choice during instruction selection for
+// cases when m0 is not guaranteed to be all ones.
+//
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "XET" in {
+let Predicates = [HasXETsimd] in {
+
+// Guess: load two consecutive 16-bit floats...
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def FLQ2 : RVInstI<0b101, OPC_LOAD_FP,
+ (outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1),
+ "flq2", "$rd, ${imm12}(${rs1})">;
+
+// Guess: store two consecutive 16-bit floats...
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def FSQ2 : RVInstS<0b101, OPC_STORE_FP,
+ (outs),
+ (ins FPR256:$rs2, simm12_lo:$imm12, GPR:$rs1),
+ "fsq2", "$rs2, ${imm12}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+def FLW_PS : RVInstI<0b010, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1),
+ "flw.ps", "$rd, ${imm12}(${rs1})">;
+def FLW_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1, MR0:$m0), [],
+ "flw.ps", "$rd, ${imm12}(${rs1}), $m0">;
+def FLW_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, simm12_lo:$imm12, GPR:$rs1, MR0:$m0), [],
+ "flw.ps", "$rd, ${imm12}(${rs1}), $m0"> {
+ let Constraints = "$rd = $in";
+}
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+def FSW_PS : RVInstS<0b110, OPC_ET_MEM_PS,
+ (outs),
+ (ins FPR256:$rs2, simm12_lo:$imm12, GPR:$rs1),
+ "fsw.ps", "$rs2, ${imm12}(${rs1})">;
+def FSW_PS_EX : Pseudo<(outs),
+ (ins FPR256:$rs2, simm12_lo:$imm12, GPR:$rs1, MR0:$m0),
+ [], "fsw.ps", "$rs2, ${imm12}(${rs1}), $m0">;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+def FBC_PS : RVInstI<0b000, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1),
+ "fbc.ps", "$rd, ${imm12}(${rs1})">;
+def FBC_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1, MR0:$m0), [],
+ "fbc.ps", "$rd, ${imm12}(${rs1}), $m0">;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def FBCX_PS : RVInstI<0b011, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins GPR:$rs1),
+ "fbcx.ps", "$rd, ${rs1}"> {
+ let imm12 = 0;
+}
+def FBCX_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins GPR:$rs1, MR0:$m0),[],
+ "fbcx.ps", "$rd, ${rs1}, $m0">;
+def FBCX_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, GPR:$rs1, MR0:$m0),[],
+ "fbcx.ps", "$rd, ${rs1}, $m0"> {
+ let Constraints = "$rd = $in";
+}
+
+def FBCI_PS : RVInstU<OPC_ET_IMM_PS,
+ (outs FPR256:$rd),
+ (ins uimm20_lui:$imm20),
+ "fbci.ps", "$rd, $imm20"> ;
+
+def FBCI_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins uimm20_lui:$imm20, MR0:$m0), [],
+ "fbci.ps", "$rd, $imm20, $m0">;
+def FBCI_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, uimm20_lui:$imm20, MR0:$m0), [],
+ "fbci.ps", "$rd, $imm20, $m0"> {
+ let Constraints = "$rd = $in";
+}
+
+multiclass ETOpsRdF1R2G<bits<7> funct7, string opcodestr> {
+ def "" : RVInstR<funct7, 0b001, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, GPRMemZeroOffset:$rs2),
+ opcodestr, "$rd, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, ${rs1}, ${rs2}, $m0">;
+ def _PASSTHRU_EX : Pseudo<
+ (outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, ${rs1}, ${rs2}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+}
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+defm FGW_PS : ETOpsRdF1R2G<0b0110000, "fgw.ps">;
+defm FGH_PS : ETOpsRdF1R2G<0b0101000, "fgh.ps">;
+defm FGB_PS : ETOpsRdF1R2G<0b0100100, "fgb.ps">;
+}
+
+multiclass ETOpsR3R1R2<bits<7> funct7, bits<3> funct3, string opcodestr> {
+ def "" : RVInstET12<funct7, funct3, OPC_ET_MEM_PS,
----------------
topperc wrote:
2 space indentation
https://github.com/llvm/llvm-project/pull/174571
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