[llvm] [BOLT] Fix isCallCoveredByBTI and insertBTI assertions (PR #174600)
Gergely Bálint via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 6 06:49:04 PST 2026
https://github.com/bgergely0 created https://github.com/llvm/llvm-project/pull/174600
Use MCPlus::getNumPrimeOperands to check number of non-annotation
operands instead of getNumOperands.
>From 15dcecaac3696660b001dcc3dc85be0d051c910b Mon Sep 17 00:00:00 2001
From: Gergely Balint <gergely.balint at arm.com>
Date: Tue, 6 Jan 2026 14:43:00 +0000
Subject: [PATCH] [BOLT] Fix isCallCoveredByBTI and insertBTI assertions
Use MCPlus::getNumPrimeOperands to check number of non-annotation
operands instead of getNumOperands.
---
bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
index 03fb4ddc2f238..a30799d5f45d3 100644
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -2818,7 +2818,7 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
// x16 or x17. If the operand is not x16 or x17, it can be accepted by a BTI
// j or BTI jc (and not BTI c).
if (isIndirectBranch(Call)) {
- assert(Call.getNumOperands() == 1 &&
+ assert(MCPlus::getNumPrimeOperands(Call) == 1 &&
"Indirect branch needs to have 1 operand.");
assert(Call.getOperand(0).isReg() &&
"Indirect branch does not have a register operand.");
@@ -2856,7 +2856,7 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
// x16 or x17. If the operand is not x16 or x17, it can be accepted by a
// BTI j or BTI jc (and not BTI c).
if (isIndirectBranch(Call)) {
- assert(Call.getNumOperands() == 1 &&
+ assert(MCPlus::getNumPrimeOperands(Call) == 1 &&
"Indirect branch needs to have 1 operand.");
assert(Call.getOperand(0).isReg() &&
"Indirect branch does not have a register operand.");
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