[llvm] [ISel] Introduce llvm.clmul intrinsic (PR #168731)

[Ramkumar Ramachandra via llvm-commits]

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@@ -221,6 +223,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
   case ISD::VP_SDIV:
   case ISD::VP_SREM:     Res = PromoteIntRes_SExtIntBinOp(N); break;
 
+  case ISD::CLMUL:
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artagnon wrote:

I _think_ that when the upper bits don't matter, zext produces better codegen: I tried with SimpleBinOp, and it is indeed worse.

https://github.com/llvm/llvm-project/pull/168731