[llvm] [RISCV][MCA] Consolidate inputs for different SchedModel tests (PR #173926)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 29 14:17:05 PST 2025
https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/173926
>From 6f4bedf3d2b0ce4ec6a72f1e7a7839fef659da97 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Mon, 29 Dec 2025 11:37:04 -0800
Subject: [PATCH 1/2] [RISCV][MCA] Share input files among SchedModel tests of
different processors
---
.../test/tools/llvm-mca/RISCV/Inputs/atomic.s | 99 +
.../llvm-mca/RISCV/Inputs/floating-point.s | 90 +
.../tools/llvm-mca/RISCV/Inputs/integer.s | 81 +
.../tools/llvm-mca/RISCV/Inputs/mul-div.s | 13 +
.../llvm-mca/RISCV/Inputs/rvv/arithmetic.s | 2297 ++++++++
.../tools/llvm-mca/RISCV/Inputs/rvv/bitwise.s | 1453 +++++
.../llvm-mca/RISCV/Inputs/rvv/comparison.s | 901 ++++
.../llvm-mca/RISCV/Inputs/rvv/conversion.s | 591 +++
.../tools/llvm-mca/RISCV/Inputs/rvv/fma.s | 731 +++
.../test/tools/llvm-mca/RISCV/Inputs/rvv/fp.s | 1897 +++++++
.../tools/llvm-mca/RISCV/Inputs/rvv/mask.s | 618 +++
.../tools/llvm-mca/RISCV/Inputs/rvv/minmax.s | 362 ++
.../rvv-mul-div.s => Inputs/rvv/mul} | 0
.../llvm-mca/RISCV/Inputs/rvv/permutation.s | 1174 ++++
.../llvm-mca/RISCV/Inputs/rvv/reduction.s | 605 +++
.../llvm-mca/RISCV/Inputs/rvv/vle-vse-vlm.s | 178 +
.../llvm-mca/RISCV/Inputs/rvv/vlse-vsse.s | 96 +
.../llvm-mca/RISCV/Inputs/rvv/vlseg-vsseg.s | 1603 ++++++
.../llvm-mca/RISCV/Inputs/rvv/vlxe-vsxe.s | 191 +
.../tools/llvm-mca/RISCV/Inputs/rvv/zvbc.s | 25 +
llvm/test/tools/llvm-mca/RISCV/Inputs/zba.s | 9 +
llvm/test/tools/llvm-mca/RISCV/Inputs/zbb.s | 32 +
llvm/test/tools/llvm-mca/RISCV/Inputs/zbc.s | 4 +
llvm/test/tools/llvm-mca/RISCV/Inputs/zbs.s | 9 +
llvm/test/tools/llvm-mca/RISCV/Inputs/zfh.s | 21 +
.../test/tools/llvm-mca/RISCV/Inputs/zfhmin.s | 18 +
.../test/tools/llvm-mca/RISCV/Inputs/zicond.s | 5 +
.../llvm-mca/RISCV/SiFiveP400/atomic.test | 229 +
.../tools/llvm-mca/RISCV/SiFiveP400/div.s | 1009 ----
.../RISCV/SiFiveP400/floating-point.test | 173 +
.../llvm-mca/RISCV/SiFiveP400/integer.test | 165 +
.../tools/llvm-mca/RISCV/SiFiveP400/load.s | 61 -
.../llvm-mca/RISCV/SiFiveP400/mul-cpop.s | 60 -
.../llvm-mca/RISCV/SiFiveP400/mul-div.test | 79 +
.../RISCV/SiFiveP400/rvv/arithmetic.test | 4533 ++++++++++++++++
.../RISCV/SiFiveP400/rvv/bitwise.test | 2885 ++++++++++
.../RISCV/SiFiveP400/rvv/comparison.test | 1813 +++++++
.../RISCV/SiFiveP400/rvv/conversion.test | 1177 ++++
.../llvm-mca/RISCV/SiFiveP400/rvv/fma.test | 1465 +++++
.../llvm-mca/RISCV/SiFiveP400/rvv/fp.test | 3713 +++++++++++++
.../llvm-mca/RISCV/SiFiveP400/rvv/mask.test | 1257 +++++
.../llvm-mca/RISCV/SiFiveP400/rvv/minmax.test | 757 +++
.../RISCV/SiFiveP400/rvv/permutation.test | 2341 ++++++++
.../RISCV/SiFiveP400/rvv/reduction.test | 1229 +++++
.../RISCV/SiFiveP400/rvv/vle-vse-vlm.test | 373 ++
.../RISCV/SiFiveP400/rvv/vlse-vsse.test | 229 +
.../RISCV/SiFiveP400/rvv/vlseg-vsseg.test | 3133 +++++++++++
.../RISCV/SiFiveP400/rvv/vlxe-vsxe.test | 405 ++
.../RISCV/SiFiveP400/{ => rvv}/zvbb.s | 0
.../llvm-mca/RISCV/SiFiveP400/rvv/zvbc.test | 93 +
.../RISCV/SiFiveP400/{ => rvv}/zvkg.s | 0
.../RISCV/SiFiveP400/{ => rvv}/zvkned.s | 0
.../RISCV/SiFiveP400/{ => rvv}/zvknhb.s | 0
.../RISCV/SiFiveP400/{ => rvv}/zvksed.s | 0
.../RISCV/SiFiveP400/{ => rvv}/zvksh.s | 0
.../llvm-mca/RISCV/SiFiveP400/vislide-vx.s | 108 -
.../llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s | 542 --
.../llvm-mca/RISCV/SiFiveP400/vlse-vsse.s | 316 --
.../llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s | 4727 -----------------
.../llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s | 588 --
.../tools/llvm-mca/RISCV/SiFiveP400/vmv.s | 895 ----
.../tools/llvm-mca/RISCV/SiFiveP400/vreduce.s | 438 --
.../llvm-mca/RISCV/SiFiveP400/vrgather.s | 86 -
.../llvm-mca/RISCV/SiFiveP400/vshift-vmul.s | 132 -
.../tools/llvm-mca/RISCV/SiFiveP400/zba.test | 69 +
.../tools/llvm-mca/RISCV/SiFiveP400/zbb.test | 101 +
.../tools/llvm-mca/RISCV/SiFiveP400/zbs.test | 69 +
.../llvm-mca/RISCV/SiFiveP400/zfhmin.test | 73 +
.../tools/llvm-mca/RISCV/SiFiveP400/zvbc.s | 112 -
.../SpacemitX60/{atomic.s => atomic.test} | 102 +-
.../{floating-point.s => floating-point.test} | 182 +-
.../llvm-mca/RISCV/SpacemitX60/integer.s | 437 --
.../llvm-mca/RISCV/SpacemitX60/integer.test | 154 +
.../llvm-mca/RISCV/SpacemitX60/mul-div.test | 68 +
.../{rvv-arithmetic.s => rvv/arithmetic.test} | 2300 +-------
.../{rvv-bitwise.s => rvv/bitwise.test} | 1456 +----
.../{rvv-comparison.s => rvv/comparison.test} | 904 +---
.../{rvv-conversion.s => rvv/conversion.test} | 593 +--
.../SpacemitX60/{rvv-fma.s => rvv/fma.test} | 733 +--
.../SpacemitX60/{rvv-fp.s => rvv/fp.test} | 1899 +------
.../SpacemitX60/{rvv-mask.s => rvv/mask.test} | 620 +--
.../{rvv-minmax.s => rvv/minmax.test} | 364 +-
.../permutation.test} | 1176 +---
.../{rvv-reduction.s => rvv/reduction.test} | 608 +--
.../{vle-vse-vlm.s => rvv/vle-vse-vlm.test} | 180 +-
.../{vlse-vsse.s => rvv/vlse-vsse.test} | 98 +-
.../{vlseg-vsseg.s => rvv/vlseg-vsseg.test} | 1605 +-----
.../{vlxe-vsxe.s => rvv/vlxe-vsxe.test} | 194 +-
.../tools/llvm-mca/RISCV/SpacemitX60/zba.test | 58 +
.../tools/llvm-mca/RISCV/SpacemitX60/zbb.test | 90 +
.../tools/llvm-mca/RISCV/SpacemitX60/zbc.test | 48 +
.../tools/llvm-mca/RISCV/SpacemitX60/zbs.test | 58 +
.../tools/llvm-mca/RISCV/SpacemitX60/zfh.test | 72 +
.../llvm-mca/RISCV/SpacemitX60/zfhmin.test | 62 +
.../llvm-mca/RISCV/SpacemitX60/zicond.test | 50 +
95 files changed, 40141 insertions(+), 22508 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/atomic.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/floating-point.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/integer.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/mul-div.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/arithmetic.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/bitwise.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/comparison.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/conversion.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/fma.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/fp.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mask.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/minmax.s
rename llvm/test/tools/llvm-mca/RISCV/{SpacemitX60/rvv-mul-div.s => Inputs/rvv/mul} (100%)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/permutation.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/reduction.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vle-vse-vlm.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlse-vsse.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlseg-vsseg.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlxe-vsxe.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/zvbc.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/zba.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/zbb.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/zbc.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/zbs.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/zfh.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/zfhmin.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/zicond.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/atomic.test
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/floating-point.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/integer.test
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-div.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/arithmetic.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/bitwise.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/comparison.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/conversion.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/fma.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/fp.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/mask.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/minmax.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/permutation.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/reduction.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vle-vse-vlm.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlse-vsse.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlseg-vsseg.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlxe-vsxe.test
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP400/{ => rvv}/zvbb.s (100%)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvbc.test
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP400/{ => rvv}/zvkg.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP400/{ => rvv}/zvkned.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP400/{ => rvv}/zvknhb.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP400/{ => rvv}/zvksed.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP400/{ => rvv}/zvksh.s (100%)
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vreduce.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vrgather.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vshift-vmul.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zba.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zbb.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zbs.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zfhmin.test
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbc.s
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{atomic.s => atomic.test} (91%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{floating-point.s => floating-point.test} (65%)
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/mul-div.test
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{rvv-arithmetic.s => rvv/arithmetic.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{rvv-bitwise.s => rvv/bitwise.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{rvv-comparison.s => rvv/comparison.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{rvv-conversion.s => rvv/conversion.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{rvv-fma.s => rvv/fma.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{rvv-fp.s => rvv/fp.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{rvv-mask.s => rvv/mask.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{rvv-minmax.s => rvv/minmax.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{rvv-permutation.s => rvv/permutation.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{rvv-reduction.s => rvv/reduction.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{vle-vse-vlm.s => rvv/vle-vse-vlm.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{vlse-vsse.s => rvv/vlse-vsse.test} (90%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{vlseg-vsseg.s => rvv/vlseg-vsseg.test} (89%)
rename llvm/test/tools/llvm-mca/RISCV/SpacemitX60/{vlxe-vsxe.s => rvv/vlxe-vsxe.test} (89%)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zba.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbb.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbc.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbs.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zfh.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zfhmin.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zicond.test
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/atomic.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/atomic.s
new file mode 100644
index 0000000000000..bd61a6d64445a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/atomic.s
@@ -0,0 +1,99 @@
+# Zalrsc
+lr.w t0, (t1)
+lr.w.aq t1, (t2)
+lr.w.rl t2, (t3)
+lr.w.aqrl t3, (t4)
+sc.w t6, t5, (t4)
+sc.w.aq t5, t4, (t3)
+sc.w.rl t4, t3, (t2)
+sc.w.aqrl t3, t2, (t1)
+
+lr.d t0, (t1)
+lr.d.aq t1, (t2)
+lr.d.rl t2, (t3)
+lr.d.aqrl t3, (t4)
+sc.d t6, t5, (t4)
+sc.d.aq t5, t4, (t3)
+sc.d.rl t4, t3, (t2)
+sc.d.aqrl t3, t2, (t1)
+
+# Zaamo
+amoswap.w a4, ra, (s0)
+amoadd.w a1, a2, (a3)
+amoxor.w a2, a3, (a4)
+amoand.w a3, a4, (a5)
+amoor.w a4, a5, (a6)
+amomin.w a5, a6, (a7)
+amomax.w s7, s6, (s5)
+amominu.w s6, s5, (s4)
+amomaxu.w s5, s4, (s3)
+
+amoswap.w.aq a4, ra, (s0)
+amoadd.w.aq a1, a2, (a3)
+amoxor.w.aq a2, a3, (a4)
+amoand.w.aq a3, a4, (a5)
+amoor.w.aq a4, a5, (a6)
+amomin.w.aq a5, a6, (a7)
+amomax.w.aq s7, s6, (s5)
+amominu.w.aq s6, s5, (s4)
+amomaxu.w.aq s5, s4, (s3)
+
+amoswap.w.rl a4, ra, (s0)
+amoadd.w.rl a1, a2, (a3)
+amoxor.w.rl a2, a3, (a4)
+amoand.w.rl a3, a4, (a5)
+amoor.w.rl a4, a5, (a6)
+amomin.w.rl a5, a6, (a7)
+amomax.w.rl s7, s6, (s5)
+amominu.w.rl s6, s5, (s4)
+amomaxu.w.rl s5, s4, (s3)
+
+amoswap.w.aqrl a4, ra, (s0)
+amoadd.w.aqrl a1, a2, (a3)
+amoxor.w.aqrl a2, a3, (a4)
+amoand.w.aqrl a3, a4, (a5)
+amoor.w.aqrl a4, a5, (a6)
+amomin.w.aqrl a5, a6, (a7)
+amomax.w.aqrl s7, s6, (s5)
+amominu.w.aqrl s6, s5, (s4)
+amomaxu.w.aqrl s5, s4, (s3)
+
+amoswap.d a4, ra, (s0)
+amoadd.d a1, a2, (a3)
+amoxor.d a2, a3, (a4)
+amoand.d a3, a4, (a5)
+amoor.d a4, a5, (a6)
+amomin.d a5, a6, (a7)
+amomax.d s7, s6, (s5)
+amominu.d s6, s5, (s4)
+amomaxu.d s5, s4, (s3)
+
+amoswap.d.aq a4, ra, (s0)
+amoadd.d.aq a1, a2, (a3)
+amoxor.d.aq a2, a3, (a4)
+amoand.d.aq a3, a4, (a5)
+amoor.d.aq a4, a5, (a6)
+amomin.d.aq a5, a6, (a7)
+amomax.d.aq s7, s6, (s5)
+amominu.d.aq s6, s5, (s4)
+amomaxu.d.aq s5, s4, (s3)
+
+amoswap.d.rl a4, ra, (s0)
+amoadd.d.rl a1, a2, (a3)
+amoxor.d.rl a2, a3, (a4)
+amoand.d.rl a3, a4, (a5)
+amoor.d.rl a4, a5, (a6)
+amomin.d.rl a5, a6, (a7)
+amomax.d.rl s7, s6, (s5)
+amominu.d.rl s6, s5, (s4)
+amomaxu.d.rl s5, s4, (s3)
+
+amoswap.d.aqrl a4, ra, (s0)
+amoadd.d.aqrl a1, a2, (a3)
+amoxor.d.aqrl a2, a3, (a4)
+amoand.d.aqrl a3, a4, (a5)
+amoor.d.aqrl a4, a5, (a6)
+amomin.d.aqrl a5, a6, (a7)
+amomax.d.aqrl s7, s6, (s5)
+amominu.d.aqrl s6, s5, (s4)
+amomaxu.d.aqrl s5, s4, (s3)
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/floating-point.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/floating-point.s
new file mode 100644
index 0000000000000..ca3cd3ade5bba
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/floating-point.s
@@ -0,0 +1,90 @@
+# Floating-Point Load and Store Instructions
+## Single-Precision
+flw ft0, 0(a0)
+fsw ft0, 0(a0)
+
+## Double-Precision
+fld ft0, 0(a0)
+fsd ft0, 0(a0)
+
+# Floating-Point Computational Instructions
+## Single-Precision
+fadd.s f26, f27, f28
+fsub.s f29, f30, f31
+fmul.s ft0, ft1, ft2
+fdiv.s ft3, ft4, ft5
+fsqrt.s ft6, ft7
+fmin.s fa5, fa6, fa7
+fmax.s fs2, fs3, fs4
+fmadd.s f10, f11, f12, f31
+fmsub.s f14, f15, f16, f17
+fnmsub.s f18, f19, f20, f21
+fnmadd.s f22, f23, f24, f25
+
+## Double-Precision
+fadd.d f26, f27, f28
+fsub.d f29, f30, f31
+fmul.d ft0, ft1, ft2
+fdiv.d ft3, ft4, ft5
+fsqrt.d ft6, ft7
+fmin.d fa5, fa6, fa7
+fmax.d fs2, fs3, fs4
+fmadd.d f10, f11, f12, f31
+fmsub.d f14, f15, f16, f17
+fnmsub.d f18, f19, f20, f21
+fnmadd.d f22, f23, f24, f25
+
+# Floating-Point Conversion and Move Instructions
+## Single-Precision
+fcvt.w.s a0, fs5
+fcvt.wu.s a1, fs6
+fcvt.s.w ft11, a4
+fcvt.s.wu ft0, a5
+
+fcvt.l.s a0, ft0
+fcvt.lu.s a1, ft1
+fcvt.s.l ft2, a2
+fcvt.s.lu ft3, a3
+
+fmv.x.w a2, fs7
+fmv.w.x ft1, a6
+
+fsgnj.s fs1, fa0, fa1
+fsgnjn.s fa1, fa3, fa4
+
+## Double-Precision
+fcvt.wu.d a4, ft11
+fcvt.w.d a4, ft11
+fcvt.d.w ft0, a5
+fcvt.d.wu ft1, a6
+
+fcvt.s.d fs5, fs6
+fcvt.d.s fs7, fs8
+
+fcvt.l.d a0, ft0
+fcvt.lu.d a1, ft1
+fcvt.d.l ft3, a3
+fcvt.d.lu ft4, a4
+
+fmv.x.d a2, ft2
+fmv.d.x ft5, a5
+
+fsgnj.d fs1, fa0, fa1
+fsgnjn.d fa1, fa3, fa4
+
+# Floating-Point Compare Instructions
+## Single-Precision
+feq.s a1, fs8, fs9
+flt.s a2, fs10, fs11
+fle.s a3, ft8, ft9
+
+## Double-Precision
+feq.d a1, fs8, fs9
+flt.d a2, fs10, fs11
+fle.d a3, ft8, ft9
+
+# Floating-Point Classify Instruction
+## Single-Precision
+fclass.s a3, ft10
+## Double-Precision
+fclass.d a3, ft10
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/integer.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/integer.s
new file mode 100644
index 0000000000000..5f20853ec01bf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/integer.s
@@ -0,0 +1,81 @@
+# Integer Register-Immediate Instructions
+addi a0, a0, 1
+addiw a0, a0, 1
+slti a0, a0, 1
+sltiu a0, a0, 1
+
+andi a0, a0, 1
+ori a0, a0, 1
+xori a0, a0, 1
+
+slli a0, a0, 1
+srli a0, a0, 1
+srai a0, a0, 1
+slliw a0, a0, 1
+srliw a0, a0, 1
+sraiw a0, a0, 1
+
+lui a0, 1
+auipc a1, 1
+
+# Integer Register-Register Operations
+add a0, a0, a1
+addw a0, a0, a0
+slt a0, a0, a0
+sltu a0, a0, a0
+
+and a0, a0, a0
+or a0, a0, a0
+xor a0, a0, a0
+
+sll a0, a0, a0
+srl a0, a0, a0
+sra a0, a0, a0
+sllw a0, a0, a0
+srlw a0, a0, a0
+sraw a0, a0, a0
+
+sub a0, a0, a0
+subw a0, a0, a0
+
+# Control Transfer Instructions
+
+## Unconditional Jumps
+jal a0, 1f
+1:
+jalr a0
+beq a0, a0, 1f
+1:
+bne a0, a0, 1f
+1:
+blt a0, a0, 1f
+1:
+bltu a0, a0, 1f
+1:
+bge a0, a0, 1f
+1:
+bgeu a0, a0, 1f
+1:
+add a0, a0, a0
+
+# Load and Store Instructions
+lb t0, 0(a0)
+lbu t0, 0(a0)
+lh t0, 0(a0)
+lhu t0, 0(a0)
+lw t0, 0(a0)
+lwu t0, 0(a0)
+ld t0, 0(a0)
+
+sb t0, 0(a0)
+sh t0, 0(a0)
+sw t0, 0(a0)
+sd t0, 0(a0)
+
+# Zicsr
+csrrw t0, 0xfff, t1
+csrrs s3, 0x001, s5
+csrrc sp, 0x000, ra
+csrrwi a5, 0x000, 0
+csrrsi t2, 0xfff, 31
+csrrci t1, 0x140, 5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/mul-div.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/mul-div.s
new file mode 100644
index 0000000000000..4221f74898f94
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/mul-div.s
@@ -0,0 +1,13 @@
+mul a0, a0, a0
+mulh a0, a0, a0
+mulhu a0, a0, a0
+mulhsu a0, a0, a0
+mulw a0, a0, a0
+div a0, a1, a2
+divu a0, a1, a2
+rem a0, a1, a2
+remu a0, a1, a2
+divw a0, a1, a2
+divuw a0, a1, a2
+remw a0, a1, a2
+remuw a0, a1, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/arithmetic.s
new file mode 100644
index 0000000000000..66dea1770efe9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/arithmetic.s
@@ -0,0 +1,2297 @@
+# Basic arithmetic operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vsub.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vsub.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
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+vmadc.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
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+vmadc.vv v8, v8, v8
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+vmadc.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmadc.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmadc.vvm v8, v8, v8, v0
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+vmadc.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vmadc.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vsetvli x28, x0, e32, m8, tu, mu
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+vmadc.vxm v8, v8, x30, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vmsbc.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsbc.vvm v8, v8, v8, v0
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+vmsbc.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vmsbc.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vsetvli x28, x0, e64, m8, tu, mu
+vmsbc.vxm v8, v8, x30, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vrsub.vi v8, v8, 12
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+vrsub.vi v8, v8, 12
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+vrsub.vi v8, v8, 12
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+vrsub.vi v8, v8, 12
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+vrsub.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vrsub.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vrsub.vx v8, v8, x30
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+vrsub.vx v8, v8, x30
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+vrsub.vx v8, v8, x30
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+vrsub.vx v8, v8, x30
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+vrsub.vx v8, v8, x30
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+vrsub.vx v8, v8, x30
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+vsetvli x28, x0, e16, m1, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vssub.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vssub.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwaddu.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwaddu.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwaddu.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwaddu.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwadd.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwadd.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwadd.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwsubu.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwsubu.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwsubu.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwsubu.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwsub.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwsub.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwsub.wx v8, v16, x30
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/bitwise.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/bitwise.s
new file mode 100644
index 0000000000000..6b771f9a4a96b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/bitwise.s
@@ -0,0 +1,1453 @@
+# Bitwise and logical operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vand.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vand.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vand.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vand.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vand.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vand.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vor.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vor.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vor.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vor.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vor.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vor.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vxor.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vxor.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vxor.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vxor.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vxor.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vxor.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vnsra.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vnsra.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vnsra.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vnsra.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vnsra.wi v8, v16, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vnsra.wi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vnsrl.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vnsrl.wv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vnsrl.wx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vnsrl.wx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vnsrl.wi v8, v16, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vnsrl.wi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vnclipu.wi v8, v16, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vnclipu.wi v8, v16, 12
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+vsra.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vsrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vsrl.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vsrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vsrl.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vsrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vsrl.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vssra.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vssra.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vssra.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vssra.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vssra.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vssra.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vssrl.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vssrl.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vssrl.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vssrl.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vssrl.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vssrl.vx v8, v8, x30
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/comparison.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/comparison.s
new file mode 100644
index 0000000000000..5127261850931
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/comparison.s
@@ -0,0 +1,901 @@
+# Comparison operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmseq.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmseq.vv v8, v8, v8
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+vsetvli x28, x0, e64, m8, tu, mu
+vmslt.vx v8, v8, x30
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/conversion.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/conversion.s
new file mode 100644
index 0000000000000..d99c0fbed019d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/conversion.s
@@ -0,0 +1,591 @@
+
+# Conversion operations
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vsext.vf2 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vsext.vf2 v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vzext.vf2 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vzext.vf2 v8, v16
+
+vsetvli x28, x0, e32, mf2, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vsext.vf4 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vsext.vf4 v8, v16
+
+vsetvli x28, x0, e32, mf2, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vzext.vf4 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vzext.vf4 v8, v16
+
+vsetvli x28, x0, e64, m1, tu, mu
+vsext.vf8 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vsext.vf8 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vsext.vf8 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vsext.vf8 v8, v16
+
+vsetvli x28, x0, e64, m1, tu, mu
+vzext.vf8 v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vzext.vf8 v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vzext.vf8 v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vzext.vf8 v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.f.xu.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.f.xu.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.f.x.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.f.x.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.rtz.x.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.rtz.xu.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.x.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.x.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfcvt.xu.f.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfcvt.xu.f.v v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.f.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.f.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.f.xu.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.f.xu.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.f.x.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.f.x.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.rod.f.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.rtz.x.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.rtz.xu.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.x.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.x.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfncvt.xu.f.w v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfncvt.xu.f.w v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.f.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.f.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.f.x.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.f.x.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.f.xu.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.f.xu.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.rtz.x.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.rtz.xu.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.x.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.x.f.v v8, v16
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vfwcvt.xu.f.v v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vfwcvt.xu.f.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/fma.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/fma.s
new file mode 100644
index 0000000000000..35a05a1ef53ec
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/fma.s
@@ -0,0 +1,731 @@
+
+# Fused multiply-add operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmacc.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmacc.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmacc.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmacc.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmadd.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmadd.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmadd.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsac.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsac.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsac.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsac.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsub.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vnmsub.vx v8, x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vnmsub.vx v8, x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccu.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccu.vx v8, x16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmacc.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmacc.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmacc.vx v8, x16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccsu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccsu.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccsu.vx v8, x16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmaccus.vx v8, x16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmaccus.vx v8, x16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmacc.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmacc.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmsac.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmsac.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmacc.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmacc.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmacc.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmacc.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmsac.vf v8, f16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmsac.vf v8, f16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwnmsac.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwnmsac.vv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/fp.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/fp.s
new file mode 100644
index 0000000000000..29040c523ca63
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/fp.s
@@ -0,0 +1,1897 @@
+
+# Floating point operations
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmfeq.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmfeq.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmfeq.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmfeq.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmfge.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmfge.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmfge.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmfge.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmfgt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmfgt.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmfgt.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmfgt.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmfle.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmfle.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmfle.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmfle.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmflt.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmflt.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmflt.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmflt.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vmfne.vf v8, v8, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vmfne.vf v8, v8, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmfne.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmfne.vv v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfadd.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfadd.vv v8, v8, v8
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+vsetvli x28, x0, e16, m1, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwadd.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwadd.vf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwadd.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwadd.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwadd.wf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwadd.wf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwadd.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwadd.wv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmul.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmul.vf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwmul.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.vf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.vv v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.wf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.wf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vfwsub.wv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vfwsub.wv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mask.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mask.s
new file mode 100644
index 0000000000000..b413052f15f88
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mask.s
@@ -0,0 +1,618 @@
+
+# Mask operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmand.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmand.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmnand.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmnand.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmandn.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmandn.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmxor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmxor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmnor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmorn.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmorn.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmxnor.mm v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmxnor.mm v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vmsbf.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vmsbf.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vmsif.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vmsif.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+vmsof.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+vmsof.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e8, m8, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e16, m8, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e32, m8, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m1, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m2, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m4, tu, mu
+vid.v v8
+vsetvli x28, x0, e64, m8, tu, mu
+vid.v v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vcpop.m x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vcpop.m x8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfirst.m x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfirst.m x8, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/minmax.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/minmax.s
new file mode 100644
index 0000000000000..66f2afd3b63ca
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/minmax.s
@@ -0,0 +1,362 @@
+
+# Min/max operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmax.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmax.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmax.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmax.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmaxu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmaxu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmaxu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmaxu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmin.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmin.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmin.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmin.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vminu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vminu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vminu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vminu.vx v8, v8, x30
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mul
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mul-div.s
rename to llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mul
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/permutation.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/permutation.s
new file mode 100644
index 0000000000000..7f63fd5c37ced
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/permutation.s
@@ -0,0 +1,1174 @@
+
+# Permutation and shuffle operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.v.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.v.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.v.x v8, x8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.v.x v8, x8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.v.i v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.v.i v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.x.s x8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.x.s x8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv.s.x v8, x8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv.s.x v8, x8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv1r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv1r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv2r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv2r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv4r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv4r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmv8r.v v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmv8r.v v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, mf4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, mf8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e8, m8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, mf2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, mf4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e16, m8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, mf2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e32, m8, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m1, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m2, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m4, tu, mu
+viota.m v8, v16
+vsetvli x28, x0, e64, m8, tu, mu
+viota.m v8, v16
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e8, m8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m1, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m2, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m4, tu, mu
+vcompress.vm v8, v16, v24
+vsetvli x28, x0, e64, m8, tu, mu
+vcompress.vm v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vslide1up.vx v8, v16, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vslide1up.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vslide1down.vx v8, v16, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vslide1down.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vslideup.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
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+vslidedown.vx v8, v16, x30
+
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+vslidedown.vi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
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+vrgather.vv v8, v16, v24
+vsetvli x28, x0, e64, m8, tu, mu
+vrgather.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
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+vrgather.vx v8, v16, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vrgather.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vrgather.vi v8, v16, 12
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+vrgather.vi v8, v16, 12
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+vrgather.vi v8, v16, 12
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+vrgather.vi v8, v16, 12
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+vrgather.vi v8, v16, 12
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+vrgather.vi v8, v16, 12
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+vrgather.vi v8, v16, 12
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+vrgather.vi v8, v16, 12
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+vrgather.vi v8, v16, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vrgather.vi v8, v16, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
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+
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+
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+vmerge.vim v8, v8, 12, v0
+
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+vmerge.vvm v8, v8, v8, v0
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+vmerge.vvm v8, v8, v8, v0
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+vmerge.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmerge.vxm v8, v8, x30, v0
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+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vmerge.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vmerge.vxm v8, v8, x30, v0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vfmerge.vfm v8, v8, ft0, v0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vfslide1down.vf v8, v16, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vfslide1down.vf v8, v16, ft0
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, mf4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m1, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e16, m8, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, mf2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m1, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e32, m8, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m1, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m2, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m4, tu, mu
+vfslide1up.vf v8, v16, ft0
+vsetvli x28, x0, e64, m8, tu, mu
+vfslide1up.vf v8, v16, ft0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/reduction.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/reduction.s
new file mode 100644
index 0000000000000..a4a013e36e09e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/reduction.s
@@ -0,0 +1,605 @@
+# Reduction operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredand.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredand.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredmaxu.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredmaxu.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredmax.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredminu.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredminu.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredmin.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredor.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredor.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredsum.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredsum.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vredxor.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vredxor.vs v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e8, m8, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwredsumu.vs v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vwredsumu.vs v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e8, m8, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e16, m8, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwredsum.vs v8, v16, v24
+vsetvli x28, x0, e32, m8, tu, mu
+vwredsum.vs v8, v16, v24
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredmax.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredmax.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredmin.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredmin.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredosum.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredosum.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vfredusum.vs v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vfredusum.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfwredosum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfwredosum.vs v8, v8, v8
+
+vsetvli x28, x0, e16, mf2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vfwredusum.vs v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vfwredusum.vs v8, v8, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vle-vse-vlm.s
new file mode 100644
index 0000000000000..87a511c88aacb
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vle-vse-vlm.s
@@ -0,0 +1,178 @@
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64.v v8, (a0)
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vse8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vse16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vse32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vse64.v v8, (a0)
+
+# Unit-stride mask load/store
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vlm.v v8, (a0)
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vsm.v v8, (a0)
+
+# Fault-only-first
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8ff.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16ff.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32ff.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlse-vsse.s
new file mode 100644
index 0000000000000..9435ffc2607e9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlse-vsse.s
@@ -0,0 +1,96 @@
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vlse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vlse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vlse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vlse64.v v8, (a0), t0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vsse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vsse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vsse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlseg-vsseg.s
new file mode 100644
index 0000000000000..725b92481a508
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlseg-vsseg.s
@@ -0,0 +1,1603 @@
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlseg2e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg3e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg4e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg5e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg6e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg7e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg7e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg7e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg8e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg8e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg8e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vsseg2e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg3e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg4e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg5e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg5e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg6e8.v v8,(a0)
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+vsoxseg6ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg7ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlxe-vsxe.s
new file mode 100644
index 0000000000000..66dc1956339ca
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlxe-vsxe.s
@@ -0,0 +1,191 @@
+vsetvli zero, zero, e8, mf8, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vluxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vluxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vluxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vluxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vloxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vloxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vloxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vloxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsuxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsuxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsuxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsuxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsoxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsoxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsoxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsoxei64.v v8, (a0), v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/zvbc.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/zvbc.s
new file mode 100644
index 0000000000000..7c3402255da1e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/zvbc.s
@@ -0,0 +1,25 @@
+# These instructions only work with e64
+
+vsetvli zero, zero, e64, m1, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m2, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m4, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m8, tu, mu
+vclmul.vv v8, v12, v24
+vclmul.vx v8, v12, a0
+vclmulh.vv v8, v12, v24
+vclmulh.vx v8, v12, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/zba.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/zba.s
new file mode 100644
index 0000000000000..63519a1b1ff45
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/zba.s
@@ -0,0 +1,9 @@
+
+add.uw a0, a0, a0
+slli.uw a0, a0, 1
+sh1add.uw a0, a0, a0
+sh2add.uw a0, a0, a0
+sh3add.uw a0, a0, a0
+sh1add a0, a0, a0
+sh2add a0, a0, a0
+sh3add a0, a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/zbb.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/zbb.s
new file mode 100644
index 0000000000000..9a6849e594e97
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/zbb.s
@@ -0,0 +1,32 @@
+
+andn a0, a0, a0
+orn a0, a0, a0
+xnor a0, a0, a0
+
+clz a0, a0
+clzw a0, a0
+ctz a0, a0
+ctzw a0, a0
+
+cpop a0, a0
+cpopw a0, a0
+
+min a0, a0, a0
+minu a0, a0, a0
+max a0, a0, a0
+maxu a0, a0, a0
+
+sext.b a0, a0
+sext.h a0, a0
+zext.h a0, a0
+
+rol a0, a0, a0
+rolw a0, a0, a0
+ror a0, a0, a0
+rorw a0, a0, a0
+rori a0, a0, 1
+roriw a0, a0, 1
+
+orc.b a0, a0
+
+rev8 a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/zbc.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/zbc.s
new file mode 100644
index 0000000000000..66f299cca2e68
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/zbc.s
@@ -0,0 +1,4 @@
+
+clmul a0, a0, a0
+clmulr a0, a0, a0
+clmulh a0, a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/zbs.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/zbs.s
new file mode 100644
index 0000000000000..5279f1577a127
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/zbs.s
@@ -0,0 +1,9 @@
+
+bclr a0, a1, a2
+bclri a0, a1, 1
+bext a0, a1, a2
+bexti a0, a1, 1
+binv a0, a1, a2
+binvi a0, a1, 1
+bset a0, a1, a2
+bseti a0, a1, 1
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/zfh.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/zfh.s
new file mode 100644
index 0000000000000..c6d721536b183
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/zfh.s
@@ -0,0 +1,21 @@
+
+# Floating-Point Computational Instructions
+fadd.h f26, f27, f28
+fsub.h f29, f30, f31
+fmul.h ft0, ft1, ft2
+fdiv.h ft3, ft4, ft5
+fsqrt.h ft6, ft7
+fmin.h fa5, fa6, fa7
+fmax.h fs2, fs3, fs4
+fmadd.h f10, f11, f12, f31
+fmsub.h f14, f15, f16, f17
+fnmsub.h f18, f19, f20, f21
+fnmadd.h f22, f23, f24, f25
+
+# Floating-Point Compare Instructions
+feq.h a1, fs8, fs9
+flt.h a2, fs10, fs11
+fle.h a3, ft8, ft9
+
+# Floating-Point Classify Instruction
+fclass.h a3, ft10
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/zfhmin.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/zfhmin.s
new file mode 100644
index 0000000000000..fdc6941f946a9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/zfhmin.s
@@ -0,0 +1,18 @@
+
+# Floating-Point Load and Store Instructions
+flh ft0, 0(a0)
+fsh ft0, 0(a0)
+
+# Floating-Point Conversion and Move Instructions
+fmv.x.h a2, fs7
+fmv.h.x ft1, a6
+
+fcvt.s.h fa0, ft0
+fcvt.s.h fa0, ft0, rup
+
+fcvt.h.s ft2, fa2
+fcvt.d.h fa0, ft0
+
+fcvt.d.h fa0, ft0, rup
+fcvt.h.d ft2, fa2
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/zicond.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/zicond.s
new file mode 100644
index 0000000000000..c37762b527245
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/zicond.s
@@ -0,0 +1,5 @@
+czero.eqz a0, a1, a2
+czero.nez a0, a1, a2
+
+czero.eqz a0, a1, a2
+czero.nez a0, a1, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/atomic.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/atomic.test
new file mode 100644
index 0000000000000..cfca325a4386c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/atomic.test
@@ -0,0 +1,229 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../Inputs/atomic.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Load LR_W lr.w t0, (t1)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Load LR_W_AQ lr.w.aq t1, (t2)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Load LR_W_RL lr.w.rl t2, (t3)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Load LR_W_AQRL lr.w.aqrl t3, (t4)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Store SC_W sc.w t6, t5, (t4)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Store SC_W_AQ sc.w.aq t5, t4, (t3)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Store SC_W_RL sc.w.rl t4, t3, (t2)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Store SC_W_AQRL sc.w.aqrl t3, t2, (t1)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Load LR_D lr.d t0, (t1)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Load LR_D_AQ lr.d.aq t1, (t2)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Load LR_D_RL lr.d.rl t2, (t3)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Load LR_D_AQRL lr.d.aqrl t3, (t4)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Store SC_D sc.d t6, t5, (t4)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Store SC_D_AQ sc.d.aq t5, t4, (t3)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Store SC_D_RL sc.d.rl t4, t3, (t2)
+# CHECK-NEXT: 1 3 1.00 * 3 SiFiveP400Store SC_D_AQRL sc.d.aqrl t3, t2, (t1)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOSWAP_W amoswap.w a4, ra, (s0)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOADD_W amoadd.w a1, a2, (a3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOXOR_W amoxor.w a2, a3, (a4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOAND_W amoand.w a3, a4, (a5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOOR_W amoor.w a4, a5, (a6)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMIN_W amomin.w a5, a6, (a7)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAX_W amomax.w s7, s6, (s5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMINU_W amominu.w s6, s5, (s4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAXU_W amomaxu.w s5, s4, (s3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOSWAP_W_AQ amoswap.w.aq a4, ra, (s0)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOADD_W_AQ amoadd.w.aq a1, a2, (a3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOXOR_W_AQ amoxor.w.aq a2, a3, (a4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOAND_W_AQ amoand.w.aq a3, a4, (a5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOOR_W_AQ amoor.w.aq a4, a5, (a6)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMIN_W_AQ amomin.w.aq a5, a6, (a7)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAX_W_AQ amomax.w.aq s7, s6, (s5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMINU_W_AQ amominu.w.aq s6, s5, (s4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAXU_W_AQ amomaxu.w.aq s5, s4, (s3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOSWAP_W_RL amoswap.w.rl a4, ra, (s0)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOADD_W_RL amoadd.w.rl a1, a2, (a3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOXOR_W_RL amoxor.w.rl a2, a3, (a4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOAND_W_RL amoand.w.rl a3, a4, (a5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOOR_W_RL amoor.w.rl a4, a5, (a6)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMIN_W_RL amomin.w.rl a5, a6, (a7)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAX_W_RL amomax.w.rl s7, s6, (s5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMINU_W_RL amominu.w.rl s6, s5, (s4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAXU_W_RL amomaxu.w.rl s5, s4, (s3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOSWAP_W_AQRL amoswap.w.aqrl a4, ra, (s0)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOADD_W_AQRL amoadd.w.aqrl a1, a2, (a3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOXOR_W_AQRL amoxor.w.aqrl a2, a3, (a4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOAND_W_AQRL amoand.w.aqrl a3, a4, (a5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOOR_W_AQRL amoor.w.aqrl a4, a5, (a6)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMIN_W_AQRL amomin.w.aqrl a5, a6, (a7)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAX_W_AQRL amomax.w.aqrl s7, s6, (s5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMINU_W_AQRL amominu.w.aqrl s6, s5, (s4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAXU_W_AQRL amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOSWAP_D amoswap.d a4, ra, (s0)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOADD_D amoadd.d a1, a2, (a3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOXOR_D amoxor.d a2, a3, (a4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOAND_D amoand.d a3, a4, (a5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOOR_D amoor.d a4, a5, (a6)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMIN_D amomin.d a5, a6, (a7)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAX_D amomax.d s7, s6, (s5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMINU_D amominu.d s6, s5, (s4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAXU_D amomaxu.d s5, s4, (s3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOSWAP_D_AQ amoswap.d.aq a4, ra, (s0)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOADD_D_AQ amoadd.d.aq a1, a2, (a3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOXOR_D_AQ amoxor.d.aq a2, a3, (a4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOAND_D_AQ amoand.d.aq a3, a4, (a5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOOR_D_AQ amoor.d.aq a4, a5, (a6)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMIN_D_AQ amomin.d.aq a5, a6, (a7)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAX_D_AQ amomax.d.aq s7, s6, (s5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMINU_D_AQ amominu.d.aq s6, s5, (s4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAXU_D_AQ amomaxu.d.aq s5, s4, (s3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOSWAP_D_RL amoswap.d.rl a4, ra, (s0)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOADD_D_RL amoadd.d.rl a1, a2, (a3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOXOR_D_RL amoxor.d.rl a2, a3, (a4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOAND_D_RL amoand.d.rl a3, a4, (a5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOOR_D_RL amoor.d.rl a4, a5, (a6)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMIN_D_RL amomin.d.rl a5, a6, (a7)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAX_D_RL amomax.d.rl s7, s6, (s5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMINU_D_RL amominu.d.rl s6, s5, (s4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAXU_D_RL amomaxu.d.rl s5, s4, (s3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOSWAP_D_AQRL amoswap.d.aqrl a4, ra, (s0)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOADD_D_AQRL amoadd.d.aqrl a1, a2, (a3)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOXOR_D_AQRL amoxor.d.aqrl a2, a3, (a4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOAND_D_AQRL amoand.d.aqrl a3, a4, (a5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOOR_D_AQRL amoor.d.aqrl a4, a5, (a6)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMIN_D_AQRL amomin.d.aqrl a5, a6, (a7)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAX_D_AQRL amomax.d.aqrl s7, s6, (s5)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMINU_D_AQRL amominu.d.aqrl s6, s5, (s4)
+# CHECK-NEXT: 1 3 1.00 * * 3 SiFiveP400Load AMOMAXU_D_AQRL amomaxu.d.aqrl s5, s4, (s3)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - - - 80.00 8.00 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lr.w t0, (t1)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lr.w.aq t1, (t2)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lr.w.rl t2, (t3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lr.w.aqrl t3, (t4)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sc.w t6, t5, (t4)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sc.w.aq t5, t4, (t3)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sc.w.rl t4, t3, (t2)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sc.w.aqrl t3, t2, (t1)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lr.d t0, (t1)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lr.d.aq t1, (t2)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lr.d.rl t2, (t3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lr.d.aqrl t3, (t4)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sc.d t6, t5, (t4)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sc.d.aq t5, t4, (t3)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sc.d.rl t4, t3, (t2)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sc.d.aqrl t3, t2, (t1)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoswap.w a4, ra, (s0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoadd.w a1, a2, (a3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoxor.w a2, a3, (a4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoand.w a3, a4, (a5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoor.w a4, a5, (a6)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomin.w a5, a6, (a7)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomax.w s7, s6, (s5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amominu.w s6, s5, (s4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomaxu.w s5, s4, (s3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoswap.w.aq a4, ra, (s0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoadd.w.aq a1, a2, (a3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoxor.w.aq a2, a3, (a4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoand.w.aq a3, a4, (a5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoor.w.aq a4, a5, (a6)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomin.w.aq a5, a6, (a7)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomax.w.aq s7, s6, (s5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amominu.w.aq s6, s5, (s4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomaxu.w.aq s5, s4, (s3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoswap.w.rl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoadd.w.rl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoxor.w.rl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoand.w.rl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoor.w.rl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomin.w.rl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomax.w.rl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amominu.w.rl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomaxu.w.rl s5, s4, (s3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoswap.w.aqrl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoadd.w.aqrl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoxor.w.aqrl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoand.w.aqrl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoor.w.aqrl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomin.w.aqrl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomax.w.aqrl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amominu.w.aqrl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoswap.d a4, ra, (s0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoadd.d a1, a2, (a3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoxor.d a2, a3, (a4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoand.d a3, a4, (a5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoor.d a4, a5, (a6)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomin.d a5, a6, (a7)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomax.d s7, s6, (s5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amominu.d s6, s5, (s4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomaxu.d s5, s4, (s3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoswap.d.aq a4, ra, (s0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoadd.d.aq a1, a2, (a3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoxor.d.aq a2, a3, (a4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoand.d.aq a3, a4, (a5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoor.d.aq a4, a5, (a6)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomin.d.aq a5, a6, (a7)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomax.d.aq s7, s6, (s5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amominu.d.aq s6, s5, (s4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomaxu.d.aq s5, s4, (s3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoswap.d.rl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoadd.d.rl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoxor.d.rl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoand.d.rl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoor.d.rl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomin.d.rl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomax.d.rl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amominu.d.rl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomaxu.d.rl s5, s4, (s3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoswap.d.aqrl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoadd.d.aqrl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoxor.d.aqrl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoand.d.aqrl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amoor.d.aqrl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomin.d.aqrl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomax.d.aqrl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amominu.d.aqrl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - amomaxu.d.aqrl s5, s4, (s3)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s
deleted file mode 100644
index 311310bc95982..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s
+++ /dev/null
@@ -1,1009 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, mf4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, mf2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, mf8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, mf4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, mf2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, mf8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, mf4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, mf2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, mf8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, mf4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, mf2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m8, tu, mu
-vdiv.vv v8, v16, v24
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, mf4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, mf2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, m2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, m4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, m8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, mf8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, mf4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, mf2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, m2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, m4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, m8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, mf8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, mf4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, mf2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, m2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, m4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, m8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, mf8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, mf4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, mf2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, m2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, m4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, m8, tu, mu
-vdiv.vx v8, v16, a0
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, mf4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, mf2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, mf8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, mf4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, mf2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, mf8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, mf4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, mf2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, mf8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, mf4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, mf2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m8, tu, mu
-vfdiv.vv v8, v16, v24
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, mf4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, mf2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, m2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, m4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, m8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, mf8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, mf4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, mf2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, m2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, m4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, m8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, mf8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, mf4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, mf2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, m2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, m4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, m8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, mf8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, mf4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, mf2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, m2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, m4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, m8, tu, mu
-vfdiv.vf v8, v16, fa0
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, m2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, m4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, m8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, mf8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, m2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, m4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, m8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, mf8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, mf4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, m2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, m4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, m8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, mf8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, mf4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, mf2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, m2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, m4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, m8, tu, mu
-vfsqrt.v v8, v16
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 320
-# CHECK-NEXT: Total Cycles: 19388
-# CHECK-NEXT: Total uOps: 320
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.02
-# CHECK-NEXT: IPC: 0.02
-# CHECK-NEXT: Block RThroughput: 14361.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 102 102.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 204 204.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 90 90.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 180 180.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 360 360.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 84 84.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 168 168.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 336 336.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 72 72.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 72 72.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 144 144.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 288 288.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 576 576.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 102 102.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 204 204.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 90 90.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 180 180.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 360 360.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 84 84.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 168 168.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 336 336.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 72 72.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 72 72.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 144 144.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 288 288.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 576 576.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 58 58.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 116 116.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 50 50.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 100 100.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 200 200.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 74 74.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 148 148.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 296 296.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 58 58.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 116 116.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 50 50.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 100 100.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 200 200.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 74 74.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 148 148.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 296 296.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 58 58.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 116 116.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 50 50.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 100 100.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 200 200.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 74 74.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 148 148.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 296 296.00 vfsqrt.v v8, v16
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 160.00 - - - 12186.00 725.00 14361.00 - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - 51.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - 51.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - 51.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - 51.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - 51.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - 102.00 2.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - 204.00 4.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - 408.00 8.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - 408.00 8.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - 45.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - 45.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - 45.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - 45.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - 90.00 2.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - 180.00 4.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - 360.00 8.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - 408.00 8.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - 408.00 8.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - 42.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - 42.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - 42.00 1.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - 84.00 2.00 - - - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - 168.00 4.00 - - - vdiv.vv v8, v16, v24
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-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 148.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 296.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 58.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 116.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 25.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 25.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 25.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 50.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 100.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 200.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 37.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 37.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 74.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 148.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 296.00 - - vfsqrt.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/floating-point.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/floating-point.test
new file mode 100644
index 0000000000000..b42624f586fca
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/floating-point.test
@@ -0,0 +1,173 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../Inputs/floating-point.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 5 1.00 * 5 SiFiveP400Load FLW flw ft0, 0(a0)
+# CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store FSW fsw ft0, 0(a0)
+# CHECK-NEXT: 1 5 1.00 * 5 SiFiveP400Load FLD fld ft0, 0(a0)
+# CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store FSD fsd ft0, 0(a0)
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FADD_S fadd.s fs10, fs11, ft8
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FSUB_S fsub.s ft9, ft10, ft11
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FMUL_S fmul.s ft0, ft1, ft2
+# CHECK-NEXT: 1 19 18.00 19 SiFiveP400FEXQ0,SiFiveP400FloatDiv[18] FDIV_S fdiv.s ft3, ft4, ft5
+# CHECK-NEXT: 1 18 17.00 18 SiFiveP400FEXQ0,SiFiveP400FloatDiv[17] FSQRT_S fsqrt.s ft6, ft7
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FMIN_S fmin.s fa5, fa6, fa7
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FMAX_S fmax.s fs2, fs3, fs4
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FMADD_S fmadd.s fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FMSUB_S fmsub.s fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FNMSUB_S fnmsub.s fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FNMADD_S fnmadd.s fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FADD_D fadd.d fs10, fs11, ft8
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FSUB_D fsub.d ft9, ft10, ft11
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FMUL_D fmul.d ft0, ft1, ft2
+# CHECK-NEXT: 1 33 32.00 33 SiFiveP400FEXQ0,SiFiveP400FloatDiv[32] FDIV_D fdiv.d ft3, ft4, ft5
+# CHECK-NEXT: 1 33 32.00 33 SiFiveP400FEXQ0,SiFiveP400FloatDiv[32] FSQRT_D fsqrt.d ft6, ft7
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FMIN_D fmin.d fa5, fa6, fa7
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FMAX_D fmax.d fs2, fs3, fs4
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FMADD_D fmadd.d fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FMSUB_D fmsub.d fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FNMSUB_D fnmsub.d fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400FEXQ0 FNMADD_D fnmadd.d fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_W_S fcvt.w.s a0, fs5
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_WU_S fcvt.wu.s a1, fs6
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FCVT_S_W fcvt.s.w ft11, a4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FCVT_S_WU fcvt.s.wu ft0, a5
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_L_S fcvt.l.s a0, ft0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_LU_S fcvt.lu.s a1, ft1
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FCVT_S_L fcvt.s.l ft2, a2
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FCVT_S_LU fcvt.s.lu ft3, a3
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FMV_X_W fmv.x.w a2, fs7
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FMV_W_X fmv.w.x ft1, a6
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FSGNJ_S fsgnj.s fs1, fa0, fa1
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FSGNJN_S fsgnjn.s fa1, fa3, fa4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_WU_D fcvt.wu.d a4, ft11
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_W_D fcvt.w.d a4, ft11
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FCVT_D_W fcvt.d.w ft0, a5
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FCVT_D_WU fcvt.d.wu ft1, a6
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_S_D fcvt.s.d fs5, fs6
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_D_S fcvt.d.s fs7, fs8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_L_D fcvt.l.d a0, ft0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_LU_D fcvt.lu.d a1, ft1
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FCVT_D_L fcvt.d.l ft3, a3
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FCVT_D_LU fcvt.d.lu ft4, a4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FMV_X_D fmv.x.d a2, ft2
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FMV_D_X fmv.d.x ft5, a5
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FSGNJ_D fsgnj.d fs1, fa0, fa1
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FSGNJN_D fsgnjn.d fa1, fa3, fa4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FEQ_S feq.s a1, fs8, fs9
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FLT_S flt.s a2, fs10, fs11
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FLE_S fle.s a3, ft8, ft9
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FEQ_D feq.d a1, fs8, fs9
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FLT_D flt.d a2, fs10, fs11
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FLE_D fle.d a3, ft8, ft9
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCLASS_S fclass.s a3, ft10
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCLASS_D fclass.d a3, ft10
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - 46.00 99.00 - - 10.00 2.00 2.00 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - flw ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - fsw ft0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - fld ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - fsd ft0, 0(a0)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fadd.s fs10, fs11, ft8
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fsub.s ft9, ft10, ft11
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmul.s ft0, ft1, ft2
+# CHECK-NEXT: - 1.00 18.00 - - - - - - - - - - fdiv.s ft3, ft4, ft5
+# CHECK-NEXT: - 1.00 17.00 - - - - - - - - - - fsqrt.s ft6, ft7
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmin.s fa5, fa6, fa7
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmax.s fs2, fs3, fs4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmadd.s fa0, fa1, fa2, ft11
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmsub.s fa4, fa5, fa6, fa7
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fnmsub.s fs2, fs3, fs4, fs5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fnmadd.s fs6, fs7, fs8, fs9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fadd.d fs10, fs11, ft8
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fsub.d ft9, ft10, ft11
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmul.d ft0, ft1, ft2
+# CHECK-NEXT: - 1.00 32.00 - - - - - - - - - - fdiv.d ft3, ft4, ft5
+# CHECK-NEXT: - 1.00 32.00 - - - - - - - - - - fsqrt.d ft6, ft7
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmin.d fa5, fa6, fa7
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmax.d fs2, fs3, fs4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmadd.d fa0, fa1, fa2, ft11
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmsub.d fa4, fa5, fa6, fa7
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fnmsub.d fs2, fs3, fs4, fs5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fnmadd.d fs6, fs7, fs8, fs9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.w.s a0, fs5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.wu.s a1, fs6
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcvt.s.w ft11, a4
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcvt.s.wu ft0, a5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.l.s a0, ft0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.lu.s a1, ft1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcvt.s.l ft2, a2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcvt.s.lu ft3, a3
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmv.x.w a2, fs7
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fmv.w.x ft1, a6
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fsgnj.s fs1, fa0, fa1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fsgnjn.s fa1, fa3, fa4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.wu.d a4, ft11
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.w.d a4, ft11
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcvt.d.w ft0, a5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcvt.d.wu ft1, a6
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.s.d fs5, fs6
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.d.s fs7, fs8
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.l.d a0, ft0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.lu.d a1, ft1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcvt.d.l ft3, a3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcvt.d.lu ft4, a4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmv.x.d a2, ft2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fmv.d.x ft5, a5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fsgnj.d fs1, fa0, fa1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fsgnjn.d fa1, fa3, fa4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - feq.s a1, fs8, fs9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - flt.s a2, fs10, fs11
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fle.s a3, ft8, ft9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - feq.d a1, fs8, fs9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - flt.d a2, fs10, fs11
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fle.d a3, ft8, ft9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fclass.s a3, ft10
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fclass.d a3, ft10
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/integer.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/integer.test
new file mode 100644
index 0000000000000..edef34cad3386
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/integer.test
@@ -0,0 +1,165 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ADDI addi a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ADDIW addiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLTI slti a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLTIU seqz a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ANDI andi a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith ORI ori a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith XORI xori a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_SLLI slli a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_SRLI srli a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_SRAI srai a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLLIW slliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRLIW srliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRAIW sraiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_LUI lui a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith AUIPC auipc a1, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ADD add a0, a0, a1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ADDW addw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLT slt a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLTU sltu a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_AND and a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_OR or a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_XOR xor a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLL sll a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRL srl a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRA sra a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLLW sllw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRLW srlw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRAW sraw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_SUB sub a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_SUBW subw a0, a0, a0
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith JAL jal a0, .Ltmp0
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith C_JALR jalr a0
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BEQ beq a0, a0, .Ltmp1
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BNE bne a0, a0, .Ltmp2
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BLT blt a0, a0, .Ltmp3
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BLTU bltu a0, a0, .Ltmp4
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BGE bge a0, a0, .Ltmp5
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BGEU bgeu a0, a0, .Ltmp6
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ADD add a0, a0, a0
+# CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LB lb t0, 0(a0)
+# CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LBU lbu t0, 0(a0)
+# CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LH lh t0, 0(a0)
+# CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LHU lhu t0, 0(a0)
+# CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LW lw t0, 0(a0)
+# CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LWU lwu t0, 0(a0)
+# CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LD ld t0, 0(a0)
+# CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store SB sb t0, 0(a0)
+# CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store SH sh t0, 0(a0)
+# CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store SW sw t0, 0(a0)
+# CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store SD sd t0, 0(a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRW csrrw t0, 4095, t1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRS csrrs s3, fflags, s5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRC csrrc sp, 0, ra
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRWI csrrwi a5, 0, 0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRSI csrrsi t2, 4095, 31
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRCI csrrci t1, sscratch, 5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - 18.33 16.33 10.33 7.00 4.00 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - addi a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - addiw a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - slti a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - seqz a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - andi a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - ori a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - xori a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - slli a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - srli a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - srai a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - slliw a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - srliw a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sraiw a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - lui a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - auipc a1, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - add a0, a0, a1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - addw a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - slt a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sltu a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - and a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - or a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - xor a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sll a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - srl a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sra a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sllw a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - srlw a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sraw a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sub a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - subw a0, a0, a0
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - jal a0, .Ltmp0
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - jalr a0
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - beq a0, a0, .Ltmp1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - bne a0, a0, .Ltmp2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - blt a0, a0, .Ltmp3
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - bltu a0, a0, .Ltmp4
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - bge a0, a0, .Ltmp5
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - bgeu a0, a0, .Ltmp6
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lb t0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lbu t0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lh t0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lhu t0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lw t0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lwu t0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - ld t0, 0(a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sb t0, 0(a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sh t0, 0(a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sw t0, 0(a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sd t0, 0(a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrw t0, 4095, t1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrs s3, fflags, s5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrc sp, 0, ra
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrwi a5, 0, 0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrsi t2, 4095, 31
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrci t1, sscratch, 5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
deleted file mode 100644
index 216d2f6c9b571..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
+++ /dev/null
@@ -1,61 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p450 -iterations=1 < %s | FileCheck %s
-
-lw t0, 0(a0)
-ld t0, 0(a0)
-
-flh ft0, 0(a0)
-flw ft0, 0(a0)
-fld ft0, 0(a0)
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 5
-# CHECK-NEXT: Total Cycles: 12
-# CHECK-NEXT: Total uOps: 5
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.42
-# CHECK-NEXT: IPC: 0.42
-# CHECK-NEXT: Block RThroughput: 5.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 4 1.00 * lw t0, 0(a0)
-# CHECK-NEXT: 1 4 1.00 * ld t0, 0(a0)
-# CHECK-NEXT: 1 5 1.00 * flh ft0, 0(a0)
-# CHECK-NEXT: 1 5 1.00 * flw ft0, 0(a0)
-# CHECK-NEXT: 1 5 1.00 * fld ft0, 0(a0)
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - - - 5.00 - - - - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - lw t0, 0(a0)
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - ld t0, 0(a0)
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - flh ft0, 0(a0)
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - flw ft0, 0(a0)
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - fld ft0, 0(a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s
deleted file mode 100644
index 5f7a1d1dce09b..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s
+++ /dev/null
@@ -1,60 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-mul s6, s6, s7
-
-mulw s4, s4, a2
-
-cpop t1, t1
-
-cpopw t2, t2
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 4
-# CHECK-NEXT: Total Cycles: 8
-# CHECK-NEXT: Total uOps: 4
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.50
-# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 4.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 2 1.00 mul s6, s6, s7
-# CHECK-NEXT: 1 2 1.00 mulw s4, s4, a2
-# CHECK-NEXT: 1 2 1.00 cpop t1, t1
-# CHECK-NEXT: 1 2 1.00 cpopw t2, t2
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - - 4.00 - - - - - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - mul s6, s6, s7
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - mulw s4, s4, a2
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - cpop t1, t1
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - cpopw t2, t2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-div.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-div.test
new file mode 100644
index 0000000000000..52d7c6884b72d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-div.test
@@ -0,0 +1,79 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../Inputs/mul-div.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith MUL mul a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith MULH mulh a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith MULHU mulhu a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith MULHSU mulhsu a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith MULW mulw a0, a0, a0
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP400Div[34],SiFiveP400IEXQ2,SiFiveP400IntArith DIV div a0, a1, a2
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP400Div[34],SiFiveP400IEXQ2,SiFiveP400IntArith DIVU divu a0, a1, a2
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP400Div[34],SiFiveP400IEXQ2,SiFiveP400IntArith REM rem a0, a1, a2
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP400Div[34],SiFiveP400IEXQ2,SiFiveP400IntArith REMU remu a0, a1, a2
+# CHECK-NEXT: 1 20 19.00 20 SiFiveP400Div[19],SiFiveP400IEXQ2,SiFiveP400IntArith DIVW divw a0, a1, a2
+# CHECK-NEXT: 1 20 19.00 20 SiFiveP400Div[19],SiFiveP400IEXQ2,SiFiveP400IntArith DIVUW divuw a0, a1, a2
+# CHECK-NEXT: 1 20 19.00 20 SiFiveP400Div[19],SiFiveP400IEXQ2,SiFiveP400IntArith REMW remw a0, a1, a2
+# CHECK-NEXT: 1 20 19.00 20 SiFiveP400Div[19],SiFiveP400IEXQ2,SiFiveP400IntArith REMUW remuw a0, a1, a2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 212.00 - - - - 13.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - mul a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - mulh a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - mulhu a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - mulhsu a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - mulw a0, a0, a0
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - div a0, a1, a2
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - divu a0, a1, a2
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - rem a0, a1, a2
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - remu a0, a1, a2
+# CHECK-NEXT: 19.00 - - - - 1.00 - - - - - - - divw a0, a1, a2
+# CHECK-NEXT: 19.00 - - - - 1.00 - - - - - - - divuw a0, a1, a2
+# CHECK-NEXT: 19.00 - - - - 1.00 - - - - - - - remw a0, a1, a2
+# CHECK-NEXT: 19.00 - - - - 1.00 - - - - - - - remuw a0, a1, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/arithmetic.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/arithmetic.test
new file mode 100644
index 0000000000000..d3f19e1a09f77
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/arithmetic.test
@@ -0,0 +1,4533 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/arithmetic.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWSUB_WX vwsub.wx v8, v16, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 1120.00 - - - - 3072.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vadd.vv v8, v8, v8
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsub.wx v8, v16, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/bitwise.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/bitwise.test
new file mode 100644
index 0000000000000..caf1736b57464
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/bitwise.test
@@ -0,0 +1,2885 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/bitwise.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP400VEXQ0[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP400VEXQ0[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSSRL_VX vssrl.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 708.00 - - - - 1908.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vand.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vxor.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnsra.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnsra.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnsra.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnsra.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnsra.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnsra.wi v8, v16, 12
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclipu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnclipu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclipu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclipu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnclipu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnclipu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclipu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclipu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnclipu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnclipu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclip.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclip.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclip.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclip.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vnclip.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vnclip.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclip.wi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vnclip.wi v8, v16, 12
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vssrl.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/comparison.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/comparison.test
new file mode 100644
index 0000000000000..d172b2cca21a6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/comparison.test
@@ -0,0 +1,1813 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/comparison.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMSLT_VX vmslt.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 440.00 - - - - 1320.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmseq.vv v8, v8, v8
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmslt.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/conversion.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/conversion.test
new file mode 100644
index 0000000000000..62096902f0bec
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/conversion.test
@@ -0,0 +1,1177 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/conversion.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 281.00 - - - - 731.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwcvt.xu.f.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/fma.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/fma.test
new file mode 100644
index 0000000000000..fd9e61eb50046
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/fma.test
@@ -0,0 +1,1465 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fma.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 353.00 - - - - 853.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmacc.vx v8, s0, v8
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+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwnmsac.vv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/fp.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/fp.test
new file mode 100644
index 0000000000000..af69a895620f7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/fp.test
@@ -0,0 +1,3713 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fp.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[58] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[116] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[232] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[25] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[25] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[50] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[100] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[200] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[37] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[74] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[148] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[296] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[58] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[116] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[232] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[25] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[25] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[50] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[100] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[200] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[37] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[74] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[148] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[296] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[58] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[116] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[232] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[25] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[25] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[50] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[100] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[200] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[37] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[74] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[148] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[296] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[29] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[58] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[116] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[232] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[25] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[25] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[50] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[100] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[200] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP400VEXQ0,SiFiveP400VFloatDiv[37] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP400VEXQ0[2],SiFiveP400VFloatDiv[74] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP400VEXQ0[4],SiFiveP400VFloatDiv[148] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP400VEXQ0[8],SiFiveP400VFloatDiv[296] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VFWSUB_WV vfwsub.wv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 915.00 - - - - 2774.00 5792.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfge.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmflt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmflt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmflt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmflt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmflt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmflt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmflt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmflt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfabs.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfabs.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfabs.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfabs.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfabs.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfabs.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfabs.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfabs.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfabs.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfabs.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwadd.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwadd.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwadd.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwadd.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwsub.wv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/mask.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/mask.test
new file mode 100644
index 0000000000000..c2084958394c0
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/mask.test
@@ -0,0 +1,1257 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mask.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFIRST_M vfirst.m s0, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 301.00 - - - - 345.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcpop.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcpop.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcpop.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcpop.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcpop.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfirst.m s0, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/minmax.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/minmax.test
new file mode 100644
index 0000000000000..f7bfa164c39da
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/minmax.test
@@ -0,0 +1,757 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/minmax.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMINU_VX vminu.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 176.00 - - - - 528.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vminu.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/permutation.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/permutation.test
new file mode 100644
index 0000000000000..e367fbbd4eafc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/permutation.test
@@ -0,0 +1,2341 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/permutation.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP400VEXQ0[10] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SiFiveP400VEXQ0[12] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP400VEXQ0[10] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SiFiveP400VEXQ0[12] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP400VEXQ0[10] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SiFiveP400VEXQ0[12] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP400VEXQ0[10] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SiFiveP400VEXQ0[12] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 11.00 11 SiFiveP400VEXQ0[11] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SiFiveP400VEXQ0[14] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP400VEXQ0[20] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 11.00 11 SiFiveP400VEXQ0[11] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SiFiveP400VEXQ0[14] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP400VEXQ0[20] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 11.00 11 SiFiveP400VEXQ0[11] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SiFiveP400VEXQ0[14] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP400VEXQ0[20] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 11.00 11 SiFiveP400VEXQ0[11] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SiFiveP400VEXQ0[14] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP400VEXQ0[20] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP400VEXQ0[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP400VEXQ0[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP400VEXQ0[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP400VEXQ0 VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP400VEXQ0[12] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP400VEXQ0[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP400VEXQ0[24] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 572.00 - - - - 2402.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv.v.i v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, s0
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vslide1down.vx v8, v16, t5
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vslideup.vi v8, v16, 12
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+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfslide1up.vf v8, v16, ft0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/reduction.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/reduction.test
new file mode 100644
index 0000000000000..abdef1704576e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/reduction.test
@@ -0,0 +1,1229 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/reduction.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SiFiveP400VEXQ0[5] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 SiFiveP400VEXQ0[6] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 9.00 14 SiFiveP400VEXQ0[9] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SiFiveP400VEXQ0[17] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SiFiveP400VEXQ0[5] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SiFiveP400VEXQ0[8] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 SiFiveP400VEXQ0[14] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP400VEXQ0[6] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 SiFiveP400VEXQ0[12] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP400VEXQ0[5] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 SiFiveP400VEXQ0[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SiFiveP400VEXQ0[5] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 SiFiveP400VEXQ0[6] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 9.00 14 SiFiveP400VEXQ0[9] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SiFiveP400VEXQ0[17] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SiFiveP400VEXQ0[5] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SiFiveP400VEXQ0[8] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 SiFiveP400VEXQ0[14] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP400VEXQ0[6] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 SiFiveP400VEXQ0[12] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP400VEXQ0[5] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 SiFiveP400VEXQ0[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SiFiveP400VEXQ0[5] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 SiFiveP400VEXQ0[6] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 9.00 14 SiFiveP400VEXQ0[9] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SiFiveP400VEXQ0[17] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SiFiveP400VEXQ0[5] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SiFiveP400VEXQ0[8] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 SiFiveP400VEXQ0[14] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP400VEXQ0[6] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 SiFiveP400VEXQ0[12] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP400VEXQ0[5] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 SiFiveP400VEXQ0[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SiFiveP400VEXQ0[5] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 SiFiveP400VEXQ0[6] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 9.00 14 SiFiveP400VEXQ0[9] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SiFiveP400VEXQ0[17] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SiFiveP400VEXQ0[5] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SiFiveP400VEXQ0[8] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 15 SiFiveP400VEXQ0[14] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SiFiveP400VEXQ0 VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP400VEXQ0[6] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 SiFiveP400VEXQ0[12] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP400VEXQ0[5] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 SiFiveP400VEXQ0[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 16 SiFiveP400VEXQ0[9] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP400VEXQ0[6] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 SiFiveP400VEXQ0[12] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP400VEXQ0[6] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 SiFiveP400VEXQ0[12] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP400VEXQ0[5] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 SiFiveP400VEXQ0[10] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP400VEXQ0[6] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 SiFiveP400VEXQ0[12] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP400VEXQ0[4] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP400VEXQ0[6] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 13 SiFiveP400VEXQ0[12] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP400VEXQ0[2] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SiFiveP400VEXQ0[3] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP400VEXQ0[5] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 SiFiveP400VEXQ0[10] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SiFiveP400VEXQ0[32] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 64 SiFiveP400VEXQ0[64] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 128 128.00 128 SiFiveP400VEXQ0[128] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP400VEXQ0[10] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP400VEXQ0[10] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP400VEXQ0[20] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 40 40.00 40 SiFiveP400VEXQ0[40] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 80 80.00 80 SiFiveP400VEXQ0[80] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP400VEXQ0[6] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SiFiveP400VEXQ0[12] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SiFiveP400VEXQ0[24] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SiFiveP400VEXQ0[48] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 22 16.00 22 SiFiveP400VEXQ0[16] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 28 16.00 28 SiFiveP400VEXQ0[16] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 34 16.00 34 SiFiveP400VEXQ0[16] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP400VEXQ0[10] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP400VEXQ0[10] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 10.00 16 SiFiveP400VEXQ0[10] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 22 10.00 22 SiFiveP400VEXQ0[10] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 28 10.00 28 SiFiveP400VEXQ0[10] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP400VEXQ0[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 SiFiveP400VEXQ0[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 18 6.00 18 SiFiveP400VEXQ0[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 24 6.00 24 SiFiveP400VEXQ0[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SiFiveP400VEXQ0[16] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SiFiveP400VEXQ0[32] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 64 SiFiveP400VEXQ0[64] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 128 128.00 128 SiFiveP400VEXQ0[128] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP400VEXQ0[10] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP400VEXQ0[10] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP400VEXQ0[20] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 40 40.00 40 SiFiveP400VEXQ0[40] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 80 80.00 80 SiFiveP400VEXQ0[80] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 1.00 12 SiFiveP400VEXQ0 VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 1.00 12 SiFiveP400VEXQ0 VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 12 1.00 12 SiFiveP400VEXQ0 VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 18 2.00 18 SiFiveP400VEXQ0[2] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 30 4.00 30 SiFiveP400VEXQ0[4] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 54 8.00 54 SiFiveP400VEXQ0[8] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 1.00 12 SiFiveP400VEXQ0 VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 12 1.00 12 SiFiveP400VEXQ0 VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 18 2.00 18 SiFiveP400VEXQ0[2] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 30 4.00 30 SiFiveP400VEXQ0[4] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 54 8.00 54 SiFiveP400VEXQ0[8] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 294.00 - - - - 2179.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 17.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 14.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 17.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 14.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 17.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 14.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredmin.vs v8, v8, v8
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 32.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 64.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 128.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 20.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 40.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 80.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 24.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 48.00 - - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 32.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 64.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 128.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 20.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 40.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 80.00 - - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vfwredusum.vs v8, v8, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vle-vse-vlm.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vle-vse-vlm.test
new file mode 100644
index 0000000000000..a5970b18d8439
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vle-vse-vlm.test
@@ -0,0 +1,373 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vle-vse-vlm.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VLD[2] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VLD[4] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VLD[8] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VLD[2] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VLD[4] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VLD[8] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VLD[2] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VLD[4] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VLD[8] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VLD[2] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VLD[4] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VLD[8] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VST[2] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VST[4] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VST[8] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VST[2] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VST[4] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VST[8] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VST[2] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VST[4] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VST[8] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VST[2] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VST[4] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VST[8] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VLD[2] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VLD[4] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VLD[8] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VLD[2] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VLD[4] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VLD[8] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VLD[2] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VLD[4] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VLD[8] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP400VLD VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP400VLD[2] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP400VLD[4] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP400VLD[8] VLE64FF_V vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 80.00 - - - - - - 139.00 73.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlse-vsse.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlse-vsse.test
new file mode 100644
index 0000000000000..ca2bff05db87d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlse-vsse.test
@@ -0,0 +1,229 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlse-vsse.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VLD[32] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VLD[64] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP400VLD[128] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VLD[32] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VLD[64] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VLD[32] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VST[32] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VST[64] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP400VST[128] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VST[32] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VST[64] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VST[32] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSSE64_V vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 44.00 - - - - - - 472.00 472.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 128.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlseg-vsseg.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlseg-vsseg.test
new file mode 100644
index 0000000000000..4c20e7618ed55
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlseg-vsseg.test
@@ -0,0 +1,3133 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlseg-vsseg.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP400VLD[108] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP400VLD[52] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * 92 SiFiveP400VLD[92] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP400VLD[52] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSEG5E64_V vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP400VLD[108] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG6E64_V vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP400VLD[68] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * 124 SiFiveP400VLD[124] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP400VLD[68] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSEG7E64_V vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG8E64_V vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP400VST[108] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP400VST[52] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * 81 SiFiveP400VST[92] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP400VST[52] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSSEG5E64_V vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP400VST[108] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSEG6E64_V vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP400VST[68] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * 113 SiFiveP400VST[124] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP400VST[68] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSSEG7E64_V vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSEG8E64_V vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP400VLD[108] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP400VLD[52] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * 92 SiFiveP400VLD[92] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP400VLD[52] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSSEG5E64_V vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP400VLD[108] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSSEG6E64_V vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP400VLD[68] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * 124 SiFiveP400VLD[124] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP400VLD[68] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSSEG7E64_V vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSSEG8E64_V vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP400VST[108] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP400VST[52] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * 81 SiFiveP400VST[92] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP400VST[52] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSSSEG5E64_V vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP400VST[108] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSSSEG6E64_V vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP400VST[68] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * 113 SiFiveP400VST[124] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP400VST[68] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSSSEG7E64_V vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSSSEG8E64_V vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP400VLD[108] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP400VLD[52] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * 92 SiFiveP400VLD[92] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP400VLD[52] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLSEG5E64FF_V vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP400VLD[108] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLSEG6E64FF_V vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP400VLD[68] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * 124 SiFiveP400VLD[124] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP400VLD[68] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLSEG7E64FF_V vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLSEG8E64FF_V vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP400VLD[108] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP400VLD[52] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * 92 SiFiveP400VLD[92] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP400VLD[52] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLUXSEG5EI64_V vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP400VLD[108] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLUXSEG6EI64_V vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP400VLD[68] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * 124 SiFiveP400VLD[124] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP400VLD[68] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLUXSEG7EI64_V vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLUXSEG8EI64_V vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP400VLD[16] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP400VLD[108] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP400VLD[18] VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP400VLD[20] VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP400VLD[52] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * 92 SiFiveP400VLD[92] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP400VLD[52] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP400VLD[32] VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP400VLD[22] VLOXSEG5EI64_V vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP400VLD[108] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP400VLD[60] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP400VLD[36] VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP400VLD[24] VLOXSEG6EI64_V vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP400VLD[68] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * 124 SiFiveP400VLD[124] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP400VLD[68] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP400VLD[40] VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP400VLD[26] VLOXSEG7EI64_V vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP400VLD[140] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP400VLD[76] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP400VLD[44] VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP400VLD[28] VLOXSEG8EI64_V vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP400VST[108] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP400VST[52] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * 81 SiFiveP400VST[92] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP400VST[52] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSUXSEG5EI64_V vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP400VST[108] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSUXSEG6EI64_V vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP400VST[68] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * 113 SiFiveP400VST[124] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP400VST[68] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSUXSEG7EI64_V vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSUXSEG8EI64_V vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP400VST[16] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP400VST[108] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP400VST[18] VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP400VST[20] VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP400VST[52] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * 81 SiFiveP400VST[92] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP400VST[52] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP400VST[32] VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP400VST[22] VSOXSEG5EI64_V vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP400VST[108] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP400VST[60] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP400VST[36] VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP400VST[24] VSOXSEG6EI64_V vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP400VST[68] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * 113 SiFiveP400VST[124] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP400VST[68] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP400VST[40] VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP400VST[26] VSOXSEG7EI64_V vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP400VST[140] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP400VST[76] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP400VST[44] VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP400VST[28] VSOXSEG8EI64_V vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 770.00 - - - - - - 18160.00 14240.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 76.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 140.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 76.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 18.00 - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 24.00 - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 36.00 - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 60.00 - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 108.00 - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 18.00 - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 52.00 vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 92.00 vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 22.00 vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 52.00 vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 22.00 vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 22.00 vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 36.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 60.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 108.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 36.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 60.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 36.00 vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 40.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 68.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 124.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 40.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 68.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 40.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 44.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 76.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 140.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 44.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 76.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 44.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlxe-vsxe.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlxe-vsxe.test
new file mode 100644
index 0000000000000..5f099f6bd9cc7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlxe-vsxe.test
@@ -0,0 +1,405 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlxe-vsxe.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VLD[32] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VLD[64] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP400VLD[128] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VLD[32] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VLD[64] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VLD[32] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VLD[32] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VLD[64] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP400VLD[128] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VLD[32] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VLD[64] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VLD[32] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VLD[2] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VLD[4] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VLD[8] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VLD[16] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VST[32] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VST[64] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP400VST[128] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VST[32] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VST[64] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VST[32] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VST[32] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VST[64] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP400VST[128] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VST[32] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP400VST[64] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP400VST[32] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP400VST[2] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP400VST[4] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP400VST[8] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP400VST[16] VSOXEI64_V vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 88.00 - - - - - - 944.00 944.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 128.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 128.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei64.v v8, (a0), v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvbb.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbb.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvbb.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvbc.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvbc.test
new file mode 100644
index 0000000000000..b3833e14d5370
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvbc.test
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/zvbc.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCLMUL_VV vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCLMUL_VX vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCLMULH_VV vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400VEXQ0 VCLMULH_VX vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VCLMUL_VV vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VCLMUL_VX vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VCLMULH_VV vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP400VEXQ0[2] VCLMULH_VX vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VCLMUL_VV vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VCLMUL_VX vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VCLMULH_VV vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP400VEXQ0[4] VCLMULH_VX vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VCLMUL_VV vclmul.vv v8, v12, v24
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VCLMUL_VX vclmul.vx v8, v12, a0
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VCLMULH_VV vclmulh.vv v8, v12, v24
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP400VEXQ0[8] VCLMULH_VX vclmulh.vx v8, v12, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 4.00 - - - - 60.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmul.vv v8, v12, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmul.vx v8, v12, a0
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmulh.vv v8, v12, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmulh.vx v8, v12, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvkg.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkg.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvkg.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkned.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvkned.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkned.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvkned.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvknhb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvknhb.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvknhb.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvknhb.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksed.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvksed.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksed.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvksed.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksh.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvksh.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksh.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvksh.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s
deleted file mode 100644
index c4934f4ab0209..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s
+++ /dev/null
@@ -1,108 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e32, m2, tu, mu
-vslidedown.vx v5, v7, x6
-
-vsetvli zero, zero, e32, m4, tu, mu
-vslidedown.vx v5, v7, x6
-
-vsetvli zero, zero, e32, m8, tu, mu
-vslidedown.vx v5, v7, x6
-
-vsetvli zero, zero, e32, m2, tu, mu
-vslideup.vx v5, v7, x6
-
-vsetvli zero, zero, e32, m4, tu, mu
-vslideup.vx v5, v7, x6
-
-vsetvli zero, zero, e32, m8, tu, mu
-vslideup.vx v5, v7, x6
-
-vsetvli zero, zero, e32, m2, tu, mu
-vslideup.vx v5, v7, x6, v0.t
-
-vsetvli zero, zero, e32, m4, tu, mu
-vslideup.vx v5, v7, x6, v0.t
-
-vsetvli zero, zero, e32, m8, tu, mu
-vslideup.vx v5, v7, x6, v0.t
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 18
-# CHECK-NEXT: Total Cycles: 125
-# CHECK-NEXT: Total uOps: 18
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.14
-# CHECK-NEXT: IPC: 0.14
-# CHECK-NEXT: Block RThroughput: 121.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 11 11.00 vslidedown.vx v5, v7, t1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 14 14.00 vslidedown.vx v5, v7, t1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 20 20.00 vslidedown.vx v5, v7, t1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 10 10.00 vslideup.vx v5, v7, t1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 12 12.00 vslideup.vx v5, v7, t1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 16 16.00 vslideup.vx v5, v7, t1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 10 10.00 vslideup.vx v5, v7, t1, v0.t
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 12 12.00 vslideup.vx v5, v7, t1, v0.t
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 16 16.00 vslideup.vx v5, v7, t1, v0.t
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 9.00 - - - - 121.00 - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 11.00 - - - vslidedown.vx v5, v7, t1
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 14.00 - - - vslidedown.vx v5, v7, t1
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 20.00 - - - vslidedown.vx v5, v7, t1
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v5, v7, t1
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v5, v7, t1
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v5, v7, t1
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v5, v7, t1, v0.t
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v5, v7, t1, v0.t
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v5, v7, t1, v0.t
-
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s
deleted file mode 100644
index 53bf836263759..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s
+++ /dev/null
@@ -1,542 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vle8.v v8, (a0)
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, mf2, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m1, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m2, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m4, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m8, ta, ma
-vle16.v v8, (a0)
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m1, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m2, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m4, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m8, ta, ma
-vle32.v v8, (a0)
-
-vsetvli zero, zero, e64, m1, ta, ma
-vle64.v v8, (a0)
-vsetvli zero, zero, e64, m2, ta, ma
-vle64.v v8, (a0)
-vsetvli zero, zero, e64, m4, ta, ma
-vle64.v v8, (a0)
-vsetvli zero, zero, e64, m8, ta, ma
-vle64.v v8, (a0)
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vse8.v v8, (a0)
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, mf2, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m1, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m2, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m4, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m8, ta, ma
-vse16.v v8, (a0)
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m1, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m2, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m4, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m8, ta, ma
-vse32.v v8, (a0)
-
-vsetvli zero, zero, e64, m1, ta, ma
-vse64.v v8, (a0)
-vsetvli zero, zero, e64, m2, ta, ma
-vse64.v v8, (a0)
-vsetvli zero, zero, e64, m4, ta, ma
-vse64.v v8, (a0)
-vsetvli zero, zero, e64, m8, ta, ma
-vse64.v v8, (a0)
-
-# Unit-stride mask load/store
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vlm.v v8, (a0)
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vsm.v v8, (a0)
-
-# Fault-only-first
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vle8ff.v v8, (a0)
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, mf2, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m1, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m2, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m4, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m8, ta, ma
-vle16ff.v v8, (a0)
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m1, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m2, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m4, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m8, ta, ma
-vle32ff.v v8, (a0)
-
-vsetvli zero, zero, e64, m1, ta, ma
-vle64ff.v v8, (a0)
-vsetvli zero, zero, e64, m2, ta, ma
-vle64ff.v v8, (a0)
-vsetvli zero, zero, e64, m4, ta, ma
-vle64ff.v v8, (a0)
-vsetvli zero, zero, e64, m8, ta, ma
-vle64ff.v v8, (a0)
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 160
-# CHECK-NEXT: Total Cycles: 146
-# CHECK-NEXT: Total uOps: 160
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 1.10
-# CHECK-NEXT: IPC: 1.10
-# CHECK-NEXT: Block RThroughput: 139.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle64ff.v v8, (a0)
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 80.00 - - - - - - 139.00 73.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle32ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle32ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle32ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle64ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle64ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle64ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
deleted file mode 100644
index fcf544395db8f..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
+++ /dev/null
@@ -1,316 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf4, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf2, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m1, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m2, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m4, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m8, ta, ma
-vlse8.v v8, (a0), t0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, mf2, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m1, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m2, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m4, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m8, ta, ma
-vlse16.v v8, (a0), t0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m1, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m2, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m4, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m8, ta, ma
-vlse32.v v8, (a0), t0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vlse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m2, ta, ma
-vlse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m4, ta, ma
-vlse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m8, ta, ma
-vlse64.v v8, (a0), t0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf4, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf2, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m1, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m2, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m4, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m8, ta, ma
-vsse8.v v8, (a0), t0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, mf2, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m1, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m2, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m4, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m8, ta, ma
-vsse16.v v8, (a0), t0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m1, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m2, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m4, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m8, ta, ma
-vsse32.v v8, (a0), t0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vsse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m2, ta, ma
-vsse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m4, ta, ma
-vsse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m8, ta, ma
-vsse64.v v8, (a0), t0
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 88
-# CHECK-NEXT: Total Cycles: 954
-# CHECK-NEXT: Total uOps: 88
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.09
-# CHECK-NEXT: IPC: 0.09
-# CHECK-NEXT: Block RThroughput: 472.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsse64.v v8, (a0), t0
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 44.00 - - - - - - 472.00 472.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 64.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 128.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 64.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
deleted file mode 100644
index 41e9101486ead..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
+++ /dev/null
@@ -1,4727 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, m2, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, m4, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vlseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vlseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vlseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, m2, tu, mu
-vlseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, m4, tu, mu
-vlseg2e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vlseg2e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vlseg2e32.v v8,(a0)
-vsetvli zero, zero, e32, m2, tu, mu
-vlseg2e32.v v8,(a0)
-vsetvli zero, zero, e32, m4, tu, mu
-vlseg2e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vlseg2e64.v v8,(a0)
-vsetvli zero, zero, e64, m2, tu, mu
-vlseg2e64.v v8,(a0)
-vsetvli zero, zero, e64, m4, tu, mu
-vlseg2e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vlseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vlseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vlseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, m2, tu, mu
-vlseg3e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vlseg3e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vlseg3e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vlseg3e16.v v8,(a0)
-vsetvli zero, zero, e16, m2, tu, mu
-vlseg3e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vlseg3e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vlseg3e32.v v8,(a0)
-vsetvli zero, zero, e32, m2, tu, mu
-vlseg3e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vlseg3e64.v v8,(a0)
-vsetvli zero, zero, e64, m2, tu, mu
-vlseg3e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlseg4e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vlseg4e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vlseg4e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vlseg4e8.v v8,(a0)
-vsetvli zero, zero, e8, m2, tu, mu
-vlseg4e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vlseg4e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vlseg4e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vlseg4e16.v v8,(a0)
-vsetvli zero, zero, e16, m2, tu, mu
-vlseg4e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vlseg4e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vlseg4e32.v v8,(a0)
-vsetvli zero, zero, e32, m2, tu, mu
-vlseg4e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vlseg4e64.v v8,(a0)
-vsetvli zero, zero, e64, m2, tu, mu
-vlseg4e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlseg5e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vlseg5e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vlseg5e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vlseg5e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vlseg5e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vlseg5e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vlseg5e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vlseg5e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vlseg5e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vlseg5e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlseg6e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vlseg6e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vlseg6e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vlseg6e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vlseg6e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vlseg6e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vlseg6e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vlseg6e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vlseg6e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vlseg6e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlseg7e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vlseg7e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vlseg7e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vlseg7e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vlseg7e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vlseg7e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vlseg7e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vlseg7e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vlseg7e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vlseg7e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlseg8e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vlseg8e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vlseg8e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vlseg8e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vlseg8e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vlseg8e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vlseg8e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vlseg8e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vlseg8e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vlseg8e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vsseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vsseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vsseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, m2, tu, mu
-vsseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, m4, tu, mu
-vsseg2e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vsseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vsseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vsseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, m2, tu, mu
-vsseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, m4, tu, mu
-vsseg2e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vsseg2e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vsseg2e32.v v8,(a0)
-vsetvli zero, zero, e32, m2, tu, mu
-vsseg2e32.v v8,(a0)
-vsetvli zero, zero, e32, m4, tu, mu
-vsseg2e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vsseg2e64.v v8,(a0)
-vsetvli zero, zero, e64, m2, tu, mu
-vsseg2e64.v v8,(a0)
-vsetvli zero, zero, e64, m4, tu, mu
-vsseg2e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vsseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vsseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vsseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, m2, tu, mu
-vsseg3e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vsseg3e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vsseg3e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vsseg3e16.v v8,(a0)
-vsetvli zero, zero, e16, m2, tu, mu
-vsseg3e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vsseg3e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vsseg3e32.v v8,(a0)
-vsetvli zero, zero, e32, m2, tu, mu
-vsseg3e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vsseg3e64.v v8,(a0)
-vsetvli zero, zero, e64, m2, tu, mu
-vsseg3e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsseg4e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vsseg4e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vsseg4e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vsseg4e8.v v8,(a0)
-vsetvli zero, zero, e8, m2, tu, mu
-vsseg4e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vsseg4e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vsseg4e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vsseg4e16.v v8,(a0)
-vsetvli zero, zero, e16, m2, tu, mu
-vsseg4e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vsseg4e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vsseg4e32.v v8,(a0)
-vsetvli zero, zero, e32, m2, tu, mu
-vsseg4e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vsseg4e64.v v8,(a0)
-vsetvli zero, zero, e64, m2, tu, mu
-vsseg4e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsseg5e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vsseg5e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vsseg5e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vsseg5e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vsseg5e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vsseg5e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vsseg5e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vsseg5e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vsseg5e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vsseg5e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsseg6e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vsseg6e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vsseg6e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vsseg6e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vsseg6e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vsseg6e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vsseg6e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vsseg6e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vsseg6e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vsseg6e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsseg7e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vsseg7e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vsseg7e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vsseg7e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vsseg7e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vsseg7e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vsseg7e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vsseg7e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vsseg7e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vsseg7e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsseg8e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vsseg8e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vsseg8e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vsseg8e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vsseg8e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vsseg8e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vsseg8e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vsseg8e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vsseg8e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vsseg8e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlsseg2e8.v v8, (a0), a1
-vsetvli zero, zero, e8, mf4, tu, mu
-vlsseg2e8.v v8, (a0), a1
-vsetvli zero, zero, e8, mf2, tu, mu
-vlsseg2e8.v v8, (a0), a1
-vsetvli zero, zero, e8, m1, tu, mu
-vlsseg2e8.v v8, (a0), a1
-vsetvli zero, zero, e8, m2, tu, mu
-vlsseg2e8.v v8, (a0), a1
-vsetvli zero, zero, e8, m4, tu, mu
-vlsseg2e8.v v8, (a0), a1
-vsetvli zero, zero, e16, mf4, tu, mu
-vlsseg2e16.v v8, (a0), a1
-vsetvli zero, zero, e16, mf2, tu, mu
-vlsseg2e16.v v8, (a0), a1
-vsetvli zero, zero, e16, m1, tu, mu
-vlsseg2e16.v v8, (a0), a1
-vsetvli zero, zero, e16, m2, tu, mu
-vlsseg2e16.v v8, (a0), a1
-vsetvli zero, zero, e16, m4, tu, mu
-vlsseg2e16.v v8, (a0), a1
-vsetvli zero, zero, e32, mf2, tu, mu
-vlsseg2e32.v v8, (a0), a1
-vsetvli zero, zero, e32, m1, tu, mu
-vlsseg2e32.v v8, (a0), a1
-vsetvli zero, zero, e32, m2, tu, mu
-vlsseg2e32.v v8, (a0), a1
-vsetvli zero, zero, e32, m4, tu, mu
-vlsseg2e32.v v8, (a0), a1
-vsetvli zero, zero, e64, m1, tu, mu
-vlsseg2e64.v v8, (a0), a1
-vsetvli zero, zero, e64, m2, tu, mu
-vlsseg2e64.v v8, (a0), a1
-vsetvli zero, zero, e64, m4, tu, mu
-vlsseg2e64.v v8, (a0), a1
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlsseg3e8.v v8, (a0), a1
-vsetvli zero, zero, e8, mf4, tu, mu
-vlsseg3e8.v v8, (a0), a1
-vsetvli zero, zero, e8, mf2, tu, mu
-vlsseg3e8.v v8, (a0), a1
-vsetvli zero, zero, e8, m1, tu, mu
-vlsseg3e8.v v8, (a0), a1
-vsetvli zero, zero, e8, m2, tu, mu
-vlsseg3e8.v v8, (a0), a1
-vsetvli zero, zero, e16, mf4, tu, mu
-vlsseg3e16.v v8, (a0), a1
-vsetvli zero, zero, e16, mf2, tu, mu
-vlsseg3e16.v v8, (a0), a1
-vsetvli zero, zero, e16, m1, tu, mu
-vlsseg3e16.v v8, (a0), a1
-vsetvli zero, zero, e16, m2, tu, mu
-vlsseg3e16.v v8, (a0), a1
-vsetvli zero, zero, e32, mf2, tu, mu
-vlsseg3e32.v v8, (a0), a1
-vsetvli zero, zero, e32, m1, tu, mu
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-vsuxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsuxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsuxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg2ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsuxseg2ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsuxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsuxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsuxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg3ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsuxseg3ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsuxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsuxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsuxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg4ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsuxseg4ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg5ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg6ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg7ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg8ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m4, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m4, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m4, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg2ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsoxseg2ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m4, tu, mu
-vsoxseg2ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsoxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg3ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsoxseg3ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsoxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg4ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsoxseg4ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg5ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg6ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg7ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg8ei64.v v8, (a0), v16
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 1540
-# CHECK-NEXT: Total Cycles: 28599
-# CHECK-NEXT: Total uOps: 1540
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.05
-# CHECK-NEXT: IPC: 0.05
-# CHECK-NEXT: Block RThroughput: 18160.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 92 92.00 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 124 124.00 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 81 92.00 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsseg5e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg6e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 113 124.00 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsseg7e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg8e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlsseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlsseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlsseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 92 92.00 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlsseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlsseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlsseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlsseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlsseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlsseg5e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlsseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg6e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 124 124.00 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlsseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlsseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlsseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlsseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlsseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlsseg7e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg8e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vssseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vssseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vssseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 81 92.00 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vssseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vssseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vssseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vssseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vssseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vssseg5e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vssseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg6e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 113 124.00 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vssseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vssseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vssseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vssseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vssseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vssseg7e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg8e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 92 92.00 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlseg5e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg6e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 124 124.00 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlseg7e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg8e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vluxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vluxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vluxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 92 92.00 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vluxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vluxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vluxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vluxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vluxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vluxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vluxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 124 124.00 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vluxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vluxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vluxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vluxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vluxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vluxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg8ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vloxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vloxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vloxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 92 92.00 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vloxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vloxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vloxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vloxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vloxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vloxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vloxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 124 124.00 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vloxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vloxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vloxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vloxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vloxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vloxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg8ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 81 92.00 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsuxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsuxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsuxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsuxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 113 124.00 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsuxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsuxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsuxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsuxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 81 92.00 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsoxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 113 124.00 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsoxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei64.v v8, (a0), v16
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 770.00 - - - - - - 18160.00 14240.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 76.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 140.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 76.00 - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 18.00 - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 24.00 - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 36.00 - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
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-# CHECK-NEXT: - - - - - - - - - - - - 20.00 vsoxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 22.00 vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 52.00 vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 92.00 vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 22.00 vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 52.00 vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 22.00 vsoxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 22.00 vsoxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 36.00 vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 60.00 vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 108.00 vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 36.00 vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 60.00 vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 36.00 vsoxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 40.00 vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 68.00 vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 124.00 vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 40.00 vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 68.00 vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 40.00 vsoxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 44.00 vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 76.00 vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 140.00 vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 44.00 vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 76.00 vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 44.00 vsoxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
deleted file mode 100644
index 086dd524ba812..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
+++ /dev/null
@@ -1,588 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vluxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vluxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vluxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vluxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vluxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vluxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vluxei64.v v8, (a0), v0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vloxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vloxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vloxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vloxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vloxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vloxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vloxei64.v v8, (a0), v0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vsuxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vsuxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vsuxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vsuxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vsuxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vsuxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vsuxei64.v v8, (a0), v0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vsoxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vsoxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vsoxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vsoxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vsoxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vsoxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vsoxei64.v v8, (a0), v0
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 176
-# CHECK-NEXT: Total Cycles: 1898
-# CHECK-NEXT: Total uOps: 176
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.09
-# CHECK-NEXT: IPC: 0.09
-# CHECK-NEXT: Block RThroughput: 944.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsoxei64.v v8, (a0), v0
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 88.00 - - - - - - 944.00 944.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 64.00 - vluxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 128.00 - vluxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 64.00 - vluxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 64.00 - vloxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 128.00 - vloxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 64.00 - vloxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei64.v v8, (a0), v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s
deleted file mode 100644
index e69b7fb38295e..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s
+++ /dev/null
@@ -1,895 +0,0 @@
-
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, m2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, m4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, m8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, mf8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, m2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, m4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, m8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, mf8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, mf4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, m2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, m4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, m8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, mf8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, mf4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, mf2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, m2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, m4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, m8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, mf8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, m2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, m4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, m8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, mf8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, m2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, m4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, m8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, mf8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, mf4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, m2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, m4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, m8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, mf8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, mf4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, mf2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, m2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, m4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, m8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, mf8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, m2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, m4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, m8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, mf8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, m2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, m4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, m8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, mf8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, mf4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, m2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, m4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, m8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, mf8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, mf4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, mf2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, m2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, m4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, m8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, mf8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, m2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, m4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, m8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, mf8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, m2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, m4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, m8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, mf8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, mf4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, m2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, m4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, m8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, mf8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, mf4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, mf2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, m2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, m4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, m8, tu, mu
-vmv8r.v v8, v16
-
-vsetvli zero, zero, e64, m1, tu, mu
-vmv.s.x v8, x5
-vmv.x.s x7, v16
-
-vsetvli zero, zero, e64, m2, tu, mu
-vmv.s.x v8, x5
-vmv.x.s x7, v16
-
-vsetvli zero, zero, e64, m4, tu, mu
-vmv.s.x v8, x5
-vmv.x.s x7, v16
-
-vsetvli zero, zero, e64, m8, tu, mu
-vmv.s.x v8, x5
-vmv.x.s x7, v16
-
-vsetvli zero, zero, e64, m1, tu, mu
-vfmv.s.f v8, f5
-vfmv.f.s f7, v16
-
-vsetvli zero, zero, e64, m2, tu, mu
-vfmv.s.f v8, f5
-vfmv.f.s f7, v16
-
-vsetvli zero, zero, e64, m4, tu, mu
-vfmv.s.f v8, f5
-vfmv.f.s f7, v16
-
-vsetvli zero, zero, e64, m8, tu, mu
-vfmv.s.f v8, f5
-vfmv.f.s f7, v16
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 280
-# CHECK-NEXT: Total Cycles: 524
-# CHECK-NEXT: Total uOps: 280
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.53
-# CHECK-NEXT: IPC: 0.53
-# CHECK-NEXT: Block RThroughput: 512.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv.s.x v8, t0
-# CHECK-NEXT: 1 2 2.00 vmv.x.s t2, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv.s.x v8, t0
-# CHECK-NEXT: 1 2 2.00 vmv.x.s t2, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv.s.x v8, t0
-# CHECK-NEXT: 1 2 2.00 vmv.x.s t2, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv.s.x v8, t0
-# CHECK-NEXT: 1 2 2.00 vmv.x.s t2, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 6 2.00 vfmv.s.f v8, ft5
-# CHECK-NEXT: 1 6 2.00 vfmv.f.s ft7, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 6 2.00 vfmv.s.f v8, ft5
-# CHECK-NEXT: 1 6 2.00 vfmv.f.s ft7, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 6 2.00 vfmv.s.f v8, ft5
-# CHECK-NEXT: 1 6 2.00 vfmv.f.s ft7, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 6 2.00 vfmv.s.f v8, ft5
-# CHECK-NEXT: 1 6 2.00 vfmv.f.s ft7, v16
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 136.00 - - - - 512.00 - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, t0
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s t2, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, t0
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s t2, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, t0
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s t2, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, t0
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s t2, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.s.f v8, ft5
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.f.s ft7, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.s.f v8, ft5
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.f.s ft7, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.s.f v8, ft5
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.f.s ft7, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.s.f v8, ft5
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.f.s ft7, v16
-
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vreduce.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vreduce.s
deleted file mode 100644
index 0fc0bf03d7ecb..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vreduce.s
+++ /dev/null
@@ -1,438 +0,0 @@
-
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-# Simple integer reductions: varies by LMUL
-vsetvli zero, zero, e32, m1, tu, mu
-vredsum.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m2, tu, mu
-vredsum.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m4, tu, mu
-vredsum.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m8, tu, mu
-vredsum.vs v5, v7, v8
-
-# Advanced integer reductions: varies by LMUL and SEW
-vsetvli zero, zero, e16, m1, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e16, m2, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e16, m4, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e16, m8, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m1, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m2, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m4, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m8, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m1, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m2, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m4, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m8, tu, mu
-vredmin.vs v5, v7, v8
-vredmax.vs v5, v7, v8
-
-# Simple floating point reductions: varies by LMUL and SEW
-vsetvli zero, zero, e16, m1, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e16, m2, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e16, m4, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e16, m8, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m1, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m2, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m4, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m8, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m1, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m2, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m4, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m8, tu, mu
-vfredusum.vs v5, v7, v8
-vfredosum.vs v5, v7, v8
-
-# Advanced floating point reductions: varies by LMUL and SEW
-vsetvli zero, zero, e16, m1, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e16, m2, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e16, m4, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e16, m8, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m1, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m2, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m4, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e32, m8, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m1, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m2, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m4, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-vsetvli zero, zero, e64, m8, tu, mu
-vfredmin.vs v5, v7, v8
-vfredmax.vs v5, v7, v8
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 116
-# CHECK-NEXT: Total Cycles: 921
-# CHECK-NEXT: Total uOps: 116
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.13
-# CHECK-NEXT: IPC: 0.13
-# CHECK-NEXT: Block RThroughput: 916.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vredsum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 4 2.00 vredsum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 8 4.00 vredsum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 16 9.00 vredsum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 4.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 10 5.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 10 5.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 12 8.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 12 8.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 15 14.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 15 14.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 6 3.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 4.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 10 6.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 10 6.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 13 12.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 13 12.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 4 2.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 4 2.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 6 3.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 6 3.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 8 5.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 5.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 11 10.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 11 10.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 16 16.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 22 16.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 32 32.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 28 16.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 64 64.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 34 16.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 128 128.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 10 10.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 10 10.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 10.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 20 20.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 22 10.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 40 40.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 28 10.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 80 80.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 6 6.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 6 6.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 12 6.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 12 12.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 18 6.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 24 24.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 24 6.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 48 48.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 6 3.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 4.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 10 6.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 10 6.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 13 12.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 13 12.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 6 3.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 4.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 10 6.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 10 6.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 13 12.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 13 12.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 4 2.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 4 2.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 6 3.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 8 5.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 5.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 11 10.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 11 10.00 vfredmax.vs v5, v7, v8
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 40.00 - - - - 916.00 - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredsum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredsum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredsum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredsum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 14.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 14.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 32.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 64.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 128.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 20.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 40.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 80.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 24.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 48.00 - - - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 5.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 5.00 - - - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredmax.vs v5, v7, v8
-
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vrgather.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vrgather.s
deleted file mode 100644
index ef24850957193..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vrgather.s
+++ /dev/null
@@ -1,86 +0,0 @@
-
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e32, m1, tu, mu
-vrgather.vv v5, v7, v8
-vcompress.vm v4, v9, v0
-
-vsetvli zero, zero, e32, m2, tu, mu
-vrgather.vv v5, v7, v8
-vcompress.vm v4, v9, v0
-
-vsetvli zero, zero, e32, m4, tu, mu
-vrgather.vv v5, v7, v8
-vcompress.vm v4, v9, v0
-
-vsetvli zero, zero, e32, m8, tu, mu
-vrgather.vv v5, v7, v8
-vcompress.vm v4, v9, v0
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 12
-# CHECK-NEXT: Total Cycles: 92
-# CHECK-NEXT: Total uOps: 12
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.13
-# CHECK-NEXT: IPC: 0.13
-# CHECK-NEXT: Block RThroughput: 106.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 3 1.00 vrgather.vv v5, v7, v8
-# CHECK-NEXT: 1 3 1.00 vcompress.vm v4, v9, v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 6 12.00 vrgather.vv v5, v7, v8
-# CHECK-NEXT: 1 6 12.00 vcompress.vm v4, v9, v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 6 16.00 vrgather.vv v5, v7, v8
-# CHECK-NEXT: 1 6 16.00 vcompress.vm v4, v9, v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 6 24.00 vrgather.vv v5, v7, v8
-# CHECK-NEXT: 1 6 24.00 vcompress.vm v4, v9, v0
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 4.00 - - - - 106.00 - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrgather.vv v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcompress.vm v4, v9, v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vrgather.vv v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 12.00 - - - vcompress.vm v4, v9, v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 16.00 - - - vrgather.vv v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 16.00 - - - vcompress.vm v4, v9, v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 24.00 - - - vrgather.vv v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - 24.00 - - - vcompress.vm v4, v9, v0
-
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vshift-vmul.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vshift-vmul.s
deleted file mode 100644
index 7a0cf27f37425..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vshift-vmul.s
+++ /dev/null
@@ -1,132 +0,0 @@
-
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e32, m1, ta, ma
-
-vsll.vv v1, v2, v5
-vsll.vx v1, v2, t0
-vsll.vi v1, v2, 7
-
-vsrl.vv v1, v2, v5
-vsrl.vx v1, v2, t0
-vsrl.vi v1, v2, 7
-
-vsra.vv v1, v2, v5
-vsra.vx v1, v2, t0
-vsra.vi v1, v2, 7
-
-vsetvli zero, zero, e32, mf4, ta, ma
-
-vsll.vv v1, v2, v5
-vsll.vx v1, v2, t0
-vsll.vi v1, v2, 7
-
-vsrl.vv v1, v2, v5
-vsrl.vx v1, v2, t0
-vsrl.vi v1, v2, 7
-
-vsra.vv v1, v2, v5
-vsra.vx v1, v2, t0
-vsra.vi v1, v2, 7
-
-vsetvli zero, zero, e32, m8, ta, ma
-
-vmul.vv v1, v2, v5
-vmul.vx v1, v2, t1
-
-vmadd.vv v1, v2, v5
-vmadd.vx v1, t1, v2
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 25
-# CHECK-NEXT: Total Cycles: 57
-# CHECK-NEXT: Total uOps: 25
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.44
-# CHECK-NEXT: IPC: 0.44
-# CHECK-NEXT: Block RThroughput: 50.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 2 1.00 vsll.vv v1, v2, v5
-# CHECK-NEXT: 1 2 1.00 vsll.vx v1, v2, t0
-# CHECK-NEXT: 1 2 1.00 vsll.vi v1, v2, 7
-# CHECK-NEXT: 1 2 1.00 vsrl.vv v1, v2, v5
-# CHECK-NEXT: 1 2 1.00 vsrl.vx v1, v2, t0
-# CHECK-NEXT: 1 2 1.00 vsrl.vi v1, v2, 7
-# CHECK-NEXT: 1 2 1.00 vsra.vv v1, v2, v5
-# CHECK-NEXT: 1 2 1.00 vsra.vx v1, v2, t0
-# CHECK-NEXT: 1 2 1.00 vsra.vi v1, v2, 7
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, ta, ma
-# CHECK-NEXT: 1 2 1.00 vsll.vv v1, v2, v5
-# CHECK-NEXT: 1 2 1.00 vsll.vx v1, v2, t0
-# CHECK-NEXT: 1 2 1.00 vsll.vi v1, v2, 7
-# CHECK-NEXT: 1 2 1.00 vsrl.vv v1, v2, v5
-# CHECK-NEXT: 1 2 1.00 vsrl.vx v1, v2, t0
-# CHECK-NEXT: 1 2 1.00 vsrl.vi v1, v2, 7
-# CHECK-NEXT: 1 2 1.00 vsra.vv v1, v2, v5
-# CHECK-NEXT: 1 2 1.00 vsra.vx v1, v2, t0
-# CHECK-NEXT: 1 2 1.00 vsra.vi v1, v2, 7
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 9 8.00 vmul.vv v1, v2, v5
-# CHECK-NEXT: 1 9 8.00 vmul.vx v1, v2, t1
-# CHECK-NEXT: 1 9 8.00 vmadd.vv v1, v2, v5
-# CHECK-NEXT: 1 9 8.00 vmadd.vx v1, t1, v2
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 3.00 - - - - 50.00 - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vx v1, v2, t0
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vi v1, v2, 7
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vx v1, v2, t0
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vi v1, v2, 7
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vx v1, v2, t0
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vi v1, v2, 7
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vx v1, v2, t0
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vi v1, v2, 7
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vx v1, v2, t0
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vi v1, v2, 7
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vx v1, v2, t0
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vi v1, v2, 7
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmul.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmul.vx v1, v2, t1
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmadd.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmadd.vx v1, t1, v2
-
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zba.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zba.test
new file mode 100644
index 0000000000000..f7886be9b37b2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zba.test
@@ -0,0 +1,69 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../Inputs/zba.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith ADD_UW add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLLI_UW slli.uw a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SH1ADD_UW sh1add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SH2ADD_UW sh2add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SH3ADD_UW sh3add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SH1ADD sh1add a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SH2ADD sh2add a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SH3ADD sh3add a0, a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - 2.67 2.67 2.67 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - add.uw a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - slli.uw a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sh1add.uw a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sh2add.uw a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sh3add.uw a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sh1add a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sh2add a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sh3add a0, a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zbb.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zbb.test
new file mode 100644
index 0000000000000..de4c9bd689a55
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zbb.test
@@ -0,0 +1,101 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../Inputs/zbb.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith ANDN andn a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith ORN orn a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith XNOR xnor a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith CLZ clz a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith CLZW clzw a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith CTZ ctz a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith CTZW ctzw a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith CPOP cpop a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith CPOPW cpopw a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith MIN min a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith MINU minu a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith MAX max a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith MAXU maxu a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SEXT_B sext.b a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SEXT_H sext.h a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith ZEXT_H_RV64 zext.h a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith ROL rol a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith ROLW rolw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith ROR ror a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith RORW rorw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith RORI rori a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith RORIW roriw a0, a0, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith ORC_B orc.b a0, a0
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith REV8_RV64 rev8 a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - 7.33 7.33 9.33 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - andn a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - orn a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - xnor a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - clz a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - clzw a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - ctz a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - ctzw a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - cpop a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - cpopw a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - min a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - minu a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - max a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - maxu a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sext.b a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sext.h a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - zext.h a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - rol a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - rolw a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - ror a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - rorw a0, a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - rori a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - roriw a0, a0, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - orc.b a0, a0
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - rev8 a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zbs.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zbs.test
new file mode 100644
index 0000000000000..1ce35f9d8ad12
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zbs.test
@@ -0,0 +1,69 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../Inputs/zbs.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith BCLR bclr a0, a1, a2
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith BCLRI bclri a0, a1, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith BEXT bext a0, a1, a2
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith BEXTI bexti a0, a1, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith BINV binv a0, a1, a2
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith BINVI binvi a0, a1, 1
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith BSET bset a0, a1, a2
+# CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith BSETI bseti a0, a1, 1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - 2.67 2.67 2.67 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - bclr a0, a1, a2
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - bclri a0, a1, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - bext a0, a1, a2
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - bexti a0, a1, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - binv a0, a1, a2
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - binvi a0, a1, 1
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - bset a0, a1, a2
+# CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - bseti a0, a1, 1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zfhmin.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zfhmin.test
new file mode 100644
index 0000000000000..23989b7176a3c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zfhmin.test
@@ -0,0 +1,73 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../Inputs/zfhmin.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 5 1.00 * 5 SiFiveP400Load FLH flh ft0, 0(a0)
+# CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store FSH fsh ft0, 0(a0)
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FMV_X_H fmv.x.h a2, fs7
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400IEXQ2,SiFiveP400IntArith FMV_H_X fmv.h.x ft1, a6
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_S_H fcvt.s.h fa0, ft0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_S_H fcvt.s.h fa0, ft0, rup
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_H_S fcvt.h.s ft2, fa2
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_D_H fcvt.d.h fa0, ft0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_D_H fcvt.d.h fa0, ft0, rup
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP400FEXQ0 FCVT_H_D fcvt.h.d ft2, fa2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - 7.00 - - - 1.00 1.00 1.00 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - flh ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - fsh ft0, 0(a0)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmv.x.h a2, fs7
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fmv.h.x ft1, a6
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.s.h fa0, ft0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.s.h fa0, ft0, rup
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.h.s ft2, fa2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.d.h fa0, ft0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.d.h fa0, ft0, rup
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcvt.h.d ft2, fa2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbc.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbc.s
deleted file mode 100644
index 1e304f6b75a14..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbc.s
+++ /dev/null
@@ -1,112 +0,0 @@
-
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
-
-# These instructions only work with e64
-
-vsetvli zero, zero, e64, m1, tu, mu
-vclmul.vv v4, v8, v12
-vclmul.vx v4, v8, a0
-vclmulh.vv v4, v8, v12
-vclmulh.vx v4, v8, a0
-
-vsetvli zero, zero, e64, m2, tu, mu
-vclmul.vv v4, v8, v12
-vclmul.vx v4, v8, a0
-vclmulh.vv v4, v8, v12
-vclmulh.vx v4, v8, a0
-
-vsetvli zero, zero, e64, m4, tu, mu
-vclmul.vv v4, v8, v12
-vclmul.vx v4, v8, a0
-vclmulh.vv v4, v8, v12
-vclmulh.vx v4, v8, a0
-
-vsetvli zero, zero, e64, m8, tu, mu
-vclmul.vv v8, v12, v24
-vclmul.vx v8, v12, a0
-vclmulh.vv v8, v12, v24
-vclmulh.vx v8, v12, a0
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 20
-# CHECK-NEXT: Total Cycles: 58
-# CHECK-NEXT: Total uOps: 20
-
-# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.34
-# CHECK-NEXT: IPC: 0.34
-# CHECK-NEXT: Block RThroughput: 60.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vclmul.vv v4, v8, v12
-# CHECK-NEXT: 1 2 1.00 vclmul.vx v4, v8, a0
-# CHECK-NEXT: 1 2 1.00 vclmulh.vv v4, v8, v12
-# CHECK-NEXT: 1 2 1.00 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vclmul.vv v4, v8, v12
-# CHECK-NEXT: 1 2 2.00 vclmul.vx v4, v8, a0
-# CHECK-NEXT: 1 2 2.00 vclmulh.vv v4, v8, v12
-# CHECK-NEXT: 1 2 2.00 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vclmul.vv v4, v8, v12
-# CHECK-NEXT: 1 2 4.00 vclmul.vx v4, v8, a0
-# CHECK-NEXT: 1 2 4.00 vclmulh.vv v4, v8, v12
-# CHECK-NEXT: 1 2 4.00 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 8.00 vclmul.vv v8, v12, v24
-# CHECK-NEXT: 1 2 8.00 vclmul.vx v8, v12, a0
-# CHECK-NEXT: 1 2 8.00 vclmulh.vv v8, v12, v24
-# CHECK-NEXT: 1 2 8.00 vclmulh.vx v8, v12, a0
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP400Div
-# CHECK-NEXT: [1] - SiFiveP400FEXQ0
-# CHECK-NEXT: [2] - SiFiveP400FloatDiv
-# CHECK-NEXT: [3] - SiFiveP400IEXQ0
-# CHECK-NEXT: [4] - SiFiveP400IEXQ1
-# CHECK-NEXT: [5] - SiFiveP400IEXQ2
-# CHECK-NEXT: [6] - SiFiveP400Load
-# CHECK-NEXT: [7] - SiFiveP400Store
-# CHECK-NEXT: [8] - SiFiveP400VDiv
-# CHECK-NEXT: [9] - SiFiveP400VEXQ0
-# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
-# CHECK-NEXT: [11] - SiFiveP400VLD
-# CHECK-NEXT: [12] - SiFiveP400VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: - - - - 4.00 - - - - 60.00 - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmul.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmul.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmul.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmulh.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmul.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmul.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmulh.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmul.vv v8, v12, v24
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmul.vx v8, v12, a0
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmulh.vv v8, v12, v24
-# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmulh.vx v8, v12, a0
-
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.test
similarity index 91%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.test
index ecd96a30d6c2d..59b8bb9e86a5f 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.test
@@ -1,105 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Zalrsc
-lr.w t0, (t1)
-lr.w.aq t1, (t2)
-lr.w.rl t2, (t3)
-lr.w.aqrl t3, (t4)
-sc.w t6, t5, (t4)
-sc.w.aq t5, t4, (t3)
-sc.w.rl t4, t3, (t2)
-sc.w.aqrl t3, t2, (t1)
-
-lr.d t0, (t1)
-lr.d.aq t1, (t2)
-lr.d.rl t2, (t3)
-lr.d.aqrl t3, (t4)
-sc.d t6, t5, (t4)
-sc.d.aq t5, t4, (t3)
-sc.d.rl t4, t3, (t2)
-sc.d.aqrl t3, t2, (t1)
-
-# Zaamo
-amoswap.w a4, ra, (s0)
-amoadd.w a1, a2, (a3)
-amoxor.w a2, a3, (a4)
-amoand.w a3, a4, (a5)
-amoor.w a4, a5, (a6)
-amomin.w a5, a6, (a7)
-amomax.w s7, s6, (s5)
-amominu.w s6, s5, (s4)
-amomaxu.w s5, s4, (s3)
-
-amoswap.w.aq a4, ra, (s0)
-amoadd.w.aq a1, a2, (a3)
-amoxor.w.aq a2, a3, (a4)
-amoand.w.aq a3, a4, (a5)
-amoor.w.aq a4, a5, (a6)
-amomin.w.aq a5, a6, (a7)
-amomax.w.aq s7, s6, (s5)
-amominu.w.aq s6, s5, (s4)
-amomaxu.w.aq s5, s4, (s3)
-
-amoswap.w.rl a4, ra, (s0)
-amoadd.w.rl a1, a2, (a3)
-amoxor.w.rl a2, a3, (a4)
-amoand.w.rl a3, a4, (a5)
-amoor.w.rl a4, a5, (a6)
-amomin.w.rl a5, a6, (a7)
-amomax.w.rl s7, s6, (s5)
-amominu.w.rl s6, s5, (s4)
-amomaxu.w.rl s5, s4, (s3)
-
-amoswap.w.aqrl a4, ra, (s0)
-amoadd.w.aqrl a1, a2, (a3)
-amoxor.w.aqrl a2, a3, (a4)
-amoand.w.aqrl a3, a4, (a5)
-amoor.w.aqrl a4, a5, (a6)
-amomin.w.aqrl a5, a6, (a7)
-amomax.w.aqrl s7, s6, (s5)
-amominu.w.aqrl s6, s5, (s4)
-amomaxu.w.aqrl s5, s4, (s3)
-
-amoswap.d a4, ra, (s0)
-amoadd.d a1, a2, (a3)
-amoxor.d a2, a3, (a4)
-amoand.d a3, a4, (a5)
-amoor.d a4, a5, (a6)
-amomin.d a5, a6, (a7)
-amomax.d s7, s6, (s5)
-amominu.d s6, s5, (s4)
-amomaxu.d s5, s4, (s3)
-
-amoswap.d.aq a4, ra, (s0)
-amoadd.d.aq a1, a2, (a3)
-amoxor.d.aq a2, a3, (a4)
-amoand.d.aq a3, a4, (a5)
-amoor.d.aq a4, a5, (a6)
-amomin.d.aq a5, a6, (a7)
-amomax.d.aq s7, s6, (s5)
-amominu.d.aq s6, s5, (s4)
-amomaxu.d.aq s5, s4, (s3)
-
-amoswap.d.rl a4, ra, (s0)
-amoadd.d.rl a1, a2, (a3)
-amoxor.d.rl a2, a3, (a4)
-amoand.d.rl a3, a4, (a5)
-amoor.d.rl a4, a5, (a6)
-amomin.d.rl a5, a6, (a7)
-amomax.d.rl s7, s6, (s5)
-amominu.d.rl s6, s5, (s4)
-amomaxu.d.rl s5, s4, (s3)
-
-amoswap.d.aqrl a4, ra, (s0)
-amoadd.d.aqrl a1, a2, (a3)
-amoxor.d.aqrl a2, a3, (a4)
-amoand.d.aqrl a3, a4, (a5)
-amoor.d.aqrl a4, a5, (a6)
-amomin.d.aqrl a5, a6, (a7)
-amomax.d.aqrl s7, s6, (s5)
-amominu.d.aqrl s6, s5, (s4)
-amomaxu.d.aqrl s5, s4, (s3)
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/atomic.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.test
similarity index 65%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.test
index 78f4e7f50c745..240d935479ec5 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.test
@@ -1,133 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Floating-Point Load and Store Instructions
-## Half-Precision
-flh ft0, 0(a0)
-fsh ft0, 0(a0)
-
-## Single-Precision
-flw ft0, 0(a0)
-fsw ft0, 0(a0)
-
-## Double-Precision
-fld ft0, 0(a0)
-fsd ft0, 0(a0)
-
-# Floating-Point Computational Instructions
-## Half-Precision
-fadd.h f26, f27, f28
-fsub.h f29, f30, f31
-fmul.h ft0, ft1, ft2
-fdiv.h ft3, ft4, ft5
-fsqrt.h ft6, ft7
-fmin.h fa5, fa6, fa7
-fmax.h fs2, fs3, fs4
-fmadd.h f10, f11, f12, f31
-fmsub.h f14, f15, f16, f17
-fnmsub.h f18, f19, f20, f21
-fnmadd.h f22, f23, f24, f25
-
-## Single-Precision
-fadd.s f26, f27, f28
-fsub.s f29, f30, f31
-fmul.s ft0, ft1, ft2
-fdiv.s ft3, ft4, ft5
-fsqrt.s ft6, ft7
-fmin.s fa5, fa6, fa7
-fmax.s fs2, fs3, fs4
-fmadd.s f10, f11, f12, f31
-fmsub.s f14, f15, f16, f17
-fnmsub.s f18, f19, f20, f21
-fnmadd.s f22, f23, f24, f25
-
-## Double-Precision
-fadd.d f26, f27, f28
-fsub.d f29, f30, f31
-fmul.d ft0, ft1, ft2
-fdiv.d ft3, ft4, ft5
-fsqrt.d ft6, ft7
-fmin.d fa5, fa6, fa7
-fmax.d fs2, fs3, fs4
-fmadd.d f10, f11, f12, f31
-fmsub.d f14, f15, f16, f17
-fnmsub.d f18, f19, f20, f21
-fnmadd.d f22, f23, f24, f25
-
-# Floating-Point Conversion and Move Instructions
-## Half-Precision
-fmv.x.h a2, fs7
-fmv.h.x ft1, a6
-
-fcvt.s.h fa0, ft0
-fcvt.s.h fa0, ft0, rup
-
-fcvt.h.s ft2, fa2
-fcvt.d.h fa0, ft0
-
-fcvt.d.h fa0, ft0, rup
-fcvt.h.d ft2, fa2
-
-## Single-Precision
-fcvt.w.s a0, fs5
-fcvt.wu.s a1, fs6
-fcvt.s.w ft11, a4
-fcvt.s.wu ft0, a5
-
-fcvt.l.s a0, ft0
-fcvt.lu.s a1, ft1
-fcvt.s.l ft2, a2
-fcvt.s.lu ft3, a3
-
-fmv.x.w a2, fs7
-fmv.w.x ft1, a6
-
-fsgnj.s fs1, fa0, fa1
-fsgnjn.s fa1, fa3, fa4
-
-## Double-Precision
-fcvt.wu.d a4, ft11
-fcvt.w.d a4, ft11
-fcvt.d.w ft0, a5
-fcvt.d.wu ft1, a6
-
-fcvt.s.d fs5, fs6
-fcvt.d.s fs7, fs8
-
-fcvt.l.d a0, ft0
-fcvt.lu.d a1, ft1
-fcvt.d.l ft3, a3
-fcvt.d.lu ft4, a4
-
-fmv.x.d a2, ft2
-fmv.d.x ft5, a5
-
-fsgnj.d fs1, fa0, fa1
-fsgnjn.d fa1, fa3, fa4
-
-# Floating-Point Compare Instructions
-## Half-Precision
-feq.h a1, fs8, fs9
-flt.h a2, fs10, fs11
-fle.h a3, ft8, ft9
-
-## Single-Precision
-feq.s a1, fs8, fs9
-flt.s a2, fs10, fs11
-fle.s a3, ft8, ft9
-
-## Double-Precision
-feq.d a1, fs8, fs9
-flt.d a2, fs10, fs11
-fle.d a3, ft8, ft9
-
-# Floating-Point Classify Instruction
-## Half-Precision
-fclass.s a3, ft10
-## Single-Precision
-fclass.s a3, ft10
-## Double-Precision
-fclass.d a3, ft10
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/floating-point.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
@@ -151,23 +23,10 @@ fclass.d a3, ft10
# CHECK-NEXT: [9]: LLVM Opcode Name
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FLH flh ft0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FSH fsh ft0, 0(a0)
# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FLW flw ft0, 0(a0)
# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FSW fsw ft0, 0(a0)
# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FLD fld ft0, 0(a0)
# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FSD fsd ft0, 0(a0)
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FADD_H fadd.h fs10, fs11, ft8
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FSUB_H fsub.h ft9, ft10, ft11
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMUL_H fmul.h ft0, ft1, ft2
-# CHECK-NEXT: 1 12 12.00 12 SMX60_FP[12] FDIV_H fdiv.h ft3, ft4, ft5
-# CHECK-NEXT: 1 12 12.00 12 SMX60_FP[12] FSQRT_H fsqrt.h ft6, ft7
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMIN_H fmin.h fa5, fa6, fa7
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMAX_H fmax.h fs2, fs3, fs4
-# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FMADD_H fmadd.h fa0, fa1, fa2, ft11
-# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FMSUB_H fmsub.h fa4, fa5, fa6, fa7
-# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FNMSUB_H fnmsub.h fs2, fs3, fs4, fs5
-# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FNMADD_H fnmadd.h fs6, fs7, fs8, fs9
# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FADD_S fadd.s fs10, fs11, ft8
# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FSUB_S fsub.s ft9, ft10, ft11
# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMUL_S fmul.s ft0, ft1, ft2
@@ -190,14 +49,6 @@ fclass.d a3, ft10
# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FMSUB_D fmsub.d fa4, fa5, fa6, fa7
# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FNMSUB_D fnmsub.d fs2, fs3, fs4, fs5
# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FNMADD_D fnmadd.d fs6, fs7, fs8, fs9
-# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FMV_X_H fmv.x.h a2, fs7
-# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FMV_H_X fmv.h.x ft1, a6
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_S_H fcvt.s.h fa0, ft0
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_S_H fcvt.s.h fa0, ft0, rup
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_H_S fcvt.h.s ft2, fa2
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_D_H fcvt.d.h fa0, ft0
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_D_H fcvt.d.h fa0, ft0, rup
-# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_H_D fcvt.h.d ft2, fa2
# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FCVT_W_S fcvt.w.s a0, fs5
# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FCVT_WU_S fcvt.wu.s a1, fs6
# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FCVT_S_W fcvt.s.w ft11, a4
@@ -224,9 +75,6 @@ fclass.d a3, ft10
# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FMV_D_X fmv.d.x ft5, a5
# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FSGNJ_D fsgnj.d fs1, fa0, fa1
# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FSGNJN_D fsgnjn.d fa1, fa3, fa4
-# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FEQ_H feq.h a1, fs8, fs9
-# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLT_H flt.h a2, fs10, fs11
-# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLE_H fle.h a3, ft8, ft9
# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FEQ_S feq.s a1, fs8, fs9
# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLT_S flt.s a2, fs10, fs11
# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLE_S fle.s a3, ft8, ft9
@@ -234,7 +82,6 @@ fclass.d a3, ft10
# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLT_D flt.d a2, fs10, fs11
# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLE_D fle.d a3, ft8, ft9
# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FCLASS_S fclass.s a3, ft10
-# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FCLASS_S fclass.s a3, ft10
# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FCLASS_D fclass.d a3, ft10
# CHECK: Resources:
@@ -249,27 +96,14 @@ fclass.d a3, ft10
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
-# CHECK-NEXT: 149.00 11.00 11.00 3.00 3.00 - - -
+# CHECK-NEXT: 106.00 10.00 10.00 2.00 2.00 - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
-# CHECK-NEXT: - - - 0.50 0.50 - - - flh ft0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - fsh ft0, 0(a0)
# CHECK-NEXT: - - - 0.50 0.50 - - - flw ft0, 0(a0)
# CHECK-NEXT: - - - 0.50 0.50 - - - fsw ft0, 0(a0)
# CHECK-NEXT: - - - 0.50 0.50 - - - fld ft0, 0(a0)
# CHECK-NEXT: - - - 0.50 0.50 - - - fsd ft0, 0(a0)
-# CHECK-NEXT: 1.00 - - - - - - - fadd.h fs10, fs11, ft8
-# CHECK-NEXT: 1.00 - - - - - - - fsub.h ft9, ft10, ft11
-# CHECK-NEXT: 1.00 - - - - - - - fmul.h ft0, ft1, ft2
-# CHECK-NEXT: 12.00 - - - - - - - fdiv.h ft3, ft4, ft5
-# CHECK-NEXT: 12.00 - - - - - - - fsqrt.h ft6, ft7
-# CHECK-NEXT: 1.00 - - - - - - - fmin.h fa5, fa6, fa7
-# CHECK-NEXT: 1.00 - - - - - - - fmax.h fs2, fs3, fs4
-# CHECK-NEXT: 1.00 - - - - - - - fmadd.h fa0, fa1, fa2, ft11
-# CHECK-NEXT: 1.00 - - - - - - - fmsub.h fa4, fa5, fa6, fa7
-# CHECK-NEXT: 1.00 - - - - - - - fnmsub.h fs2, fs3, fs4, fs5
-# CHECK-NEXT: 1.00 - - - - - - - fnmadd.h fs6, fs7, fs8, fs9
# CHECK-NEXT: 1.00 - - - - - - - fadd.s fs10, fs11, ft8
# CHECK-NEXT: 1.00 - - - - - - - fsub.s ft9, ft10, ft11
# CHECK-NEXT: 1.00 - - - - - - - fmul.s ft0, ft1, ft2
@@ -292,14 +126,6 @@ fclass.d a3, ft10
# CHECK-NEXT: 1.00 - - - - - - - fmsub.d fa4, fa5, fa6, fa7
# CHECK-NEXT: 1.00 - - - - - - - fnmsub.d fs2, fs3, fs4, fs5
# CHECK-NEXT: 1.00 - - - - - - - fnmadd.d fs6, fs7, fs8, fs9
-# CHECK-NEXT: - 0.50 0.50 - - - - - fmv.x.h a2, fs7
-# CHECK-NEXT: - 0.50 0.50 - - - - - fmv.h.x ft1, a6
-# CHECK-NEXT: 1.00 - - - - - - - fcvt.s.h fa0, ft0
-# CHECK-NEXT: 1.00 - - - - - - - fcvt.s.h fa0, ft0, rup
-# CHECK-NEXT: 1.00 - - - - - - - fcvt.h.s ft2, fa2
-# CHECK-NEXT: 1.00 - - - - - - - fcvt.d.h fa0, ft0
-# CHECK-NEXT: 1.00 - - - - - - - fcvt.d.h fa0, ft0, rup
-# CHECK-NEXT: 1.00 - - - - - - - fcvt.h.d ft2, fa2
# CHECK-NEXT: - 0.50 0.50 - - - - - fcvt.w.s a0, fs5
# CHECK-NEXT: - 0.50 0.50 - - - - - fcvt.wu.s a1, fs6
# CHECK-NEXT: - 0.50 0.50 - - - - - fcvt.s.w ft11, a4
@@ -326,9 +152,6 @@ fclass.d a3, ft10
# CHECK-NEXT: - 0.50 0.50 - - - - - fmv.d.x ft5, a5
# CHECK-NEXT: 1.00 - - - - - - - fsgnj.d fs1, fa0, fa1
# CHECK-NEXT: 1.00 - - - - - - - fsgnjn.d fa1, fa3, fa4
-# CHECK-NEXT: 1.00 - - - - - - - feq.h a1, fs8, fs9
-# CHECK-NEXT: 1.00 - - - - - - - flt.h a2, fs10, fs11
-# CHECK-NEXT: 1.00 - - - - - - - fle.h a3, ft8, ft9
# CHECK-NEXT: 1.00 - - - - - - - feq.s a1, fs8, fs9
# CHECK-NEXT: 1.00 - - - - - - - flt.s a2, fs10, fs11
# CHECK-NEXT: 1.00 - - - - - - - fle.s a3, ft8, ft9
@@ -336,5 +159,4 @@ fclass.d a3, ft10
# CHECK-NEXT: 1.00 - - - - - - - flt.d a2, fs10, fs11
# CHECK-NEXT: 1.00 - - - - - - - fle.d a3, ft8, ft9
# CHECK-NEXT: 1.00 - - - - - - - fclass.s a3, ft10
-# CHECK-NEXT: 1.00 - - - - - - - fclass.s a3, ft10
# CHECK-NEXT: 1.00 - - - - - - - fclass.d a3, ft10
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
deleted file mode 100644
index 51a036aaae784..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
+++ /dev/null
@@ -1,437 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Integer Register-Immediate Instructions
-addi a0, a0, 1
-addiw a0, a0, 1
-slti a0, a0, 1
-sltiu a0, a0, 1
-
-andi a0, a0, 1
-ori a0, a0, 1
-xori a0, a0, 1
-
-slli a0, a0, 1
-srli a0, a0, 1
-srai a0, a0, 1
-slliw a0, a0, 1
-srliw a0, a0, 1
-sraiw a0, a0, 1
-
-lui a0, 1
-auipc a1, 1
-
-# Integer Register-Register Operations
-add a0, a0, a1
-addw a0, a0, a0
-slt a0, a0, a0
-sltu a0, a0, a0
-
-and a0, a0, a0
-or a0, a0, a0
-xor a0, a0, a0
-
-sll a0, a0, a0
-srl a0, a0, a0
-sra a0, a0, a0
-sllw a0, a0, a0
-srlw a0, a0, a0
-sraw a0, a0, a0
-
-sub a0, a0, a0
-subw a0, a0, a0
-
-# Control Transfer Instructions
-
-## Unconditional Jumps
-jal a0, 1f
-1:
-jalr a0
-beq a0, a0, 1f
-1:
-bne a0, a0, 1f
-1:
-blt a0, a0, 1f
-1:
-bltu a0, a0, 1f
-1:
-bge a0, a0, 1f
-1:
-bgeu a0, a0, 1f
-1:
-add a0, a0, a0
-
-# Load and Store Instructions
-lb t0, 0(a0)
-lbu t0, 0(a0)
-lh t0, 0(a0)
-lhu t0, 0(a0)
-lw t0, 0(a0)
-lwu t0, 0(a0)
-ld t0, 0(a0)
-
-sb t0, 0(a0)
-sh t0, 0(a0)
-sw t0, 0(a0)
-sd t0, 0(a0)
-
-# Multiply/Division
-mul a0, a0, a0
-mulh a0, a0, a0
-mulhu a0, a0, a0
-mulhsu a0, a0, a0
-mulw a0, a0, a0
-div a0, a1, a2
-divu a0, a1, a2
-rem a0, a1, a2
-remu a0, a1, a2
-divw a0, a1, a2
-divuw a0, a1, a2
-remw a0, a1, a2
-remuw a0, a1, a2
-
-# Zicsr
-csrrw t0, 0xfff, t1
-csrrs s3, 0x001, s5
-csrrc sp, 0x000, ra
-csrrwi a5, 0x000, 0
-csrrsi t2, 0xfff, 31
-csrrci t1, 0x140, 5
-
-# Zicond
-czero.eqz a0, a1, a2
-czero.nez a0, a1, a2
-
-# Zicond
-czero.eqz a0, a1, a2
-czero.nez a0, a1, a2
-
-# Zba
-add.uw a0, a0, a0
-slli.uw a0, a0, 1
-sh1add.uw a0, a0, a0
-sh2add.uw a0, a0, a0
-sh3add.uw a0, a0, a0
-sh1add a0, a0, a0
-sh2add a0, a0, a0
-sh3add a0, a0, a0
-
-# Zbb
-andn a0, a0, a0
-orn a0, a0, a0
-xnor a0, a0, a0
-
-clz a0, a0
-clzw a0, a0
-ctz a0, a0
-ctzw a0, a0
-
-cpop a0, a0
-cpopw a0, a0
-
-min a0, a0, a0
-minu a0, a0, a0
-max a0, a0, a0
-maxu a0, a0, a0
-
-sext.b a0, a0
-sext.h a0, a0
-zext.h a0, a0
-
-rol a0, a0, a0
-rolw a0, a0, a0
-ror a0, a0, a0
-rorw a0, a0, a0
-rori a0, a0, 1
-roriw a0, a0, 1
-
-orc.b a0, a0
-
-rev8 a0, a0
-
-# Zbc
-clmul a0, a0, a0
-clmulr a0, a0, a0
-clmulh a0, a0, a0
-
-# Zbs
-bclr a0, a1, a2
-bclri a0, a1, 1
-bext a0, a1, a2
-bexti a0, a1, 1
-binv a0, a1, a2
-binvi a0, a1, 1
-bset a0, a1, a2
-bseti a0, a1, 1
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SMX60_FP:1
-# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
-# CHECK-NEXT: [2] - SMX60_IEUA:1
-# CHECK-NEXT: [3] - SMX60_IEUB:1
-# CHECK-NEXT: [4] - SMX60_LS:2
-# CHECK-NEXT: [5] - SMX60_VFP:1
-# CHECK-NEXT: [6] - SMX60_VIEU:1
-# CHECK-NEXT: [7] - SMX60_VLS:1
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-# CHECK-NEXT: [7]: Bypass Latency
-# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
-# CHECK-NEXT: [9]: LLVM Opcode Name
-
-# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADDI addi a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADDIW addiw a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLTI slti a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLTIU seqz a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ANDI andi a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ORI ori a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU XORI xori a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SLLI slli a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SRLI srli a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SRAI srai a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLLIW slliw a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRLIW srliw a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRAIW sraiw a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_LUI lui a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU AUIPC auipc a1, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADD add a0, a0, a1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADDW addw a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLT slt a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLTU sltu a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_AND and a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_OR or a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_XOR xor a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLL sll a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRL srl a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRA sra a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLLW sllw a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRLW srlw a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRAW sraw a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SUB sub a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SUBW subw a0, a0, a0
-# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA JAL jal a0, .Ltmp0
-# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA C_JALR jalr a0
-# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BEQ beq a0, a0, .Ltmp1
-# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BNE bne a0, a0, .Ltmp2
-# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BLT blt a0, a0, .Ltmp3
-# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BLTU bltu a0, a0, .Ltmp4
-# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BGE bge a0, a0, .Ltmp5
-# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BGEU bgeu a0, a0, .Ltmp6
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADD add a0, a0, a0
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LB lb t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LBU lbu t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LH lh t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LHU lhu t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LW lw t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LWU lwu t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LD ld t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SB sb t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SH sh t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SW sw t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SD sd t0, 0(a0)
-# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MUL mul a0, a0, a0
-# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULH mulh a0, a0, a0
-# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULHU mulhu a0, a0, a0
-# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULHSU mulhsu a0, a0, a0
-# CHECK-NEXT: 1 3 0.50 3 SMX60_IEU MULW mulw a0, a0, a0
-# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] DIV div a0, a1, a2
-# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] DIVU divu a0, a1, a2
-# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] REM rem a0, a1, a2
-# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] REMU remu a0, a1, a2
-# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] DIVW divw a0, a1, a2
-# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] DIVUW divuw a0, a1, a2
-# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] REMW remw a0, a1, a2
-# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] REMUW remuw a0, a1, a2
-# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRW csrrw t0, 4095, t1
-# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRS csrrs s3, fflags, s5
-# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRC csrrc sp, 0, ra
-# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRWI csrrwi a5, 0, 0
-# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRSI csrrsi t2, 4095, 31
-# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRCI csrrci t1, sscratch, 5
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_EQZ czero.eqz a0, a1, a2
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_NEZ czero.nez a0, a1, a2
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_EQZ czero.eqz a0, a1, a2
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_NEZ czero.nez a0, a1, a2
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ADD_UW add.uw a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLLI_UW slli.uw a0, a0, 1
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH1ADD_UW sh1add.uw a0, a0, a0
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH2ADD_UW sh2add.uw a0, a0, a0
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH3ADD_UW sh3add.uw a0, a0, a0
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH1ADD sh1add a0, a0, a0
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH2ADD sh2add a0, a0, a0
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH3ADD sh3add a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ANDN andn a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ORN orn a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU XNOR xnor a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CLZ clz a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CLZW clzw a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CTZ ctz a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CTZW ctzw a0, a0
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CPOP cpop a0, a0
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CPOPW cpopw a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MIN min a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MINU minu a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MAX max a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MAXU maxu a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SEXT_B sext.b a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SEXT_H sext.h a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ZEXT_H_RV64 zext.h a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ROL rol a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ROLW rolw a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ROR ror a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU RORW rorw a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU RORI rori a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU RORIW roriw a0, a0, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ORC_B orc.b a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU REV8_RV64 rev8 a0, a0
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CLMUL clmul a0, a0, a0
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CLMULR clmulr a0, a0, a0
-# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CLMULH clmulh a0, a0, a0
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BCLR bclr a0, a1, a2
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BCLRI bclri a0, a1, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BEXT bext a0, a1, a2
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BEXTI bexti a0, a1, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BINV binv a0, a1, a2
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BINVI binvi a0, a1, 1
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BSET bset a0, a1, a2
-# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BSETI bseti a0, a1, 1
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SMX60_FP
-# CHECK-NEXT: [1] - SMX60_IEUA
-# CHECK-NEXT: [2] - SMX60_IEUB
-# CHECK-NEXT: [3.0] - SMX60_LS
-# CHECK-NEXT: [3.1] - SMX60_LS
-# CHECK-NEXT: [4] - SMX60_VFP
-# CHECK-NEXT: [5] - SMX60_VIEU
-# CHECK-NEXT: [6] - SMX60_VLS
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
-# CHECK-NEXT: - 180.50 44.50 5.50 5.50 - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
-# CHECK-NEXT: - 0.50 0.50 - - - - - addi a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - addiw a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - slti a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - seqz a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - andi a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - ori a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - xori a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - slli a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - srli a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - srai a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - slliw a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - srliw a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - sraiw a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - lui a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - auipc a1, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - add a0, a0, a1
-# CHECK-NEXT: - 0.50 0.50 - - - - - addw a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - slt a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sltu a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - and a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - or a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - xor a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sll a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - srl a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sra a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sllw a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - srlw a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sraw a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sub a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - subw a0, a0, a0
-# CHECK-NEXT: - 1.00 - - - - - - jal a0, .Ltmp0
-# CHECK-NEXT: - 1.00 - - - - - - jalr a0
-# CHECK-NEXT: - 1.00 - - - - - - beq a0, a0, .Ltmp1
-# CHECK-NEXT: - 1.00 - - - - - - bne a0, a0, .Ltmp2
-# CHECK-NEXT: - 1.00 - - - - - - blt a0, a0, .Ltmp3
-# CHECK-NEXT: - 1.00 - - - - - - bltu a0, a0, .Ltmp4
-# CHECK-NEXT: - 1.00 - - - - - - bge a0, a0, .Ltmp5
-# CHECK-NEXT: - 1.00 - - - - - - bgeu a0, a0, .Ltmp6
-# CHECK-NEXT: - 0.50 0.50 - - - - - add a0, a0, a0
-# CHECK-NEXT: - - - 0.50 0.50 - - - lb t0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - lbu t0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - lh t0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - lhu t0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - lw t0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - lwu t0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - ld t0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - sb t0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - sh t0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - sw t0, 0(a0)
-# CHECK-NEXT: - - - 0.50 0.50 - - - sd t0, 0(a0)
-# CHECK-NEXT: - 0.50 0.50 - - - - - mul a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - mulh a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - mulhu a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - mulhsu a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - mulw a0, a0, a0
-# CHECK-NEXT: - 20.00 - - - - - - div a0, a1, a2
-# CHECK-NEXT: - 20.00 - - - - - - divu a0, a1, a2
-# CHECK-NEXT: - 20.00 - - - - - - rem a0, a1, a2
-# CHECK-NEXT: - 20.00 - - - - - - remu a0, a1, a2
-# CHECK-NEXT: - 12.00 - - - - - - divw a0, a1, a2
-# CHECK-NEXT: - 12.00 - - - - - - divuw a0, a1, a2
-# CHECK-NEXT: - 12.00 - - - - - - remw a0, a1, a2
-# CHECK-NEXT: - 12.00 - - - - - - remuw a0, a1, a2
-# CHECK-NEXT: - 0.50 0.50 - - - - - csrrw t0, 4095, t1
-# CHECK-NEXT: - 0.50 0.50 - - - - - csrrs s3, fflags, s5
-# CHECK-NEXT: - 0.50 0.50 - - - - - csrrc sp, 0, ra
-# CHECK-NEXT: - 0.50 0.50 - - - - - csrrwi a5, 0, 0
-# CHECK-NEXT: - 0.50 0.50 - - - - - csrrsi t2, 4095, 31
-# CHECK-NEXT: - 0.50 0.50 - - - - - csrrci t1, sscratch, 5
-# CHECK-NEXT: - 0.50 0.50 - - - - - czero.eqz a0, a1, a2
-# CHECK-NEXT: - 0.50 0.50 - - - - - czero.nez a0, a1, a2
-# CHECK-NEXT: - 0.50 0.50 - - - - - czero.eqz a0, a1, a2
-# CHECK-NEXT: - 0.50 0.50 - - - - - czero.nez a0, a1, a2
-# CHECK-NEXT: - 0.50 0.50 - - - - - add.uw a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - slli.uw a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - sh1add.uw a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sh2add.uw a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sh3add.uw a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sh1add a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sh2add a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sh3add a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - andn a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - orn a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - xnor a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - clz a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - clzw a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - ctz a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - ctzw a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - cpop a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - cpopw a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - min a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - minu a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - max a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - maxu a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sext.b a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - sext.h a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - zext.h a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - rol a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - rolw a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - ror a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - rorw a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - rori a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - roriw a0, a0, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - orc.b a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - rev8 a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - clmul a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - clmulr a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - clmulh a0, a0, a0
-# CHECK-NEXT: - 0.50 0.50 - - - - - bclr a0, a1, a2
-# CHECK-NEXT: - 0.50 0.50 - - - - - bclri a0, a1, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - bext a0, a1, a2
-# CHECK-NEXT: - 0.50 0.50 - - - - - bexti a0, a1, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - binv a0, a1, a2
-# CHECK-NEXT: - 0.50 0.50 - - - - - binvi a0, a1, 1
-# CHECK-NEXT: - 0.50 0.50 - - - - - bset a0, a1, a2
-# CHECK-NEXT: - 0.50 0.50 - - - - - bseti a0, a1, 1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.test
new file mode 100644
index 0000000000000..bd0939223a094
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.test
@@ -0,0 +1,154 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADDI addi a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADDIW addiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLTI slti a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLTIU seqz a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ANDI andi a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ORI ori a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU XORI xori a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SLLI slli a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SRLI srli a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SRAI srai a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLLIW slliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRLIW srliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRAIW sraiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_LUI lui a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU AUIPC auipc a1, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADD add a0, a0, a1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADDW addw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLT slt a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLTU sltu a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_AND and a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_OR or a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_XOR xor a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLL sll a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRL srl a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRA sra a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLLW sllw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRLW srlw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SRAW sraw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SUB sub a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_SUBW subw a0, a0, a0
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA JAL jal a0, .Ltmp0
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA C_JALR jalr a0
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BEQ beq a0, a0, .Ltmp1
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BNE bne a0, a0, .Ltmp2
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BLT blt a0, a0, .Ltmp3
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BLTU bltu a0, a0, .Ltmp4
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BGE bge a0, a0, .Ltmp5
+# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BGEU bgeu a0, a0, .Ltmp6
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADD add a0, a0, a0
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LB lb t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LBU lbu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LH lh t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LHU lhu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LW lw t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LWU lwu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LD ld t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SB sb t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SH sh t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SW sw t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SD sd t0, 0(a0)
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRW csrrw t0, 4095, t1
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRS csrrs s3, fflags, s5
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRC csrrc sp, 0, ra
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRWI csrrwi a5, 0, 0
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRSI csrrsi t2, 4095, 31
+# CHECK-NEXT: 1 1 0.50 U 1 SMX60_IEU CSRRCI csrrci t1, sscratch, 5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 26.50 18.50 5.50 5.50 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 0.50 0.50 - - - - - addi a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - addiw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - slti a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - seqz a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - andi a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - ori a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - xori a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - slli a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - srli a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - srai a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - slliw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - srliw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - sraiw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - lui a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - auipc a1, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - add a0, a0, a1
+# CHECK-NEXT: - 0.50 0.50 - - - - - addw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - slt a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sltu a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - and a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - or a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - xor a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sll a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - srl a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sra a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sllw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - srlw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sraw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sub a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - subw a0, a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - jal a0, .Ltmp0
+# CHECK-NEXT: - 1.00 - - - - - - jalr a0
+# CHECK-NEXT: - 1.00 - - - - - - beq a0, a0, .Ltmp1
+# CHECK-NEXT: - 1.00 - - - - - - bne a0, a0, .Ltmp2
+# CHECK-NEXT: - 1.00 - - - - - - blt a0, a0, .Ltmp3
+# CHECK-NEXT: - 1.00 - - - - - - bltu a0, a0, .Ltmp4
+# CHECK-NEXT: - 1.00 - - - - - - bge a0, a0, .Ltmp5
+# CHECK-NEXT: - 1.00 - - - - - - bgeu a0, a0, .Ltmp6
+# CHECK-NEXT: - 0.50 0.50 - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - 0.50 0.50 - - - lb t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - lbu t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - lh t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - lhu t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - lw t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - lwu t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - ld t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - sb t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - sh t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - sw t0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - sd t0, 0(a0)
+# CHECK-NEXT: - 0.50 0.50 - - - - - csrrw t0, 4095, t1
+# CHECK-NEXT: - 0.50 0.50 - - - - - csrrs s3, fflags, s5
+# CHECK-NEXT: - 0.50 0.50 - - - - - csrrc sp, 0, ra
+# CHECK-NEXT: - 0.50 0.50 - - - - - csrrwi a5, 0, 0
+# CHECK-NEXT: - 0.50 0.50 - - - - - csrrsi t2, 4095, 31
+# CHECK-NEXT: - 0.50 0.50 - - - - - csrrci t1, sscratch, 5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/mul-div.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/mul-div.test
new file mode 100644
index 0000000000000..c57eb0077d35d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/mul-div.test
@@ -0,0 +1,68 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/mul-div.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MUL mul a0, a0, a0
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULH mulh a0, a0, a0
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULHU mulhu a0, a0, a0
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULHSU mulhsu a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 SMX60_IEU MULW mulw a0, a0, a0
+# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] DIV div a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] DIVU divu a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] REM rem a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 20 SMX60_IEU[20],SMX60_IEUA[20] REMU remu a0, a1, a2
+# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] DIVW divw a0, a1, a2
+# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] DIVUW divuw a0, a1, a2
+# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] REMW remw a0, a1, a2
+# CHECK-NEXT: 1 12 12.00 12 SMX60_IEU[12],SMX60_IEUA[12] REMUW remuw a0, a1, a2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 130.50 2.50 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 0.50 0.50 - - - - - mul a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - mulh a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - mulhu a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - mulhsu a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - mulw a0, a0, a0
+# CHECK-NEXT: - 20.00 - - - - - - div a0, a1, a2
+# CHECK-NEXT: - 20.00 - - - - - - divu a0, a1, a2
+# CHECK-NEXT: - 20.00 - - - - - - rem a0, a1, a2
+# CHECK-NEXT: - 20.00 - - - - - - remu a0, a1, a2
+# CHECK-NEXT: - 12.00 - - - - - - divw a0, a1, a2
+# CHECK-NEXT: - 12.00 - - - - - - divuw a0, a1, a2
+# CHECK-NEXT: - 12.00 - - - - - - remw a0, a1, a2
+# CHECK-NEXT: - 12.00 - - - - - - remuw a0, a1, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/arithmetic.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/arithmetic.test
index 7fff4337bbbb6..9a652491397ec 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-arithmetic.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/arithmetic.test
@@ -1,2303 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Basic arithmetic operations
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e8, m4, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e8, m8, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e16, mf2, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e16, mf4, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e16, m1, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e16, m2, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e16, m4, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e16, m8, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e32, mf2, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e32, m1, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e32, m2, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e32, m4, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e32, m8, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e64, m1, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e64, m2, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e64, m4, tu, mu
-vadd.vi v8, v8, 12
-vsetvli x28, x0, e64, m8, tu, mu
-vadd.vi v8, v8, 12
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vadd.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vadd.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vadd.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vadd.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vsub.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vsub.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vsub.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vsub.vx v8, v8, x30
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-vsetvli x28, x0, e8, mf4, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vssubu.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vssubu.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vssub.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vssub.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vssub.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vssub.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwaddu.wv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwaddu.wv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vwaddu.wx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vwaddu.wx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwadd.wv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwadd.wv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vwadd.wx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vwadd.wx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwsubu.wv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwsubu.wv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vwsubu.wx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vwsubu.wx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwsub.wv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwsub.wv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vwsub.wx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vwsub.wx v8, v16, x30
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/arithmetic.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/bitwise.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/bitwise.test
index 712de84d1598d..4091e31a5e76f 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-bitwise.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/bitwise.test
@@ -1,1459 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Bitwise and logical operations
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vand.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vand.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vand.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vand.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e8, m4, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e8, m8, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e16, mf2, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e16, mf4, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e16, m1, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e16, m2, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e16, m4, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e16, m8, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e32, mf2, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e32, m1, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e32, m2, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e32, m4, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e32, m8, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e64, m1, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e64, m2, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e64, m4, tu, mu
-vand.vi v8, v8, 12
-vsetvli x28, x0, e64, m8, tu, mu
-vand.vi v8, v8, 12
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vor.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vor.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vor.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vor.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e8, m4, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e8, m8, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e16, mf2, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e16, mf4, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e16, m1, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e16, m2, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e16, m4, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e16, m8, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e32, mf2, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e32, m1, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e32, m2, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e32, m4, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e32, m8, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e64, m1, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e64, m2, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e64, m4, tu, mu
-vor.vi v8, v8, 12
-vsetvli x28, x0, e64, m8, tu, mu
-vor.vi v8, v8, 12
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vxor.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vxor.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vxor.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vxor.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e8, m4, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e8, m8, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e16, mf2, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e16, mf4, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e16, m1, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e16, m2, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e16, m4, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e16, m8, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e32, mf2, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e32, m1, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e32, m2, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e32, m4, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e32, m8, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e64, m1, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e64, m2, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e64, m4, tu, mu
-vxor.vi v8, v8, 12
-vsetvli x28, x0, e64, m8, tu, mu
-vxor.vi v8, v8, 12
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vnsra.wv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vnsra.wv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vnsra.wx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vnsra.wx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vnsra.wi v8, v16, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vnsra.wi v8, v16, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vnsra.wi v8, v16, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vnsra.wi v8, v16, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vnsra.wi v8, v16, 12
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-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vssrl.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vssrl.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vssrl.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vssrl.vx v8, v8, x30
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/bitwise.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-comparison.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/comparison.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-comparison.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/comparison.test
index ec251b970237f..d4a87cd5181eb 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-comparison.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/comparison.test
@@ -1,907 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Comparison operations
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmseq.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmseq.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vmseq.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vmseq.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e8, m4, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e8, m8, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e16, mf2, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e16, mf4, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e16, m1, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e16, m2, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e16, m4, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e16, m8, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e32, mf2, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e32, m1, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e32, m2, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e32, m4, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e32, m8, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e64, m1, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e64, m2, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e64, m4, tu, mu
-vmseq.vi v8, v8, 12
-vsetvli x28, x0, e64, m8, tu, mu
-vmseq.vi v8, v8, 12
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmsle.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmsle.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vmsle.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vmsle.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e8, m4, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e8, m8, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e16, mf2, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e16, mf4, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e16, m1, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e16, m2, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e16, m4, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e16, m8, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e32, mf2, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e32, m1, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e32, m2, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e32, m4, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e32, m8, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e64, m1, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e64, m2, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e64, m4, tu, mu
-vmsle.vi v8, v8, 12
-vsetvli x28, x0, e64, m8, tu, mu
-vmsle.vi v8, v8, 12
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmsleu.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmsleu.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmsleu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmsleu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmsleu.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmsleu.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmsleu.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmsleu.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmsleu.vx v8, v8, x30
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-vsetvli x28, x0, e64, m8, tu, mu
-vmsltu.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vmsltu.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vmsltu.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmslt.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmslt.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vmslt.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vmslt.vx v8, v8, x30
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/comparison.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/conversion.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/conversion.test
index 315f26f3dcce0..ecf9541f9c33a 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-conversion.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/conversion.test
@@ -1,596 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Conversion operations
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e16, m8, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e32, m8, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e64, m1, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e64, m2, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e64, m4, tu, mu
-vsext.vf2 v8, v16
-vsetvli x28, x0, e64, m8, tu, mu
-vsext.vf2 v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e16, m8, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e32, m8, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e64, m1, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e64, m2, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e64, m4, tu, mu
-vzext.vf2 v8, v16
-vsetvli x28, x0, e64, m8, tu, mu
-vzext.vf2 v8, v16
-
-vsetvli x28, x0, e32, mf2, tu, mu
-vsext.vf4 v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vsext.vf4 v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vsext.vf4 v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vsext.vf4 v8, v16
-vsetvli x28, x0, e32, m8, tu, mu
-vsext.vf4 v8, v16
-vsetvli x28, x0, e64, m1, tu, mu
-vsext.vf4 v8, v16
-vsetvli x28, x0, e64, m2, tu, mu
-vsext.vf4 v8, v16
-vsetvli x28, x0, e64, m4, tu, mu
-vsext.vf4 v8, v16
-vsetvli x28, x0, e64, m8, tu, mu
-vsext.vf4 v8, v16
-
-vsetvli x28, x0, e32, mf2, tu, mu
-vzext.vf4 v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vzext.vf4 v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vzext.vf4 v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vzext.vf4 v8, v16
-vsetvli x28, x0, e32, m8, tu, mu
-vzext.vf4 v8, v16
-vsetvli x28, x0, e64, m1, tu, mu
-vzext.vf4 v8, v16
-vsetvli x28, x0, e64, m2, tu, mu
-vzext.vf4 v8, v16
-vsetvli x28, x0, e64, m4, tu, mu
-vzext.vf4 v8, v16
-vsetvli x28, x0, e64, m8, tu, mu
-vzext.vf4 v8, v16
-
-vsetvli x28, x0, e64, m1, tu, mu
-vsext.vf8 v8, v16
-vsetvli x28, x0, e64, m2, tu, mu
-vsext.vf8 v8, v16
-vsetvli x28, x0, e64, m4, tu, mu
-vsext.vf8 v8, v16
-vsetvli x28, x0, e64, m8, tu, mu
-vsext.vf8 v8, v16
-
-vsetvli x28, x0, e64, m1, tu, mu
-vzext.vf8 v8, v16
-vsetvli x28, x0, e64, m2, tu, mu
-vzext.vf8 v8, v16
-vsetvli x28, x0, e64, m4, tu, mu
-vzext.vf8 v8, v16
-vsetvli x28, x0, e64, m8, tu, mu
-vzext.vf8 v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfcvt.f.xu.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfcvt.f.xu.v v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfcvt.f.x.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfcvt.f.x.v v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfcvt.rtz.x.f.v v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfcvt.rtz.xu.f.v v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfcvt.x.f.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfcvt.x.f.v v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfcvt.xu.f.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfcvt.xu.f.v v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfncvt.f.f.w v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfncvt.f.f.w v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfncvt.f.f.w v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfncvt.f.f.w v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfncvt.f.f.w v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfncvt.f.f.w v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfncvt.f.f.w v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfncvt.f.f.w v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfncvt.f.f.w v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfncvt.f.xu.w v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfncvt.f.xu.w v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfncvt.f.xu.w v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfncvt.f.xu.w v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfncvt.f.xu.w v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfncvt.f.xu.w v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfncvt.f.xu.w v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfncvt.f.xu.w v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfncvt.f.xu.w v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfncvt.f.x.w v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfncvt.f.x.w v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfncvt.f.x.w v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfncvt.f.x.w v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfncvt.f.x.w v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfncvt.f.x.w v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfncvt.f.x.w v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfncvt.f.x.w v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfncvt.f.x.w v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfncvt.rod.f.f.w v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfncvt.rod.f.f.w v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfncvt.rod.f.f.w v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfncvt.rod.f.f.w v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfncvt.rod.f.f.w v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfncvt.rod.f.f.w v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfncvt.rod.f.f.w v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfncvt.rod.f.f.w v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfncvt.rod.f.f.w v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfncvt.rtz.x.f.w v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfncvt.rtz.x.f.w v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfncvt.rtz.x.f.w v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfncvt.rtz.x.f.w v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfncvt.rtz.x.f.w v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfncvt.rtz.x.f.w v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfncvt.rtz.x.f.w v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfncvt.rtz.x.f.w v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfncvt.rtz.x.f.w v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfncvt.rtz.xu.f.w v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfncvt.rtz.xu.f.w v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfncvt.rtz.xu.f.w v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfncvt.rtz.xu.f.w v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfncvt.rtz.xu.f.w v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfncvt.rtz.xu.f.w v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfncvt.rtz.xu.f.w v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfncvt.rtz.xu.f.w v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfncvt.rtz.xu.f.w v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfncvt.x.f.w v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfncvt.x.f.w v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfncvt.x.f.w v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfncvt.x.f.w v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfncvt.x.f.w v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfncvt.x.f.w v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfncvt.x.f.w v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfncvt.x.f.w v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfncvt.x.f.w v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfncvt.xu.f.w v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfncvt.xu.f.w v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfncvt.xu.f.w v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfncvt.xu.f.w v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfncvt.xu.f.w v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfncvt.xu.f.w v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfncvt.xu.f.w v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfncvt.xu.f.w v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfncvt.xu.f.w v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwcvt.f.f.v v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwcvt.f.f.v v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfwcvt.f.f.v v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfwcvt.f.f.v v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfwcvt.f.f.v v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwcvt.f.f.v v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfwcvt.f.f.v v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfwcvt.f.f.v v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfwcvt.f.f.v v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwcvt.f.x.v v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwcvt.f.x.v v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfwcvt.f.x.v v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfwcvt.f.x.v v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfwcvt.f.x.v v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwcvt.f.x.v v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfwcvt.f.x.v v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfwcvt.f.x.v v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfwcvt.f.x.v v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwcvt.f.xu.v v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwcvt.f.xu.v v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfwcvt.f.xu.v v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfwcvt.f.xu.v v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfwcvt.f.xu.v v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwcvt.f.xu.v v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfwcvt.f.xu.v v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfwcvt.f.xu.v v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfwcvt.f.xu.v v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwcvt.rtz.x.f.v v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwcvt.rtz.x.f.v v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfwcvt.rtz.x.f.v v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfwcvt.rtz.x.f.v v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfwcvt.rtz.x.f.v v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwcvt.rtz.x.f.v v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfwcvt.rtz.x.f.v v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfwcvt.rtz.x.f.v v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfwcvt.rtz.x.f.v v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwcvt.rtz.xu.f.v v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwcvt.rtz.xu.f.v v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfwcvt.rtz.xu.f.v v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfwcvt.rtz.xu.f.v v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfwcvt.rtz.xu.f.v v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwcvt.rtz.xu.f.v v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfwcvt.rtz.xu.f.v v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfwcvt.rtz.xu.f.v v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfwcvt.rtz.xu.f.v v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwcvt.x.f.v v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwcvt.x.f.v v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfwcvt.x.f.v v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfwcvt.x.f.v v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfwcvt.x.f.v v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwcvt.x.f.v v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfwcvt.x.f.v v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfwcvt.x.f.v v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfwcvt.x.f.v v8, v16
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwcvt.xu.f.v v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwcvt.xu.f.v v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vfwcvt.xu.f.v v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vfwcvt.xu.f.v v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vfwcvt.xu.f.v v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwcvt.xu.f.v v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vfwcvt.xu.f.v v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vfwcvt.xu.f.v v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vfwcvt.xu.f.v v8, v16
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/conversion.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test
index 9bf71ec82a562..282d278002c20 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fma.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test
@@ -1,736 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Fused multiply-add operations
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmacc.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmacc.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmacc.vx v8, x8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmacc.vx v8, x8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmadd.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmadd.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmadd.vx v8, x8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmadd.vx v8, x8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vnmsac.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vnmsac.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vnmsac.vx v8, x8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vnmsac.vx v8, x8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vnmsub.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vnmsub.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vnmsub.vx v8, x8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vnmsub.vx v8, x8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwmaccu.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwmaccu.vv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwmaccu.vx v8, x16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwmaccu.vx v8, x16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwmacc.vv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwmacc.vx v8, x16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwmacc.vx v8, x16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwmaccsu.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwmaccsu.vv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwmaccsu.vx v8, x16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwmaccsu.vx v8, x16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwmaccus.vx v8, x16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwmaccus.vx v8, x16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwmacc.vf v8, f16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwmacc.vf v8, f16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwmacc.vf v8, f16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwmacc.vf v8, f16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwmacc.vf v8, f16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwmacc.vf v8, f16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwmacc.vf v8, f16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwmacc.vf v8, f16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwmacc.vf v8, f16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwmacc.vv v8, v16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwmsac.vf v8, f16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwmsac.vf v8, f16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwmsac.vf v8, f16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwmsac.vf v8, f16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwmsac.vf v8, f16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwmsac.vf v8, f16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwmsac.vf v8, f16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwmsac.vf v8, f16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwmsac.vf v8, f16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwmsac.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwmsac.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwmsac.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwmsac.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwmsac.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwmsac.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwmsac.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwmsac.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwmsac.vv v8, v16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwnmacc.vf v8, f16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwnmacc.vf v8, f16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwnmacc.vf v8, f16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwnmacc.vf v8, f16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwnmacc.vf v8, f16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwnmacc.vf v8, f16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwnmacc.vf v8, f16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwnmacc.vf v8, f16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwnmacc.vf v8, f16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwnmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwnmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwnmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwnmacc.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwnmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwnmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwnmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwnmacc.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwnmacc.vv v8, v16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwnmsac.vf v8, f16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwnmsac.vf v8, f16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwnmsac.vf v8, f16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwnmsac.vf v8, f16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwnmsac.vf v8, f16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwnmsac.vf v8, f16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwnmsac.vf v8, f16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwnmsac.vf v8, f16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwnmsac.vf v8, f16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwnmsac.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwnmsac.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwnmsac.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwnmsac.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwnmsac.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwnmsac.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwnmsac.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwnmsac.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwnmsac.vv v8, v16, v24
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fma.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test
index e1b3bd6ed7b73..9fbb1f49e6640 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-fp.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test
@@ -1,1902 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Floating point operations
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e16, m8, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e32, m8, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e64, m1, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e64, m2, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e64, m4, tu, mu
-vmfeq.vf v8, v8, ft0
-vsetvli x28, x0, e64, m8, tu, mu
-vmfeq.vf v8, v8, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmfeq.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmfeq.vv v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e16, m8, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e32, m8, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e64, m1, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e64, m2, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e64, m4, tu, mu
-vmfge.vf v8, v8, ft0
-vsetvli x28, x0, e64, m8, tu, mu
-vmfge.vf v8, v8, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmfge.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmfge.vv v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e16, m8, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e32, m8, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e64, m1, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e64, m2, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e64, m4, tu, mu
-vmfgt.vf v8, v8, ft0
-vsetvli x28, x0, e64, m8, tu, mu
-vmfgt.vf v8, v8, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmfgt.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmfgt.vv v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vmfle.vf v8, v8, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vmfle.vf v8, v8, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vmfle.vf v8, v8, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vmfle.vf v8, v8, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vmfle.vf v8, v8, ft0
-vsetvli x28, x0, e16, m8, tu, mu
-vmfle.vf v8, v8, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vmfle.vf v8, v8, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vmfle.vf v8, v8, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vmfle.vf v8, v8, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vmfle.vf v8, v8, ft0
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-vfsgnjn.vf v8, v8, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vfsgnjn.vf v8, v8, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vfsgnjn.vf v8, v8, ft0
-vsetvli x28, x0, e32, m8, tu, mu
-vfsgnjn.vf v8, v8, ft0
-vsetvli x28, x0, e64, m1, tu, mu
-vfsgnjn.vf v8, v8, ft0
-vsetvli x28, x0, e64, m2, tu, mu
-vfsgnjn.vf v8, v8, ft0
-vsetvli x28, x0, e64, m4, tu, mu
-vfsgnjn.vf v8, v8, ft0
-vsetvli x28, x0, e64, m8, tu, mu
-vfsgnjn.vf v8, v8, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfsgnjn.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfsgnjn.vv v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e16, m8, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e32, m8, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e64, m1, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e64, m2, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e64, m4, tu, mu
-vfsgnj.vf v8, v8, ft0
-vsetvli x28, x0, e64, m8, tu, mu
-vfsgnj.vf v8, v8, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfsgnj.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfsgnj.vv v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e16, m8, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e32, m8, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e64, m1, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e64, m2, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e64, m4, tu, mu
-vfsgnjx.vf v8, v8, ft0
-vsetvli x28, x0, e64, m8, tu, mu
-vfsgnjx.vf v8, v8, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfsgnjx.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfsgnjx.vv v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwadd.vf v8, v16, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwadd.vf v8, v16, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vfwadd.vf v8, v16, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vfwadd.vf v8, v16, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vfwadd.vf v8, v16, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwadd.vf v8, v16, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vfwadd.vf v8, v16, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vfwadd.vf v8, v16, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vfwadd.vf v8, v16, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwadd.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwadd.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwadd.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwadd.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwadd.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwadd.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwadd.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwadd.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwadd.vv v8, v16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwadd.wf v8, v16, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwadd.wf v8, v16, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vfwadd.wf v8, v16, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vfwadd.wf v8, v16, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vfwadd.wf v8, v16, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwadd.wf v8, v16, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vfwadd.wf v8, v16, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vfwadd.wf v8, v16, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vfwadd.wf v8, v16, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwadd.wv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwadd.wv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwadd.wv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwadd.wv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwadd.wv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwadd.wv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwadd.wv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwadd.wv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwadd.wv v8, v16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwmul.vf v8, v16, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwmul.vf v8, v16, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vfwmul.vf v8, v16, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vfwmul.vf v8, v16, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vfwmul.vf v8, v16, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwmul.vf v8, v16, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vfwmul.vf v8, v16, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vfwmul.vf v8, v16, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vfwmul.vf v8, v16, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwmul.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwmul.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwmul.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwmul.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwmul.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwmul.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwmul.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwmul.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwmul.vv v8, v16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwsub.vf v8, v16, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwsub.vf v8, v16, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vfwsub.vf v8, v16, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vfwsub.vf v8, v16, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vfwsub.vf v8, v16, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwsub.vf v8, v16, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vfwsub.vf v8, v16, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vfwsub.vf v8, v16, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vfwsub.vf v8, v16, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwsub.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwsub.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwsub.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwsub.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwsub.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwsub.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwsub.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwsub.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwsub.vv v8, v16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwsub.wf v8, v16, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwsub.wf v8, v16, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vfwsub.wf v8, v16, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vfwsub.wf v8, v16, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vfwsub.wf v8, v16, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwsub.wf v8, v16, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vfwsub.wf v8, v16, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vfwsub.wf v8, v16, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vfwsub.wf v8, v16, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwsub.wv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwsub.wv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vfwsub.wv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vfwsub.wv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vfwsub.wv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwsub.wv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vfwsub.wv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vfwsub.wv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vfwsub.wv v8, v16, v24
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fp.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/mask.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/mask.test
index fade8fce901de..16527be3b656d 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-mask.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/mask.test
@@ -1,623 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Mask operations
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmand.mm v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmand.mm v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmnand.mm v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmnand.mm v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmandn.mm v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmandn.mm v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmxor.mm v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmxor.mm v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmor.mm v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmor.mm v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmnor.mm v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmnor.mm v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmorn.mm v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmorn.mm v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmxnor.mm v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmxnor.mm v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e8, mf4, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e8, mf8, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e8, m1, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e8, m2, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e8, m4, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e8, m8, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e16, mf2, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e16, m8, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e32, m8, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e64, m1, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e64, m2, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e64, m4, tu, mu
-vmsbf.m v8, v16
-vsetvli x28, x0, e64, m8, tu, mu
-vmsbf.m v8, v16
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e8, mf4, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e8, mf8, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e8, m1, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e8, m2, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e8, m4, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e8, m8, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e16, mf2, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e16, m8, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e32, m8, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e64, m1, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e64, m2, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e64, m4, tu, mu
-vmsif.m v8, v16
-vsetvli x28, x0, e64, m8, tu, mu
-vmsif.m v8, v16
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e8, mf4, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e8, mf8, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e8, m1, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e8, m2, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e8, m4, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e8, m8, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e16, mf2, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e16, m8, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e32, m8, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e64, m1, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e64, m2, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e64, m4, tu, mu
-vmsof.m v8, v16
-vsetvli x28, x0, e64, m8, tu, mu
-vmsof.m v8, v16
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vid.v v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vid.v v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vid.v v8
-vsetvli x28, x0, e8, m1, tu, mu
-vid.v v8
-vsetvli x28, x0, e8, m2, tu, mu
-vid.v v8
-vsetvli x28, x0, e8, m4, tu, mu
-vid.v v8
-vsetvli x28, x0, e8, m8, tu, mu
-vid.v v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vid.v v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vid.v v8
-vsetvli x28, x0, e16, m1, tu, mu
-vid.v v8
-vsetvli x28, x0, e16, m2, tu, mu
-vid.v v8
-vsetvli x28, x0, e16, m4, tu, mu
-vid.v v8
-vsetvli x28, x0, e16, m8, tu, mu
-vid.v v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vid.v v8
-vsetvli x28, x0, e32, m1, tu, mu
-vid.v v8
-vsetvli x28, x0, e32, m2, tu, mu
-vid.v v8
-vsetvli x28, x0, e32, m4, tu, mu
-vid.v v8
-vsetvli x28, x0, e32, m8, tu, mu
-vid.v v8
-vsetvli x28, x0, e64, m1, tu, mu
-vid.v v8
-vsetvli x28, x0, e64, m2, tu, mu
-vid.v v8
-vsetvli x28, x0, e64, m4, tu, mu
-vid.v v8
-vsetvli x28, x0, e64, m8, tu, mu
-vid.v v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vcpop.m x8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vcpop.m x8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfirst.m x8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfirst.m x8, v8
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mask.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-minmax.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/minmax.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-minmax.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/minmax.test
index d25e5897ed925..a96e593713703 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-minmax.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/minmax.test
@@ -1,367 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Min/max operations
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmax.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmax.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vmax.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vmax.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmaxu.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmaxu.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vmaxu.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vmaxu.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmin.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmin.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vmin.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vmin.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vminu.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vminu.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vminu.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vminu.vx v8, v8, x30
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/minmax.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/permutation.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/permutation.test
index c0fe5b94c9256..afe8adef82c02 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-permutation.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/permutation.test
@@ -1,1179 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Permutation and shuffle operations
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmv.v.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmv.v.v v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e8, m1, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e8, m2, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e8, m4, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e8, m8, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e16, m1, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e16, m2, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e16, m4, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e16, m8, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e32, m1, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e32, m2, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e32, m4, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e32, m8, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e64, m1, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e64, m2, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e64, m4, tu, mu
-vmv.v.x v8, x8
-vsetvli x28, x0, e64, m8, tu, mu
-vmv.v.x v8, x8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e8, m4, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e8, m8, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e16, mf2, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e16, mf4, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e16, m1, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e16, m2, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e16, m4, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e16, m8, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e32, mf2, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e32, m1, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e32, m2, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e32, m4, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e32, m8, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e64, m1, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e64, m2, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e64, m4, tu, mu
-vmv.v.i v8, 12
-vsetvli x28, x0, e64, m8, tu, mu
-vmv.v.i v8, 12
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmv.x.s x8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmv.x.s x8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e8, m1, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e8, m2, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e8, m4, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e8, m8, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e16, m1, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e16, m2, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e16, m4, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e16, m8, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e32, m1, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e32, m2, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e32, m4, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e32, m8, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e64, m1, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e64, m2, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e64, m4, tu, mu
-vmv.s.x v8, x8
-vsetvli x28, x0, e64, m8, tu, mu
-vmv.s.x v8, x8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmv1r.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmv1r.v v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmv2r.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmv2r.v v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmv4r.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmv4r.v v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmv8r.v v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmv8r.v v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e8, mf4, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e8, mf8, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e8, m1, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e8, m2, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e8, m4, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e8, m8, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e16, mf2, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e16, mf4, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e16, m1, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e16, m2, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e16, m4, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e16, m8, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e32, mf2, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e32, m1, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e32, m2, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e32, m4, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e32, m8, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e64, m1, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e64, m2, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e64, m4, tu, mu
-viota.m v8, v16
-vsetvli x28, x0, e64, m8, tu, mu
-viota.m v8, v16
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e8, m8, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e16, m8, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e32, m8, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e64, m1, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e64, m2, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e64, m4, tu, mu
-vcompress.vm v8, v16, v24
-vsetvli x28, x0, e64, m8, tu, mu
-vcompress.vm v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vslide1up.vx v8, v16, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vslide1up.vx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vslide1down.vx v8, v16, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vslide1down.vx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vslideup.vx v8, v16, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vslideup.vx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e8, m4, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e8, m8, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e16, mf2, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e16, mf4, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e16, m1, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e16, m2, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e16, m4, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e16, m8, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e32, mf2, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e32, m1, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e32, m2, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e32, m4, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e32, m8, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e64, m1, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e64, m2, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e64, m4, tu, mu
-vslideup.vi v8, v16, 12
-vsetvli x28, x0, e64, m8, tu, mu
-vslideup.vi v8, v16, 12
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vslidedown.vx v8, v16, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vslidedown.vx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e8, m4, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e8, m8, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e16, mf2, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e16, mf4, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e16, m1, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e16, m2, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e16, m4, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e16, m8, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e32, mf2, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e32, m1, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e32, m2, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e32, m4, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e32, m8, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e64, m1, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e64, m2, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e64, m4, tu, mu
-vslidedown.vi v8, v16, 12
-vsetvli x28, x0, e64, m8, tu, mu
-vslidedown.vi v8, v16, 12
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e8, m8, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e16, m8, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e32, m8, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e64, m1, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e64, m2, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e64, m4, tu, mu
-vrgather.vv v8, v16, v24
-vsetvli x28, x0, e64, m8, tu, mu
-vrgather.vv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vrgather.vx v8, v16, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vrgather.vx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e8, mf4, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e8, mf8, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e8, m1, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e8, m2, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e8, m4, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e8, m8, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e16, mf2, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e16, mf4, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e16, m1, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e16, m2, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e16, m4, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e16, m8, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e32, mf2, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e32, m1, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e32, m2, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e32, m4, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e32, m8, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e64, m1, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e64, m2, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e64, m4, tu, mu
-vrgather.vi v8, v16, 12
-vsetvli x28, x0, e64, m8, tu, mu
-vrgather.vi v8, v16, 12
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vrgatherei16.vv v8, v16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e16, m8, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e32, m8, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e64, m1, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e64, m2, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e64, m4, tu, mu
-vrgatherei16.vv v8, v16, v24
-vsetvli x28, x0, e64, m8, tu, mu
-vrgatherei16.vv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e8, mf4, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e8, mf8, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e8, m1, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e8, m2, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e8, m4, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e8, m8, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e16, mf2, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e16, mf4, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e16, m1, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e16, m2, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e16, m4, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e16, m8, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e32, mf2, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e32, m1, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e32, m2, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e32, m4, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e32, m8, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e64, m1, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e64, m2, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e64, m4, tu, mu
-vmerge.vim v8, v8, 12, v0
-vsetvli x28, x0, e64, m8, tu, mu
-vmerge.vim v8, v8, 12, v0
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e8, mf4, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e8, mf8, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e8, m1, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e8, m2, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e8, m4, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e8, m8, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e16, mf2, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e16, mf4, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e16, m1, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e16, m2, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e16, m4, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e16, m8, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e32, mf2, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e32, m1, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e32, m2, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e32, m4, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e32, m8, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e64, m1, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e64, m2, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e64, m4, tu, mu
-vmerge.vvm v8, v8, v8, v0
-vsetvli x28, x0, e64, m8, tu, mu
-vmerge.vvm v8, v8, v8, v0
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e8, mf4, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e8, mf8, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e8, m1, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e8, m2, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e8, m4, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e8, m8, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e16, mf2, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e16, mf4, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e16, m1, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e16, m2, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e16, m4, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e16, m8, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e32, mf2, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e32, m1, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e32, m2, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e32, m4, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e32, m8, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e64, m1, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e64, m2, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e64, m4, tu, mu
-vmerge.vxm v8, v8, x30, v0
-vsetvli x28, x0, e64, m8, tu, mu
-vmerge.vxm v8, v8, x30, v0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e16, mf4, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e16, m1, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e16, m2, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e16, m4, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e16, m8, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e32, mf2, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e32, m1, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e32, m2, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e32, m4, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e32, m8, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e64, m1, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e64, m2, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e64, m4, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-vsetvli x28, x0, e64, m8, tu, mu
-vfmerge.vfm v8, v8, ft0, v0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e16, m8, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e32, m8, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e64, m1, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e64, m2, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e64, m4, tu, mu
-vfslide1down.vf v8, v16, ft0
-vsetvli x28, x0, e64, m8, tu, mu
-vfslide1down.vf v8, v16, ft0
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e16, mf4, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e16, m1, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e16, m2, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e16, m4, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e16, m8, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e32, mf2, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e32, m1, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e32, m2, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e32, m4, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e32, m8, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e64, m1, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e64, m2, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e64, m4, tu, mu
-vfslide1up.vf v8, v16, ft0
-vsetvli x28, x0, e64, m8, tu, mu
-vfslide1up.vf v8, v16, ft0
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/permutation.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/reduction.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/reduction.test
index 621cad6e121ab..8eee50ff26c5d 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv-reduction.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/reduction.test
@@ -1,611 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Reduction operations
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vredand.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vredand.vs v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vredmaxu.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vredmaxu.vs v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vredmax.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vredmax.vs v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vredminu.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vredminu.vs v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vredmin.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vredmin.vs v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vredor.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vredor.vs v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vredsum.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vredsum.vs v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vredxor.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vredxor.vs v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e8, m8, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e16, m8, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwredsumu.vs v8, v16, v24
-vsetvli x28, x0, e32, m8, tu, mu
-vwredsumu.vs v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e8, m8, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e16, m8, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwredsum.vs v8, v16, v24
-vsetvli x28, x0, e32, m8, tu, mu
-vwredsum.vs v8, v16, v24
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfredmax.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfredmax.vs v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfredmin.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfredmin.vs v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfredosum.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfredosum.vs v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vfredusum.vs v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vfredusum.vs v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwredosum.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwredosum.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfwredosum.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfwredosum.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfwredosum.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfwredosum.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwredosum.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfwredosum.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfwredosum.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfwredosum.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfwredosum.vs v8, v8, v8
-
-vsetvli x28, x0, e16, mf2, tu, mu
-vfwredusum.vs v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vfwredusum.vs v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vfwredusum.vs v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vfwredusum.vs v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vfwredusum.vs v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vfwredusum.vs v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vfwredusum.vs v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vfwredusum.vs v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vfwredusum.vs v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vfwredusum.vs v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vfwredusum.vs v8, v8, v8
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/reduction.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vle-vse-vlm.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vle-vse-vlm.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vle-vse-vlm.test
index e68b13e47c6ac..32fdba1db7fc5 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vle-vse-vlm.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vle-vse-vlm.test
@@ -1,183 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vle8.v v8, (a0)
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, mf2, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m1, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m2, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m4, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m8, ta, ma
-vle16.v v8, (a0)
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m1, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m2, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m4, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m8, ta, ma
-vle32.v v8, (a0)
-
-vsetvli zero, zero, e64, m1, ta, ma
-vle64.v v8, (a0)
-vsetvli zero, zero, e64, m2, ta, ma
-vle64.v v8, (a0)
-vsetvli zero, zero, e64, m4, ta, ma
-vle64.v v8, (a0)
-vsetvli zero, zero, e64, m8, ta, ma
-vle64.v v8, (a0)
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vse8.v v8, (a0)
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, mf2, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m1, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m2, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m4, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m8, ta, ma
-vse16.v v8, (a0)
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m1, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m2, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m4, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m8, ta, ma
-vse32.v v8, (a0)
-
-vsetvli zero, zero, e64, m1, ta, ma
-vse64.v v8, (a0)
-vsetvli zero, zero, e64, m2, ta, ma
-vse64.v v8, (a0)
-vsetvli zero, zero, e64, m4, ta, ma
-vse64.v v8, (a0)
-vsetvli zero, zero, e64, m8, ta, ma
-vse64.v v8, (a0)
-
-# Unit-stride mask load/store
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vlm.v v8, (a0)
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vsm.v v8, (a0)
-
-# Fault-only-first
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vle8ff.v v8, (a0)
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, mf2, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m1, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m2, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m4, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m8, ta, ma
-vle16ff.v v8, (a0)
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m1, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m2, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m4, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m8, ta, ma
-vle32ff.v v8, (a0)
-
-vsetvli zero, zero, e64, m1, ta, ma
-vle64ff.v v8, (a0)
-vsetvli zero, zero, e64, m2, ta, ma
-vle64ff.v v8, (a0)
-vsetvli zero, zero, e64, m4, ta, ma
-vle64ff.v v8, (a0)
-vsetvli zero, zero, e64, m8, ta, ma
-vle64ff.v v8, (a0)
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vle-vse-vlm.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlse-vsse.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlse-vsse.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlse-vsse.test
index 8d97cd252abae..b9031c1d606af 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlse-vsse.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlse-vsse.test
@@ -1,101 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf4, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf2, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m1, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m2, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m4, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m8, ta, ma
-vlse8.v v8, (a0), t0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, mf2, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m1, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m2, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m4, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m8, ta, ma
-vlse16.v v8, (a0), t0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m1, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m2, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m4, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m8, ta, ma
-vlse32.v v8, (a0), t0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vlse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m2, ta, ma
-vlse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m4, ta, ma
-vlse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m8, ta, ma
-vlse64.v v8, (a0), t0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf4, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf2, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m1, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m2, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m4, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m8, ta, ma
-vsse8.v v8, (a0), t0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, mf2, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m1, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m2, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m4, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m8, ta, ma
-vsse16.v v8, (a0), t0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m1, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m2, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m4, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m8, ta, ma
-vsse32.v v8, (a0), t0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vsse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m2, ta, ma
-vsse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m4, ta, ma
-vsse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m8, ta, ma
-vsse64.v v8, (a0), t0
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlse-vsse.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlseg-vsseg.test
similarity index 89%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlseg-vsseg.test
index c660b94353be2..7d284a6f2e850 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlseg-vsseg.test
@@ -1,1608 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vlseg2e8.v v8,(a0)
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-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsuxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg3ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsuxseg3ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsuxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsuxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsuxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg4ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsuxseg4ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg5ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg6ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg7ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg8ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m4, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m4, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m4, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg2ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsoxseg2ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m4, tu, mu
-vsoxseg2ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsoxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg3ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsoxseg3ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsoxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg4ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsoxseg4ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg5ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg6ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg7ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg8ei64.v v8, (a0), v16
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlseg-vsseg.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlxe-vsxe.test
similarity index 89%
rename from llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlxe-vsxe.s
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlxe-vsxe.test
index ad7904c55c501..cd174baf5e6bb 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlxe-vsxe.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlxe-vsxe.test
@@ -1,197 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vluxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vluxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vluxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vluxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vluxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vluxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vluxei64.v v8, (a0), v0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vloxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vloxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vloxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vloxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vloxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vloxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vloxei64.v v8, (a0), v0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vsuxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vsuxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vsuxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vsuxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vsuxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vsuxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vsuxei64.v v8, (a0), v0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vsoxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vsoxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vsoxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vsoxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vsoxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vsoxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vsoxei64.v v8, (a0), v0
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlxe-vsxe.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zba.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zba.test
new file mode 100644
index 0000000000000..661ca893accd0
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zba.test
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/zba.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ADD_UW add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SLLI_UW slli.uw a0, a0, 1
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH1ADD_UW sh1add.uw a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH2ADD_UW sh2add.uw a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH3ADD_UW sh3add.uw a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH1ADD sh1add a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH2ADD sh2add a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU SH3ADD sh3add a0, a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 4.00 4.00 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 0.50 0.50 - - - - - add.uw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - slli.uw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - sh1add.uw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sh2add.uw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sh3add.uw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sh1add a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sh2add a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sh3add a0, a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbb.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbb.test
new file mode 100644
index 0000000000000..0cbc6b500b719
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbb.test
@@ -0,0 +1,90 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/zbb.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ANDN andn a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ORN orn a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU XNOR xnor a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CLZ clz a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CLZW clzw a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CTZ ctz a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CTZW ctzw a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CPOP cpop a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CPOPW cpopw a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MIN min a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MINU minu a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MAX max a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU MAXU maxu a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SEXT_B sext.b a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU SEXT_H sext.h a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ZEXT_H_RV64 zext.h a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ROL rol a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ROLW rolw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ROR ror a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU RORW rorw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU RORI rori a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU RORIW roriw a0, a0, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU ORC_B orc.b a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU REV8_RV64 rev8 a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 12.00 12.00 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 0.50 0.50 - - - - - andn a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - orn a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - xnor a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - clz a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - clzw a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - ctz a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - ctzw a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - cpop a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - cpopw a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - min a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - minu a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - max a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - maxu a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sext.b a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - sext.h a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - zext.h a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - rol a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - rolw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - ror a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - rorw a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - rori a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - roriw a0, a0, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - orc.b a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - rev8 a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbc.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbc.test
new file mode 100644
index 0000000000000..2ef7a95e0a917
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbc.test
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/zbc.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CLMUL clmul a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CLMULR clmulr a0, a0, a0
+# CHECK-NEXT: 1 2 0.50 2 SMX60_IEU CLMULH clmulh a0, a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 1.50 1.50 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 0.50 0.50 - - - - - clmul a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - clmulr a0, a0, a0
+# CHECK-NEXT: - 0.50 0.50 - - - - - clmulh a0, a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbs.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbs.test
new file mode 100644
index 0000000000000..eba51f0cfffe2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbs.test
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/zbs.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BCLR bclr a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BCLRI bclri a0, a1, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BEXT bext a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BEXTI bexti a0, a1, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BINV binv a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BINVI binvi a0, a1, 1
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BSET bset a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU BSETI bseti a0, a1, 1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 4.00 4.00 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 0.50 0.50 - - - - - bclr a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - - - - bclri a0, a1, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - bext a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - - - - bexti a0, a1, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - binv a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - - - - binvi a0, a1, 1
+# CHECK-NEXT: - 0.50 0.50 - - - - - bset a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - - - - bseti a0, a1, 1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zfh.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zfh.test
new file mode 100644
index 0000000000000..ebd21d677ebc0
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zfh.test
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/zfh.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FADD_H fadd.h fs10, fs11, ft8
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FSUB_H fsub.h ft9, ft10, ft11
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMUL_H fmul.h ft0, ft1, ft2
+# CHECK-NEXT: 1 12 12.00 12 SMX60_FP[12] FDIV_H fdiv.h ft3, ft4, ft5
+# CHECK-NEXT: 1 12 12.00 12 SMX60_FP[12] FSQRT_H fsqrt.h ft6, ft7
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMIN_H fmin.h fa5, fa6, fa7
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMAX_H fmax.h fs2, fs3, fs4
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FMADD_H fmadd.h fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FMSUB_H fmsub.h fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FNMSUB_H fnmsub.h fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 5 1.00 5 SMX60_FP FNMADD_H fnmadd.h fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FEQ_H feq.h a1, fs8, fs9
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLT_H flt.h a2, fs10, fs11
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FLE_H fle.h a3, ft8, ft9
+# CHECK-NEXT: 1 6 1.00 6 SMX60_FP FCLASS_H fclass.h a3, ft10
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: 37.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1.00 - - - - - - - fadd.h fs10, fs11, ft8
+# CHECK-NEXT: 1.00 - - - - - - - fsub.h ft9, ft10, ft11
+# CHECK-NEXT: 1.00 - - - - - - - fmul.h ft0, ft1, ft2
+# CHECK-NEXT: 12.00 - - - - - - - fdiv.h ft3, ft4, ft5
+# CHECK-NEXT: 12.00 - - - - - - - fsqrt.h ft6, ft7
+# CHECK-NEXT: 1.00 - - - - - - - fmin.h fa5, fa6, fa7
+# CHECK-NEXT: 1.00 - - - - - - - fmax.h fs2, fs3, fs4
+# CHECK-NEXT: 1.00 - - - - - - - fmadd.h fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1.00 - - - - - - - fmsub.h fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1.00 - - - - - - - fnmsub.h fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1.00 - - - - - - - fnmadd.h fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1.00 - - - - - - - feq.h a1, fs8, fs9
+# CHECK-NEXT: 1.00 - - - - - - - flt.h a2, fs10, fs11
+# CHECK-NEXT: 1.00 - - - - - - - fle.h a3, ft8, ft9
+# CHECK-NEXT: 1.00 - - - - - - - fclass.h a3, ft10
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zfhmin.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zfhmin.test
new file mode 100644
index 0000000000000..f8c0f156a2415
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zfhmin.test
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/zfhmin.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FLH flh ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FSH fsh ft0, 0(a0)
+# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU FMV_X_H fmv.x.h a2, fs7
+# CHECK-NEXT: 1 4 0.50 4 SMX60_IEU FMV_H_X fmv.h.x ft1, a6
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_S_H fcvt.s.h fa0, ft0
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_S_H fcvt.s.h fa0, ft0, rup
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_H_S fcvt.h.s ft2, fa2
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_D_H fcvt.d.h fa0, ft0
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_D_H fcvt.d.h fa0, ft0, rup
+# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FCVT_H_D fcvt.h.d ft2, fa2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: 6.00 1.00 1.00 1.00 1.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - - - 0.50 0.50 - - - flh ft0, 0(a0)
+# CHECK-NEXT: - - - 0.50 0.50 - - - fsh ft0, 0(a0)
+# CHECK-NEXT: - 0.50 0.50 - - - - - fmv.x.h a2, fs7
+# CHECK-NEXT: - 0.50 0.50 - - - - - fmv.h.x ft1, a6
+# CHECK-NEXT: 1.00 - - - - - - - fcvt.s.h fa0, ft0
+# CHECK-NEXT: 1.00 - - - - - - - fcvt.s.h fa0, ft0, rup
+# CHECK-NEXT: 1.00 - - - - - - - fcvt.h.s ft2, fa2
+# CHECK-NEXT: 1.00 - - - - - - - fcvt.d.h fa0, ft0
+# CHECK-NEXT: 1.00 - - - - - - - fcvt.d.h fa0, ft0, rup
+# CHECK-NEXT: 1.00 - - - - - - - fcvt.h.d ft2, fa2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zicond.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zicond.test
new file mode 100644
index 0000000000000..f6b7a36005e26
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zicond.test
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../Inputs/zicond.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_EQZ czero.eqz a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_NEZ czero.nez a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_EQZ czero.eqz a0, a1, a2
+# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU CZERO_NEZ czero.nez a0, a1, a2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 2.00 2.00 - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 0.50 0.50 - - - - - czero.eqz a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - - - - czero.nez a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - - - - czero.eqz a0, a1, a2
+# CHECK-NEXT: - 0.50 0.50 - - - - - czero.nez a0, a1, a2
>From bec9e68327c0eb26d740f0502dd9ca97a16cc320 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Mon, 29 Dec 2025 14:15:21 -0800
Subject: [PATCH 2/2] fixup! [RISCV][MCA] Share input files among SchedModel
tests of different processors
---
.../tools/llvm-mca/RISCV/Inputs/rvv/mul-div.s | 997 ++++++++
.../RISCV/SiFiveP400/rvv/mul-div.test | 1997 +++++++++++++++++
.../rvv/mul => SpacemitX60/rvv/mul-div.test} | 1000 +--------
3 files changed, 2995 insertions(+), 999 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mul-div.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/mul-div.test
rename llvm/test/tools/llvm-mca/RISCV/{Inputs/rvv/mul => SpacemitX60/rvv/mul-div.test} (90%)
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mul-div.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mul-div.s
new file mode 100644
index 0000000000000..5f2fd6a3ff3cb
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mul-div.s
@@ -0,0 +1,997 @@
+# Multiplication and division operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmul.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmul.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vdiv.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vdiv.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vdiv.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
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+vsetvli x28, x0, e32, mf2, tu, mu
+vmulhu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmulhu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmulhu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmulhu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmulhu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmulhu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmulhu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmulhu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmulhu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vmulhsu.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vmulhsu.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vmulhsu.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vmulhsu.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmul.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmul.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwmul.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwmul.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulu.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulu.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulsu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulsu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vwmulsu.vx v8, v16, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vwmulsu.vx v8, v16, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vsmul.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vsmul.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vsmul.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vsmul.vx v8, v8, x30
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/mul-div.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/mul-div.test
new file mode 100644
index 0000000000000..fbeb90a911f7f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/mul-div.test
@@ -0,0 +1,1997 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mul-div.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div:1
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0:1
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv:1
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0:1
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1:1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2:1
+# CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2
+# CHECK-NEXT: [7] - SiFiveP400Load:1
+# CHECK-NEXT: [8] - SiFiveP400Store:1
+# CHECK-NEXT: [9] - SiFiveP400VDiv:1
+# CHECK-NEXT: [10] - SiFiveP400VEXQ0:1
+# CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1
+# CHECK-NEXT: [12] - SiFiveP400VLD:1
+# CHECK-NEXT: [13] - SiFiveP400VST:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP400VDiv[102],SiFiveP400VEXQ0[2] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP400VDiv[204],SiFiveP400VEXQ0[4] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP400VDiv[408],SiFiveP400VEXQ0[8] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP400VDiv[90],SiFiveP400VEXQ0[2] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP400VDiv[180],SiFiveP400VEXQ0[4] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP400VDiv[360],SiFiveP400VEXQ0[8] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP400VDiv[84],SiFiveP400VEXQ0[2] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP400VDiv[168],SiFiveP400VEXQ0[4] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP400VDiv[336],SiFiveP400VEXQ0[8] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP400VDiv[72],SiFiveP400VEXQ0 VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP400VDiv[144],SiFiveP400VEXQ0[2] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP400VDiv[288],SiFiveP400VEXQ0[4] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP400VDiv[576],SiFiveP400VEXQ0[8] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP400VDiv[102],SiFiveP400VEXQ0[2] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP400VDiv[204],SiFiveP400VEXQ0[4] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP400VDiv[408],SiFiveP400VEXQ0[8] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP400VDiv[90],SiFiveP400VEXQ0[2] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP400VDiv[180],SiFiveP400VEXQ0[4] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP400VDiv[360],SiFiveP400VEXQ0[8] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP400VDiv[84],SiFiveP400VEXQ0[2] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP400VDiv[168],SiFiveP400VEXQ0[4] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP400VDiv[336],SiFiveP400VEXQ0[8] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP400VDiv[72],SiFiveP400VEXQ0 VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP400VDiv[144],SiFiveP400VEXQ0[2] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP400VDiv[288],SiFiveP400VEXQ0[4] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP400VDiv[576],SiFiveP400VEXQ0[8] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP400VDiv[102],SiFiveP400VEXQ0[2] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP400VDiv[204],SiFiveP400VEXQ0[4] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP400VDiv[408],SiFiveP400VEXQ0[8] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP400VDiv[90],SiFiveP400VEXQ0[2] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP400VDiv[180],SiFiveP400VEXQ0[4] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP400VDiv[360],SiFiveP400VEXQ0[8] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP400VDiv[84],SiFiveP400VEXQ0[2] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP400VDiv[168],SiFiveP400VEXQ0[4] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP400VDiv[336],SiFiveP400VEXQ0[8] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP400VDiv[72],SiFiveP400VEXQ0 VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP400VDiv[144],SiFiveP400VEXQ0[2] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP400VDiv[288],SiFiveP400VEXQ0[4] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP400VDiv[576],SiFiveP400VEXQ0[8] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP400VDiv[102],SiFiveP400VEXQ0[2] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP400VDiv[204],SiFiveP400VEXQ0[4] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP400VDiv[408],SiFiveP400VEXQ0[8] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP400VDiv[90],SiFiveP400VEXQ0[2] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP400VDiv[180],SiFiveP400VEXQ0[4] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP400VDiv[360],SiFiveP400VEXQ0[8] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP400VDiv[84],SiFiveP400VEXQ0[2] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP400VDiv[168],SiFiveP400VEXQ0[4] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP400VDiv[336],SiFiveP400VEXQ0[8] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP400VDiv[72],SiFiveP400VEXQ0 VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP400VDiv[144],SiFiveP400VEXQ0[2] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP400VDiv[288],SiFiveP400VEXQ0[4] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP400VDiv[576],SiFiveP400VEXQ0[8] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP400VDiv[102],SiFiveP400VEXQ0[2] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP400VDiv[204],SiFiveP400VEXQ0[4] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP400VDiv[408],SiFiveP400VEXQ0[8] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP400VDiv[90],SiFiveP400VEXQ0[2] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP400VDiv[180],SiFiveP400VEXQ0[4] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP400VDiv[360],SiFiveP400VEXQ0[8] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP400VDiv[84],SiFiveP400VEXQ0[2] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP400VDiv[168],SiFiveP400VEXQ0[4] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP400VDiv[336],SiFiveP400VEXQ0[8] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP400VDiv[72],SiFiveP400VEXQ0 VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP400VDiv[144],SiFiveP400VEXQ0[2] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP400VDiv[288],SiFiveP400VEXQ0[4] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP400VDiv[576],SiFiveP400VEXQ0[8] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP400VDiv[102],SiFiveP400VEXQ0[2] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP400VDiv[204],SiFiveP400VEXQ0[4] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP400VDiv[408],SiFiveP400VEXQ0[8] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP400VDiv[90],SiFiveP400VEXQ0[2] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP400VDiv[180],SiFiveP400VEXQ0[4] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP400VDiv[360],SiFiveP400VEXQ0[8] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP400VDiv[84],SiFiveP400VEXQ0[2] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP400VDiv[168],SiFiveP400VEXQ0[4] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP400VDiv[336],SiFiveP400VEXQ0[8] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP400VDiv[72],SiFiveP400VEXQ0 VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP400VDiv[144],SiFiveP400VEXQ0[2] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP400VDiv[288],SiFiveP400VEXQ0[4] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP400VDiv[576],SiFiveP400VEXQ0[8] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP400VDiv[102],SiFiveP400VEXQ0[2] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP400VDiv[204],SiFiveP400VEXQ0[4] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP400VDiv[408],SiFiveP400VEXQ0[8] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP400VDiv[90],SiFiveP400VEXQ0[2] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP400VDiv[180],SiFiveP400VEXQ0[4] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP400VDiv[360],SiFiveP400VEXQ0[8] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP400VDiv[84],SiFiveP400VEXQ0[2] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP400VDiv[168],SiFiveP400VEXQ0[4] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP400VDiv[336],SiFiveP400VEXQ0[8] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP400VDiv[72],SiFiveP400VEXQ0 VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP400VDiv[144],SiFiveP400VEXQ0[2] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP400VDiv[288],SiFiveP400VEXQ0[4] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP400VDiv[576],SiFiveP400VEXQ0[8] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP400VDiv[51],SiFiveP400VEXQ0 VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP400VDiv[102],SiFiveP400VEXQ0[2] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP400VDiv[204],SiFiveP400VEXQ0[4] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP400VDiv[408],SiFiveP400VEXQ0[8] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP400VDiv[45],SiFiveP400VEXQ0 VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP400VDiv[90],SiFiveP400VEXQ0[2] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP400VDiv[180],SiFiveP400VEXQ0[4] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP400VDiv[360],SiFiveP400VEXQ0[8] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP400VDiv[42],SiFiveP400VEXQ0 VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP400VDiv[84],SiFiveP400VEXQ0[2] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP400VDiv[168],SiFiveP400VEXQ0[4] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP400VDiv[336],SiFiveP400VEXQ0[8] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP400VDiv[72],SiFiveP400VEXQ0 VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP400VDiv[144],SiFiveP400VEXQ0[2] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP400VDiv[288],SiFiveP400VEXQ0[4] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP400VDiv[576],SiFiveP400VEXQ0[8] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 9 8.00 9 SiFiveP400VEXQ0[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP400VEXQ0 VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP400VEXQ0[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP400VEXQ0[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP400VEXQ0[8] VSMUL_VX vsmul.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 486.00 - - - 27480.00 1350.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsmul.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mul b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/mul-div.test
similarity index 90%
rename from llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mul
rename to llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/mul-div.test
index 3350eedc89a09..461b927f62e68 100644
--- a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mul
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/mul-div.test
@@ -1,1003 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full < %s | FileCheck %s
-
-# Multiplication and division operations
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmul.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmul.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vmul.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vmul.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vdiv.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vdiv.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vdiv.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vdiv.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vdiv.vx v8, v8, x30
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-vsetvli x28, x0, e64, m4, tu, mu
-vmulhu.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmulhu.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vmulhu.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vmulhu.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vmulhsu.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vmulhsu.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vmulhsu.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vmulhsu.vx v8, v8, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwmul.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwmul.vv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vwmul.vx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vwmul.vx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwmulu.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwmulu.vv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vwmulu.vx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vwmulu.vx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e8, m1, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e8, m2, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e8, m4, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e16, m1, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e16, m2, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e16, m4, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e32, m1, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e32, m2, tu, mu
-vwmulsu.vv v8, v16, v24
-vsetvli x28, x0, e32, m4, tu, mu
-vwmulsu.vv v8, v16, v24
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vwmulsu.vx v8, v16, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vwmulsu.vx v8, v16, x30
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e8, mf4, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e8, mf8, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e8, m1, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e8, m2, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e8, m4, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e8, m8, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e16, mf2, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e16, mf4, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e16, m1, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e16, m2, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e16, m4, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e16, m8, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e32, mf2, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e32, m1, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e32, m2, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e32, m4, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e32, m8, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e64, m1, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e64, m2, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e64, m4, tu, mu
-vsmul.vv v8, v8, v8
-vsetvli x28, x0, e64, m8, tu, mu
-vsmul.vv v8, v8, v8
-
-vsetvli x28, x0, e8, mf2, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e8, mf4, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e8, mf8, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e8, m1, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e8, m2, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e8, m4, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e8, m8, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e16, mf2, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e16, mf4, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e16, m1, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e16, m2, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e16, m4, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e16, m8, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e32, mf2, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e32, m1, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e32, m2, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e32, m4, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e32, m8, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e64, m1, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e64, m2, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e64, m4, tu, mu
-vsmul.vx v8, v8, x30
-vsetvli x28, x0, e64, m8, tu, mu
-vsmul.vx v8, v8, x30
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x60 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mul-div.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP:1
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