[llvm] [RISCV][MCA] Consolidate inputs for different SchedModel tests (PR #173926)

Mon Dec 29 14:09:25 PST 2025

llvmbot wrote:




@llvm/pr-subscribers-backend-risc-v

Author: Min-Yih Hsu (mshockwave)

<details>
<summary>Changes</summary>

For a long time, we have been copying existing llvm-mca test files as a mean to test new scheduling model changes. This approach doesn't scale well primarily because we eventually have too many duplicated input assembly lines spread across multiple files. Also, the files you copied from might not have the best coverage. 

To address this issue, I propose to consolidate the inputs for all RISC-V scheduling model tests into a single place. More specifically, all assembly input code will now be put in `test/tools/llvm-mca/RISCV/Inputs`. Take `test/tools/llvm-mca/RISCV/Inputs/zba.s` as an example, it contains -- and only contains -- Zba instructions. To use it as an input to test `sifive-p470`'s scheduling model, we only need to create a `test/tools/llvm-mca/RISCV/SiFiveP400/zba.test` with the following `RUN` line:
```
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../Inputs/zba.s | FileCheck %s
```
Before auto-generating its contents with the UTC script. The files in `test/tools/llvm-mca/RISCV/Inputs` are roughly organized by extensions, so scheduling models can take only the extensions they support. 

This PR is a demonstration of such idea that applies it onto SiFiveP400 and SpacemitX60. If everyone thinks it's a good idea, we can do it to more scheduling models.

------

I actually have a python script to create `*.test` files from their corresponding `*.s` files in `Inputs`. Though arguably it's not really hard to do it manually, I can also upstream it if folks find it potentially useful.

---

Patch is 5.09 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/173926.diff


95 Files Affected:

- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/atomic.s (+99) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/floating-point.s (+90) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/integer.s (+81) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/mul-div.s (+13) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/arithmetic.s (+2297) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/bitwise.s (+1453) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/comparison.s (+901) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/conversion.s (+591) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/fma.s (+731) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/fp.s (+1897) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mask.s (+618) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/minmax.s (+362) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/mul () 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/permutation.s (+1174) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/reduction.s (+605) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vle-vse-vlm.s (+178) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlse-vsse.s (+96) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlseg-vsseg.s (+1603) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/vlxe-vsxe.s (+191) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/zvbc.s (+25) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/zba.s (+9) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/zbb.s (+32) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/zbc.s (+4) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/zbs.s (+9) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/zfh.s (+21) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/zfhmin.s (+18) 
- (added) llvm/test/tools/llvm-mca/RISCV/Inputs/zicond.s (+5) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/atomic.test (+229) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s (-1009) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/floating-point.test (+173) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/integer.test (+165) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s (-61) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s (-60) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-div.test (+79) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/arithmetic.test (+4533) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/bitwise.test (+2885) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/comparison.test (+1813) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/conversion.test (+1177) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/fma.test (+1465) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/fp.test (+3713) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/mask.test (+1257) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/minmax.test (+757) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/permutation.test (+2341) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/reduction.test (+1229) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vle-vse-vlm.test (+373) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlse-vsse.test (+229) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlseg-vsseg.test (+3133) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/vlxe-vsxe.test (+405) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvbb.s () 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvbc.test (+93) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvkg.s () 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvkned.s () 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvknhb.s () 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvksed.s () 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/rvv/zvksh.s () 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s (-108) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s (-542) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s (-316) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s (-4727) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s (-588) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s (-895) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vreduce.s (-438) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vrgather.s (-86) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vshift-vmul.s (-132) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zba.test (+69) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zbb.test (+101) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zbs.test (+69) 
- (added) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zfhmin.test (+73) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbc.s (-112) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.test (+1-101) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.test (+2-180) 
- (removed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s (-437) 
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.test (+154) 
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/mul-div.test (+68) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/arithmetic.test (+1-2299) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/bitwise.test (+1-1455) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/comparison.test (+1-903) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/conversion.test (+1-592) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test (+1-732) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test (+1-1898) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/mask.test (+1-619) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/minmax.test (+1-363) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/permutation.test (+1-1175) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/reduction.test (+1-607) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vle-vse-vlm.test (+1-179) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlse-vsse.test (+1-97) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlseg-vsseg.test (+1-1604) 
- (renamed) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/vlxe-vsxe.test (+1-193) 
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zba.test (+58) 
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbb.test (+90) 
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbc.test (+48) 
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zbs.test (+58) 
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zfh.test (+72) 
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zfhmin.test (+62) 
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX60/zicond.test (+50) 


``````````diff

diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/atomic.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/atomic.s
new file mode 100644
index 0000000000000..bd61a6d64445a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/atomic.s
@@ -0,0 +1,99 @@
+# Zalrsc
+lr.w t0, (t1)
+lr.w.aq t1, (t2)
+lr.w.rl t2, (t3)
+lr.w.aqrl t3, (t4)
+sc.w t6, t5, (t4)
+sc.w.aq t5, t4, (t3)
+sc.w.rl t4, t3, (t2)
+sc.w.aqrl t3, t2, (t1)
+
+lr.d t0, (t1)
+lr.d.aq t1, (t2)
+lr.d.rl t2, (t3)
+lr.d.aqrl t3, (t4)
+sc.d t6, t5, (t4)
+sc.d.aq t5, t4, (t3)
+sc.d.rl t4, t3, (t2)
+sc.d.aqrl t3, t2, (t1)
+
+# Zaamo
+amoswap.w a4, ra, (s0)
+amoadd.w a1, a2, (a3)
+amoxor.w a2, a3, (a4)
+amoand.w a3, a4, (a5)
+amoor.w a4, a5, (a6)
+amomin.w a5, a6, (a7)
+amomax.w s7, s6, (s5)
+amominu.w s6, s5, (s4)
+amomaxu.w s5, s4, (s3)
+
+amoswap.w.aq a4, ra, (s0)
+amoadd.w.aq a1, a2, (a3)
+amoxor.w.aq a2, a3, (a4)
+amoand.w.aq a3, a4, (a5)
+amoor.w.aq a4, a5, (a6)
+amomin.w.aq a5, a6, (a7)
+amomax.w.aq s7, s6, (s5)
+amominu.w.aq s6, s5, (s4)
+amomaxu.w.aq s5, s4, (s3)
+
+amoswap.w.rl a4, ra, (s0)
+amoadd.w.rl a1, a2, (a3)
+amoxor.w.rl a2, a3, (a4)
+amoand.w.rl a3, a4, (a5)
+amoor.w.rl a4, a5, (a6)
+amomin.w.rl a5, a6, (a7)
+amomax.w.rl s7, s6, (s5)
+amominu.w.rl s6, s5, (s4)
+amomaxu.w.rl s5, s4, (s3)
+
+amoswap.w.aqrl a4, ra, (s0)
+amoadd.w.aqrl a1, a2, (a3)
+amoxor.w.aqrl a2, a3, (a4)
+amoand.w.aqrl a3, a4, (a5)
+amoor.w.aqrl a4, a5, (a6)
+amomin.w.aqrl a5, a6, (a7)
+amomax.w.aqrl s7, s6, (s5)
+amominu.w.aqrl s6, s5, (s4)
+amomaxu.w.aqrl s5, s4, (s3)
+
+amoswap.d a4, ra, (s0)
+amoadd.d a1, a2, (a3)
+amoxor.d a2, a3, (a4)
+amoand.d a3, a4, (a5)
+amoor.d a4, a5, (a6)
+amomin.d a5, a6, (a7)
+amomax.d s7, s6, (s5)
+amominu.d s6, s5, (s4)
+amomaxu.d s5, s4, (s3)
+
+amoswap.d.aq a4, ra, (s0)
+amoadd.d.aq a1, a2, (a3)
+amoxor.d.aq a2, a3, (a4)
+amoand.d.aq a3, a4, (a5)
+amoor.d.aq a4, a5, (a6)
+amomin.d.aq a5, a6, (a7)
+amomax.d.aq s7, s6, (s5)
+amominu.d.aq s6, s5, (s4)
+amomaxu.d.aq s5, s4, (s3)
+
+amoswap.d.rl a4, ra, (s0)
+amoadd.d.rl a1, a2, (a3)
+amoxor.d.rl a2, a3, (a4)
+amoand.d.rl a3, a4, (a5)
+amoor.d.rl a4, a5, (a6)
+amomin.d.rl a5, a6, (a7)
+amomax.d.rl s7, s6, (s5)
+amominu.d.rl s6, s5, (s4)
+amomaxu.d.rl s5, s4, (s3)
+
+amoswap.d.aqrl a4, ra, (s0)
+amoadd.d.aqrl a1, a2, (a3)
+amoxor.d.aqrl a2, a3, (a4)
+amoand.d.aqrl a3, a4, (a5)
+amoor.d.aqrl a4, a5, (a6)
+amomin.d.aqrl a5, a6, (a7)
+amomax.d.aqrl s7, s6, (s5)
+amominu.d.aqrl s6, s5, (s4)
+amomaxu.d.aqrl s5, s4, (s3)
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/floating-point.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/floating-point.s
new file mode 100644
index 0000000000000..ca3cd3ade5bba
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/floating-point.s
@@ -0,0 +1,90 @@
+# Floating-Point Load and Store Instructions
+## Single-Precision
+flw ft0, 0(a0)
+fsw ft0, 0(a0)
+
+## Double-Precision
+fld ft0, 0(a0)
+fsd ft0, 0(a0)
+
+# Floating-Point Computational Instructions
+## Single-Precision
+fadd.s f26, f27, f28
+fsub.s f29, f30, f31
+fmul.s ft0, ft1, ft2
+fdiv.s ft3, ft4, ft5
+fsqrt.s ft6, ft7
+fmin.s fa5, fa6, fa7
+fmax.s fs2, fs3, fs4
+fmadd.s f10, f11, f12, f31
+fmsub.s f14, f15, f16, f17
+fnmsub.s f18, f19, f20, f21
+fnmadd.s f22, f23, f24, f25
+
+## Double-Precision
+fadd.d f26, f27, f28
+fsub.d f29, f30, f31
+fmul.d ft0, ft1, ft2
+fdiv.d ft3, ft4, ft5
+fsqrt.d ft6, ft7
+fmin.d fa5, fa6, fa7
+fmax.d fs2, fs3, fs4
+fmadd.d f10, f11, f12, f31
+fmsub.d f14, f15, f16, f17
+fnmsub.d f18, f19, f20, f21
+fnmadd.d f22, f23, f24, f25
+
+# Floating-Point Conversion and Move Instructions
+## Single-Precision
+fcvt.w.s a0, fs5
+fcvt.wu.s a1, fs6
+fcvt.s.w ft11, a4
+fcvt.s.wu ft0, a5
+
+fcvt.l.s a0, ft0
+fcvt.lu.s a1, ft1
+fcvt.s.l ft2, a2
+fcvt.s.lu ft3, a3
+
+fmv.x.w a2, fs7
+fmv.w.x ft1, a6
+
+fsgnj.s fs1, fa0, fa1
+fsgnjn.s fa1, fa3, fa4
+
+## Double-Precision
+fcvt.wu.d a4, ft11
+fcvt.w.d a4, ft11
+fcvt.d.w ft0, a5
+fcvt.d.wu ft1, a6
+
+fcvt.s.d fs5, fs6
+fcvt.d.s fs7, fs8
+
+fcvt.l.d a0, ft0
+fcvt.lu.d a1, ft1
+fcvt.d.l ft3, a3
+fcvt.d.lu ft4, a4
+
+fmv.x.d a2, ft2
+fmv.d.x ft5, a5
+
+fsgnj.d fs1, fa0, fa1
+fsgnjn.d fa1, fa3, fa4
+
+# Floating-Point Compare Instructions
+## Single-Precision
+feq.s a1, fs8, fs9
+flt.s a2, fs10, fs11
+fle.s a3, ft8, ft9
+
+## Double-Precision
+feq.d a1, fs8, fs9
+flt.d a2, fs10, fs11
+fle.d a3, ft8, ft9
+
+# Floating-Point Classify Instruction
+## Single-Precision
+fclass.s a3, ft10
+## Double-Precision
+fclass.d a3, ft10
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/integer.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/integer.s
new file mode 100644
index 0000000000000..5f20853ec01bf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/integer.s
@@ -0,0 +1,81 @@
+# Integer Register-Immediate Instructions
+addi a0, a0, 1
+addiw a0, a0, 1
+slti a0, a0, 1
+sltiu a0, a0, 1
+
+andi a0, a0, 1
+ori a0, a0, 1
+xori a0, a0, 1
+
+slli a0, a0, 1
+srli a0, a0, 1
+srai a0, a0, 1
+slliw a0, a0, 1
+srliw a0, a0, 1
+sraiw a0, a0, 1
+
+lui a0, 1
+auipc a1, 1
+
+# Integer Register-Register Operations
+add a0, a0, a1
+addw a0, a0, a0
+slt a0, a0, a0
+sltu a0, a0, a0
+
+and a0, a0, a0
+or a0, a0, a0
+xor a0, a0, a0
+
+sll a0, a0, a0
+srl a0, a0, a0
+sra a0, a0, a0
+sllw a0, a0, a0
+srlw a0, a0, a0
+sraw a0, a0, a0
+
+sub a0, a0, a0
+subw a0, a0, a0
+
+# Control Transfer Instructions
+
+## Unconditional Jumps
+jal a0, 1f
+1:
+jalr a0
+beq a0, a0, 1f
+1:
+bne a0, a0, 1f
+1:
+blt a0, a0, 1f
+1:
+bltu a0, a0, 1f
+1:
+bge a0, a0, 1f
+1:
+bgeu a0, a0, 1f
+1:
+add a0, a0, a0
+
+# Load and Store Instructions
+lb t0, 0(a0)
+lbu t0, 0(a0)
+lh t0, 0(a0)
+lhu t0, 0(a0)
+lw t0, 0(a0)
+lwu t0, 0(a0)
+ld t0, 0(a0)
+
+sb t0, 0(a0)
+sh t0, 0(a0)
+sw t0, 0(a0)
+sd t0, 0(a0)
+
+# Zicsr
+csrrw t0, 0xfff, t1
+csrrs s3, 0x001, s5
+csrrc sp, 0x000, ra
+csrrwi a5, 0x000, 0
+csrrsi t2, 0xfff, 31
+csrrci t1, 0x140, 5
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/mul-div.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/mul-div.s
new file mode 100644
index 0000000000000..4221f74898f94
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/mul-div.s
@@ -0,0 +1,13 @@
+mul a0, a0, a0
+mulh a0, a0, a0
+mulhu a0, a0, a0
+mulhsu a0, a0, a0
+mulw a0, a0, a0
+div a0, a1, a2
+divu a0, a1, a2
+rem a0, a1, a2
+remu a0, a1, a2
+divw a0, a1, a2
+divuw a0, a1, a2
+remw a0, a1, a2
+remuw a0, a1, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/arithmetic.s
new file mode 100644
index 0000000000000..66dea1770efe9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/Inputs/rvv/arithmetic.s
@@ -0,0 +1,2297 @@
+# Basic arithmetic operations
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vi v8, v8, 12
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vi v8, v8, 12
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vadd.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vadd.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, mf8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e8, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, mf4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e16, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, mf2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e32, m8, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m1, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m2, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m4, tu, mu
+vsub.vv v8, v8, v8
+vsetvli x28, x0, e64, m8, tu, mu
+vsub.vv v8, v8, v8
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e8, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e16, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, mf2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e32, m8, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m1, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m2, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m4, tu, mu
+vsub.vx v8, v8, x30
+vsetvli x28, x0, e64, m8, tu, mu
+vsub.vx v8, v8, x30
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vadc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vadc.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vadc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vadc.vxm v8, v8, x30, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vadc.vim v8, v8, 12, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vadc.vim v8, v8, 12, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vsbc.vvm v8, v8, v8, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vsbc.vvm v8, v8, v8, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf4, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, mf8, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m1, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m2, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m4, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e8, m8, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf2, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, mf4, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m1, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m2, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m4, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e16, m8, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, mf2, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m1, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m2, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m4, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e32, m8, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m1, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m2, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m4, tu, mu
+vsbc.vxm v8, v8, x30, v0
+vsetvli x28, x0, e64, m8, tu, mu
+vsbc.vxm v8, v8, x30, v0
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf4, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e8, mf8, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e8, m1, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e8, m2, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e8, m4, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf2, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e16, mf4, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e16, m1, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e16, m2, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e16, m4, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e32, mf2, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e32, m1, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e32, m2, tu, mu
+vwaddu.vv v8, v16, v24
+vsetvli x28, x0, e32, m4, tu, mu
+vwaddu.vv v8, v16, v24
+
+vsetvli x28, x0, e8, mf2, tu, mu
+vwaddu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf4, tu, mu
+vwaddu.vx v8, v16, x30
+vsetvli x28, x0, e8, mf8, tu, mu
+vwaddu.vx v8, v16, x30
+vsetvli x28, x0, e8, m1, tu, mu
+vwaddu.vx v8, v16, x30
+vsetvli x28, x0, e8, m2, tu, mu
+vwaddu.vx v8, v16, x30
+vsetvli x28, x0, e8, m4, tu, mu
+vwaddu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf2, tu, mu
+vwaddu.vx v8, v16, x30
+vsetvli x28, x0, e16, mf4, tu, mu
+vwaddu.vx v8, v...
[truncated]

``````````

</details>


https://github.com/llvm/llvm-project/pull/173926
