[llvm] [RISCV][SelectionDAG] Add a ISD::CTLS node for count leading redundant sign bits. Use it to select CLS(W). (PR #173417)

[Craig Topper via llvm-commits]

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@@ -11811,6 +11813,27 @@ SDValue DAGCombiner::visitBITREVERSE(SDNode *N) {
   return SDValue();
 }
 
+// Fold (ctlz (xor x, (sra x, bitwidth-1))) -> (add (ctls x), 1).
+SDValue DAGCombiner::foldCTLZToCTLS(SDValue Src, const SDLoc &DL) {
+  EVT VT = Src.getValueType();
+
+  auto LK = TLI.getTypeConversion(*DAG.getContext(), VT);
+  if (!(LK.first == TargetLoweringBase::TypeLegal ||
+        LK.first == TargetLoweringBase::TypePromoteInteger) ||
+      !TLI.isOperationLegalOrCustom(ISD::CTLS, LK.second))
+    return SDValue();
+
+  unsigned BitWidth = VT.getScalarSizeInBits();
+
+  SDValue X;
+  if (!sd_match(Src, m_Xor(m_Value(X),
+                           m_Sra(m_Deferred(X), m_SpecificInt(BitWidth - 1)))))
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topperc wrote:

On the xor or sra or both?

https://github.com/llvm/llvm-project/pull/173417