[llvm] [RISCV][SelectionDAG] Add a ISD::CTLS node for count leading redundant sign bits. Use it to select CLS(W). (PR #173417)

[Matt Arsenault via llvm-commits]

================
@@ -11811,6 +11813,27 @@ SDValue DAGCombiner::visitBITREVERSE(SDNode *N) {
   return SDValue();
 }
 
+// Fold (ctlz (xor x, (sra x, bitwidth-1))) -> (add (ctls x), 1).
+SDValue DAGCombiner::foldCTLZToCTLS(SDValue Src, const SDLoc &DL) {
+  EVT VT = Src.getValueType();
+
+  auto LK = TLI.getTypeConversion(*DAG.getContext(), VT);
+  if (!(LK.first == TargetLoweringBase::TypeLegal ||
----------------
arsenm wrote:

push negate through 

https://github.com/llvm/llvm-project/pull/173417