[llvm] Fix typo in condition. (PR #173450)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: None (Seraphimt)

<details>
<summary>Changes</summary>

Minor fix typo.
Main issue:
https://github.com/llvm/llvm-project/issues/169959

I did research and found file with tests but I couldn't figure out how cover this change. if this needs to be added then please advise. 
@<!-- -->tomershafir 

---
Full diff: https://github.com/llvm/llvm-project/pull/173450.diff


1 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 5720bef575892..8f6b2a95d5116 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5791,7 +5791,7 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       AArch64::FPR8RegClass.contains(SrcReg)) {
     if (Subtarget.hasZeroCycleRegMoveFPR128() &&
         !Subtarget.hasZeroCycleRegMoveFPR64() &&
-        !Subtarget.hasZeroCycleRegMoveFPR64() && Subtarget.isNeonAvailable()) {
+        !Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
       MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
                                                    &AArch64::FPR128RegClass);
       MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,

``````````

</details>


https://github.com/llvm/llvm-project/pull/173450