[llvm] Fix typo in condition. (PR #173450)

[via llvm-commits]

https://github.com/Seraphimt created https://github.com/llvm/llvm-project/pull/173450

Minor fix typo.
Main issue:
https://github.com/llvm/llvm-project/issues/169959

I did research and found file with tests but I couldn't figure out how cover this change. if this needs to be added then please advise. 
@tomershafir 

>From 9bd95da8afc84b9c1a0078b6a7a282054e8a3592 Mon Sep 17 00:00:00 2001
From: Seraphimt <svet58585 at mail.ru>
Date: Wed, 24 Dec 2025 08:15:55 +0300
Subject: [PATCH] Fix typo in condition.

---
 llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 5720bef575892..8f6b2a95d5116 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5791,7 +5791,7 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       AArch64::FPR8RegClass.contains(SrcReg)) {
     if (Subtarget.hasZeroCycleRegMoveFPR128() &&
         !Subtarget.hasZeroCycleRegMoveFPR64() &&
-        !Subtarget.hasZeroCycleRegMoveFPR64() && Subtarget.isNeonAvailable()) {
+        !Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
       MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
                                                    &AArch64::FPR128RegClass);
       MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,