[llvm] [RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (PR #172556)

[Craig Topper via llvm-commits]

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@@ -1033,9 +1036,27 @@ def : WriteRes<WriteCSR, [SMX60_IEU]>;
 def : WriteRes<WriteNop, [SMX60_IEU]>;
 def : WriteRes<WriteRdVLENB, [SMX60_IEUA]>;
 
-// Give COPY instructions an execution resource.
-// FIXME: This could be better modeled by looking at the regclasses of the operands.
-def : InstRW<[WriteIALU], (instrs COPY)>;
+// Assign scheduling info to COPY instructions.
+// Note: We try NOT to assign ProcResource but only latency to vector COPY because
+// those resources might prevent those COPYs from showing up to the scheulder
+// until it's too late.
+// Specifically, for a given COPY of live-in (physical) register, ideally we want it
+// to be visible to the top available queue as early as possible so that it can be scheduled
+// at the beginning of the function. Assigning resource to vector COPYs might risk
+// creating structural hazard that prevents those COPYs from even entering the available
+// queue and as a consequence, sinking those COPYs.
+// I see little difference on assigning ProcResource to scalar COPY or not, so I'm still
+// assigning WriteIALU to it.
+def SMX60CopySchedWriteVariant : SchedWriteVariant<[
+  SchedVar<SchedPredicate<[{ TII->isVRegCopy(MI, /*LMUL=*/1) }]>, [SMX60WriteVCOPY_M1]>,
+  SchedVar<SchedPredicate<[{ TII->isVRegCopy(MI, /*LMUL=*/2) }]>, [SMX60WriteVCOPY_M2]>,
+  SchedVar<SchedPredicate<[{ TII->isVRegCopy(MI, /*LMUL=*/4) }]>, [SMX60WriteVCOPY_M4]>,
+  SchedVar<SchedPredicate<[{ TII->isVRegCopy(MI, /*LMUL=*/8) }]>, [SMX60WriteVCOPY_M8]>,
+  // Every other types of vector register classes are default to M1.
+  SchedVar<SchedPredicate<[{ TII->isVRegCopy(MI) }]>,             [SMX60WriteVCOPY_M1]>,
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topperc wrote:

Is this case necessary? Shouldn't all vector registers fall into one of the above?

https://github.com/llvm/llvm-project/pull/172556