[llvm] [AArch64][GlobalISel] Fix vector lrint/llrint fallbacks (PR #170814)

[David Green via llvm-commits]

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@@ -15,369 +16,530 @@ define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) nounwind {
 declare <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half>)
 
 define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) nounwind {
-; CHECK-LABEL: llrint_v1i64_v2f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    frintx s0, s0
-; CHECK-NEXT:    frintx s1, s1
-; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    fcvtzs x9, s1
-; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    mov v0.d[1], x9
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: llrint_v1i64_v2f16:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT:    mov h1, v0.h[1]
+; CHECK-SD-NEXT:    fcvt s0, h0
+; CHECK-SD-NEXT:    fcvt s1, h1
+; CHECK-SD-NEXT:    frintx s0, s0
+; CHECK-SD-NEXT:    frintx s1, s1
+; CHECK-SD-NEXT:    fcvtzs x8, s0
+; CHECK-SD-NEXT:    fcvtzs x9, s1
+; CHECK-SD-NEXT:    fmov d0, x8
+; CHECK-SD-NEXT:    mov v0.d[1], x9
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: llrint_v1i64_v2f16:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT:    frintx v0.2s, v0.2s
+; CHECK-GI-NEXT:    fcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT:    fcvtl v0.2d, v0.2s
+; CHECK-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT:    ret
----------------
davemgreen wrote:

Vector lrint/lround are fairly new to SDAG too. So new it doesn't looks like we even have test coverage for lround. I was hoping we would be able to go through and use the vector instructions we have produce better codegen - it's not something we have looked into properly much yet.

https://github.com/llvm/llvm-project/pull/170814