[llvm] 76c3eed - [AArch64][GlobalISel] Fix vector lrint/llrint fallbacks (#170814)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 12 11:11:15 PST 2025
Author: ayank227
Date: 2025-12-12T20:11:10+01:00
New Revision: 76c3eed67321dc21a3bac493771da70b726ee883
URL: https://github.com/llvm/llvm-project/commit/76c3eed67321dc21a3bac493771da70b726ee883
DIFF: https://github.com/llvm/llvm-project/commit/76c3eed67321dc21a3bac493771da70b726ee883.diff
LOG: [AArch64][GlobalISel] Fix vector lrint/llrint fallbacks (#170814)
Add .lower() to vector lrint/llrint to enable lowering instead of
falling back to SelectionDAG.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/AArch64/vector-llrint.ll
llvm/test/CodeGen/AArch64/vector-lrint.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 44a148940ec96..112f3c2b9634a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -450,13 +450,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalFor({{s32, s32}, {s32, s64}, {s64, s32}, {s64, s64}})
.legalFor(HasFP16, {{s32, s16}, {s64, s16}})
.minScalar(1, s32)
- .libcallFor({{s64, s128}});
+ .libcallFor({{s64, s128}})
+ .lower();
getActionDefinitionsBuilder({G_LLROUND, G_INTRINSIC_LLRINT})
.legalFor({{s64, s32}, {s64, s64}})
.legalFor(HasFP16, {{s64, s16}})
.minScalar(0, s64)
.minScalar(1, s32)
- .libcallFor({{s64, s128}});
+ .libcallFor({{s64, s128}})
+ .lower();
// TODO: Custom legalization for mismatched types.
getActionDefinitionsBuilder(G_FCOPYSIGN)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index af72ffbcfadce..8a0071c9ea5c1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -188,12 +188,12 @@
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_INTRINSIC_LRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
-# DEBUG-NEXT: .. the first uncovered type index: 2, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_INTRINSIC_LLRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
-# DEBUG-NEXT: .. the first uncovered type index: 2, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_INTRINSIC_ROUNDEVEN (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
@@ -696,11 +696,11 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_LROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. the first uncovered type index: 2, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_LLROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. the first uncovered type index: 2, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_BR (opcode {{[0-9]+}}): 0 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/AArch64/vector-llrint.ll b/llvm/test/CodeGen/AArch64/vector-llrint.ll
index 45c9e4c9c7194..4e86832a5dffa 100644
--- a/llvm/test/CodeGen/AArch64/vector-llrint.ll
+++ b/llvm/test/CodeGen/AArch64/vector-llrint.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) nounwind {
; CHECK-LABEL: llrint_v1i64_v1f16:
@@ -15,369 +16,530 @@ define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) nounwind {
declare <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half>)
define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) nounwind {
-; CHECK-LABEL: llrint_v1i64_v2f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: frintx s0, s0
-; CHECK-NEXT: frintx s1, s1
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: fcvtzs x9, s1
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: mov v0.d[1], x9
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v1i64_v2f16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: mov h1, v0.h[1]
+; CHECK-SD-NEXT: fcvt s0, h0
+; CHECK-SD-NEXT: fcvt s1, h1
+; CHECK-SD-NEXT: frintx s0, s0
+; CHECK-SD-NEXT: frintx s1, s1
+; CHECK-SD-NEXT: fcvtzs x8, s0
+; CHECK-SD-NEXT: fcvtzs x9, s1
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: mov v0.d[1], x9
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v1i64_v2f16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: frintx v0.2s, v0.2s
+; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: ret
%a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x)
ret <2 x i64> %a
}
declare <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half>)
define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) nounwind {
-; CHECK-LABEL: llrint_v4i64_v4f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: mov h2, v0.h[1]
-; CHECK-NEXT: mov h3, v0.h[3]
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: frintx s0, s0
-; CHECK-NEXT: frintx s1, s1
-; CHECK-NEXT: frintx s2, s2
-; CHECK-NEXT: frintx s3, s3
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: fcvtzs x9, s1
-; CHECK-NEXT: fcvtzs x10, s2
-; CHECK-NEXT: fcvtzs x11, s3
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: mov v0.d[1], x10
-; CHECK-NEXT: mov v1.d[1], x11
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v4i64_v4f16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: mov h1, v0.h[2]
+; CHECK-SD-NEXT: mov h2, v0.h[1]
+; CHECK-SD-NEXT: mov h3, v0.h[3]
+; CHECK-SD-NEXT: fcvt s0, h0
+; CHECK-SD-NEXT: fcvt s1, h1
+; CHECK-SD-NEXT: fcvt s2, h2
+; CHECK-SD-NEXT: fcvt s3, h3
+; CHECK-SD-NEXT: frintx s0, s0
+; CHECK-SD-NEXT: frintx s1, s1
+; CHECK-SD-NEXT: frintx s2, s2
+; CHECK-SD-NEXT: frintx s3, s3
+; CHECK-SD-NEXT: fcvtzs x8, s0
+; CHECK-SD-NEXT: fcvtzs x9, s1
+; CHECK-SD-NEXT: fcvtzs x10, s2
+; CHECK-SD-NEXT: fcvtzs x11, s3
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: mov v0.d[1], x10
+; CHECK-SD-NEXT: mov v1.d[1], x11
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v4i64_v4f16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-GI-NEXT: fcvtzs v0.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-GI-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)
ret <4 x i64> %a
}
declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>)
define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind {
-; CHECK-LABEL: llrint_v8i64_v8f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: mov h4, v0.h[2]
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: mov h7, v0.h[3]
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: mov h2, v1.h[2]
-; CHECK-NEXT: mov h5, v1.h[1]
-; CHECK-NEXT: mov h6, v1.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvt s7, h7
-; CHECK-NEXT: frintx s0, s0
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: fcvt s6, h6
-; CHECK-NEXT: frintx s1, s1
-; CHECK-NEXT: frintx s4, s4
-; CHECK-NEXT: frintx s3, s3
-; CHECK-NEXT: frintx s7, s7
-; CHECK-NEXT: fcvtzs x9, s0
-; CHECK-NEXT: frintx s2, s2
-; CHECK-NEXT: frintx s5, s5
-; CHECK-NEXT: frintx s6, s6
-; CHECK-NEXT: fcvtzs x8, s1
-; CHECK-NEXT: fcvtzs x12, s4
-; CHECK-NEXT: fcvtzs x11, s3
-; CHECK-NEXT: fcvtzs x15, s7
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fcvtzs x10, s2
-; CHECK-NEXT: fcvtzs x13, s5
-; CHECK-NEXT: fcvtzs x14, s6
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: fmov d1, x12
-; CHECK-NEXT: mov v0.d[1], x11
-; CHECK-NEXT: fmov d3, x10
-; CHECK-NEXT: mov v2.d[1], x13
-; CHECK-NEXT: mov v1.d[1], x15
-; CHECK-NEXT: mov v3.d[1], x14
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v8i64_v8f16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov h4, v0.h[2]
+; CHECK-SD-NEXT: mov h3, v0.h[1]
+; CHECK-SD-NEXT: mov h7, v0.h[3]
+; CHECK-SD-NEXT: fcvt s0, h0
+; CHECK-SD-NEXT: mov h2, v1.h[2]
+; CHECK-SD-NEXT: mov h5, v1.h[1]
+; CHECK-SD-NEXT: mov h6, v1.h[3]
+; CHECK-SD-NEXT: fcvt s1, h1
+; CHECK-SD-NEXT: fcvt s4, h4
+; CHECK-SD-NEXT: fcvt s3, h3
+; CHECK-SD-NEXT: fcvt s7, h7
+; CHECK-SD-NEXT: frintx s0, s0
+; CHECK-SD-NEXT: fcvt s2, h2
+; CHECK-SD-NEXT: fcvt s5, h5
+; CHECK-SD-NEXT: fcvt s6, h6
+; CHECK-SD-NEXT: frintx s1, s1
+; CHECK-SD-NEXT: frintx s4, s4
+; CHECK-SD-NEXT: frintx s3, s3
+; CHECK-SD-NEXT: frintx s7, s7
+; CHECK-SD-NEXT: fcvtzs x9, s0
+; CHECK-SD-NEXT: frintx s2, s2
+; CHECK-SD-NEXT: frintx s5, s5
+; CHECK-SD-NEXT: frintx s6, s6
+; CHECK-SD-NEXT: fcvtzs x8, s1
+; CHECK-SD-NEXT: fcvtzs x12, s4
+; CHECK-SD-NEXT: fcvtzs x11, s3
+; CHECK-SD-NEXT: fcvtzs x15, s7
+; CHECK-SD-NEXT: fmov d0, x9
+; CHECK-SD-NEXT: fcvtzs x10, s2
+; CHECK-SD-NEXT: fcvtzs x13, s5
+; CHECK-SD-NEXT: fcvtzs x14, s6
+; CHECK-SD-NEXT: fmov d2, x8
+; CHECK-SD-NEXT: fmov d1, x12
+; CHECK-SD-NEXT: mov v0.d[1], x11
+; CHECK-SD-NEXT: fmov d3, x10
+; CHECK-SD-NEXT: mov v2.d[1], x13
+; CHECK-SD-NEXT: mov v1.d[1], x15
+; CHECK-SD-NEXT: mov v3.d[1], x14
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v8i64_v8f16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-GI-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl v2.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-GI-NEXT: fcvtl v3.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v4.2d, v0.4s
+; CHECK-GI-NEXT: fcvtzs v0.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-GI-NEXT: fcvtzs v3.2d, v4.2d
+; CHECK-GI-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)
ret <8 x i64> %a
}
declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)
define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind {
-; CHECK-LABEL: llrint_v16i64_v16f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: mov h17, v0.h[1]
-; CHECK-NEXT: mov h19, v0.h[2]
-; CHECK-NEXT: fcvt s18, h0
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: mov h4, v2.h[1]
-; CHECK-NEXT: mov h5, v2.h[2]
-; CHECK-NEXT: fcvt s7, h3
-; CHECK-NEXT: fcvt s6, h2
-; CHECK-NEXT: mov h16, v3.h[2]
-; CHECK-NEXT: mov h2, v2.h[3]
-; CHECK-NEXT: fcvt s17, h17
-; CHECK-NEXT: fcvt s19, h19
-; CHECK-NEXT: frintx s18, s18
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: frintx s7, s7
-; CHECK-NEXT: frintx s6, s6
-; CHECK-NEXT: fcvt s16, h16
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: frintx s17, s17
-; CHECK-NEXT: frintx s19, s19
-; CHECK-NEXT: fcvtzs x13, s18
-; CHECK-NEXT: frintx s0, s0
-; CHECK-NEXT: frintx s4, s4
-; CHECK-NEXT: frintx s5, s5
-; CHECK-NEXT: fcvtzs x9, s7
-; CHECK-NEXT: mov h7, v1.h[2]
-; CHECK-NEXT: fcvtzs x8, s6
-; CHECK-NEXT: mov h6, v1.h[1]
-; CHECK-NEXT: frintx s16, s16
-; CHECK-NEXT: fcvtzs x14, s17
-; CHECK-NEXT: fcvtzs x15, s19
-; CHECK-NEXT: fcvtzs x10, s4
-; CHECK-NEXT: mov h4, v3.h[1]
-; CHECK-NEXT: fcvtzs x11, s5
-; CHECK-NEXT: mov h5, v1.h[3]
-; CHECK-NEXT: mov h3, v3.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s7, h7
-; CHECK-NEXT: fcvt s6, h6
-; CHECK-NEXT: fcvtzs x12, s16
-; CHECK-NEXT: frintx s16, s2
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: frintx s1, s1
-; CHECK-NEXT: frintx s7, s7
-; CHECK-NEXT: frintx s17, s6
-; CHECK-NEXT: fmov d6, x9
-; CHECK-NEXT: mov v2.d[1], x10
-; CHECK-NEXT: frintx s4, s4
-; CHECK-NEXT: frintx s18, s3
-; CHECK-NEXT: frintx s5, s5
-; CHECK-NEXT: fcvtzs x8, s1
-; CHECK-NEXT: fcvtzs x9, s7
-; CHECK-NEXT: fmov d3, x11
-; CHECK-NEXT: fcvtzs x11, s0
-; CHECK-NEXT: fmov d7, x12
-; CHECK-NEXT: fcvtzs x12, s16
-; CHECK-NEXT: fcvtzs x16, s17
-; CHECK-NEXT: fcvtzs x17, s4
-; CHECK-NEXT: fmov d0, x13
-; CHECK-NEXT: fmov d1, x15
-; CHECK-NEXT: fcvtzs x18, s18
-; CHECK-NEXT: fcvtzs x0, s5
-; CHECK-NEXT: fmov d4, x8
-; CHECK-NEXT: fmov d5, x9
-; CHECK-NEXT: mov v0.d[1], x14
-; CHECK-NEXT: mov v1.d[1], x11
-; CHECK-NEXT: mov v3.d[1], x12
-; CHECK-NEXT: mov v4.d[1], x16
-; CHECK-NEXT: mov v6.d[1], x17
-; CHECK-NEXT: mov v7.d[1], x18
-; CHECK-NEXT: mov v5.d[1], x0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v16i64_v16f16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov h17, v0.h[1]
+; CHECK-SD-NEXT: mov h19, v0.h[2]
+; CHECK-SD-NEXT: fcvt s18, h0
+; CHECK-SD-NEXT: mov h0, v0.h[3]
+; CHECK-SD-NEXT: mov h4, v2.h[1]
+; CHECK-SD-NEXT: mov h5, v2.h[2]
+; CHECK-SD-NEXT: fcvt s7, h3
+; CHECK-SD-NEXT: fcvt s6, h2
+; CHECK-SD-NEXT: mov h16, v3.h[2]
+; CHECK-SD-NEXT: mov h2, v2.h[3]
+; CHECK-SD-NEXT: fcvt s17, h17
+; CHECK-SD-NEXT: fcvt s19, h19
+; CHECK-SD-NEXT: frintx s18, s18
+; CHECK-SD-NEXT: fcvt s0, h0
+; CHECK-SD-NEXT: fcvt s4, h4
+; CHECK-SD-NEXT: fcvt s5, h5
+; CHECK-SD-NEXT: frintx s7, s7
+; CHECK-SD-NEXT: frintx s6, s6
+; CHECK-SD-NEXT: fcvt s16, h16
+; CHECK-SD-NEXT: fcvt s2, h2
+; CHECK-SD-NEXT: frintx s17, s17
+; CHECK-SD-NEXT: frintx s19, s19
+; CHECK-SD-NEXT: fcvtzs x13, s18
+; CHECK-SD-NEXT: frintx s0, s0
+; CHECK-SD-NEXT: frintx s4, s4
+; CHECK-SD-NEXT: frintx s5, s5
+; CHECK-SD-NEXT: fcvtzs x9, s7
+; CHECK-SD-NEXT: mov h7, v1.h[2]
+; CHECK-SD-NEXT: fcvtzs x8, s6
+; CHECK-SD-NEXT: mov h6, v1.h[1]
+; CHECK-SD-NEXT: frintx s16, s16
+; CHECK-SD-NEXT: fcvtzs x14, s17
+; CHECK-SD-NEXT: fcvtzs x15, s19
+; CHECK-SD-NEXT: fcvtzs x10, s4
+; CHECK-SD-NEXT: mov h4, v3.h[1]
+; CHECK-SD-NEXT: fcvtzs x11, s5
+; CHECK-SD-NEXT: mov h5, v1.h[3]
+; CHECK-SD-NEXT: mov h3, v3.h[3]
+; CHECK-SD-NEXT: fcvt s1, h1
+; CHECK-SD-NEXT: fcvt s7, h7
+; CHECK-SD-NEXT: fcvt s6, h6
+; CHECK-SD-NEXT: fcvtzs x12, s16
+; CHECK-SD-NEXT: frintx s16, s2
+; CHECK-SD-NEXT: fmov d2, x8
+; CHECK-SD-NEXT: fcvt s4, h4
+; CHECK-SD-NEXT: fcvt s3, h3
+; CHECK-SD-NEXT: fcvt s5, h5
+; CHECK-SD-NEXT: frintx s1, s1
+; CHECK-SD-NEXT: frintx s7, s7
+; CHECK-SD-NEXT: frintx s17, s6
+; CHECK-SD-NEXT: fmov d6, x9
+; CHECK-SD-NEXT: mov v2.d[1], x10
+; CHECK-SD-NEXT: frintx s4, s4
+; CHECK-SD-NEXT: frintx s18, s3
+; CHECK-SD-NEXT: frintx s5, s5
+; CHECK-SD-NEXT: fcvtzs x8, s1
+; CHECK-SD-NEXT: fcvtzs x9, s7
+; CHECK-SD-NEXT: fmov d3, x11
+; CHECK-SD-NEXT: fcvtzs x11, s0
+; CHECK-SD-NEXT: fmov d7, x12
+; CHECK-SD-NEXT: fcvtzs x12, s16
+; CHECK-SD-NEXT: fcvtzs x16, s17
+; CHECK-SD-NEXT: fcvtzs x17, s4
+; CHECK-SD-NEXT: fmov d0, x13
+; CHECK-SD-NEXT: fmov d1, x15
+; CHECK-SD-NEXT: fcvtzs x18, s18
+; CHECK-SD-NEXT: fcvtzs x0, s5
+; CHECK-SD-NEXT: fmov d4, x8
+; CHECK-SD-NEXT: fmov d5, x9
+; CHECK-SD-NEXT: mov v0.d[1], x14
+; CHECK-SD-NEXT: mov v1.d[1], x11
+; CHECK-SD-NEXT: mov v3.d[1], x12
+; CHECK-SD-NEXT: mov v4.d[1], x16
+; CHECK-SD-NEXT: mov v6.d[1], x17
+; CHECK-SD-NEXT: mov v7.d[1], x18
+; CHECK-SD-NEXT: mov v5.d[1], x0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v16i64_v16f16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-GI-NEXT: frintx v2.4s, v2.4s
+; CHECK-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-GI-NEXT: frintx v3.4s, v3.4s
+; CHECK-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-GI-NEXT: fcvtn v2.4h, v2.4s
+; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-GI-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-GI-NEXT: fcvtl v2.4s, v2.4h
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl v3.4s, v3.4h
+; CHECK-GI-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-GI-NEXT: fcvtl v4.2d, v2.2s
+; CHECK-GI-NEXT: fcvtl2 v2.2d, v2.4s
+; CHECK-GI-NEXT: fcvtl v5.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v6.2d, v0.4s
+; CHECK-GI-NEXT: fcvtl v7.2d, v3.2s
+; CHECK-GI-NEXT: fcvtl2 v16.2d, v3.4s
+; CHECK-GI-NEXT: fcvtl v17.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v18.2d, v1.4s
+; CHECK-GI-NEXT: fcvtzs v0.2d, v4.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v2.2d, v5.2d
+; CHECK-GI-NEXT: fcvtzs v3.2d, v6.2d
+; CHECK-GI-NEXT: fcvtzs v4.2d, v7.2d
+; CHECK-GI-NEXT: fcvtzs v5.2d, v16.2d
+; CHECK-GI-NEXT: fcvtzs v6.2d, v17.2d
+; CHECK-GI-NEXT: fcvtzs v7.2d, v18.2d
+; CHECK-GI-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)
ret <16 x i64> %a
}
declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)
define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind {
-; CHECK-LABEL: llrint_v32i64_v32f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v5.16b, v2.16b, v2.16b, #8
-; CHECK-NEXT: ext v6.16b, v3.16b, v3.16b, #8
-; CHECK-NEXT: ext v7.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: mov h19, v0.h[1]
-; CHECK-NEXT: fcvt s21, h0
-; CHECK-NEXT: mov h23, v1.h[2]
-; CHECK-NEXT: fcvt s22, h1
-; CHECK-NEXT: fcvt s26, h2
-; CHECK-NEXT: mov h27, v2.h[1]
-; CHECK-NEXT: mov h28, v2.h[2]
-; CHECK-NEXT: mov h16, v4.h[2]
-; CHECK-NEXT: fcvt s17, h5
-; CHECK-NEXT: mov h18, v5.h[2]
-; CHECK-NEXT: mov h20, v6.h[2]
-; CHECK-NEXT: fcvt s24, h7
-; CHECK-NEXT: fcvt s25, h6
-; CHECK-NEXT: fcvt s19, h19
-; CHECK-NEXT: frintx s22, s22
-; CHECK-NEXT: fcvt s16, h16
-; CHECK-NEXT: frintx s17, s17
-; CHECK-NEXT: fcvt s18, h18
-; CHECK-NEXT: fcvt s20, h20
-; CHECK-NEXT: frintx s16, s16
-; CHECK-NEXT: fcvtzs x12, s17
-; CHECK-NEXT: frintx s17, s18
-; CHECK-NEXT: frintx s18, s21
-; CHECK-NEXT: fcvt s21, h23
-; CHECK-NEXT: frintx s23, s24
-; CHECK-NEXT: frintx s24, s25
-; CHECK-NEXT: frintx s25, s19
-; CHECK-NEXT: mov h19, v7.h[1]
-; CHECK-NEXT: fcvtzs x13, s16
-; CHECK-NEXT: frintx s16, s20
-; CHECK-NEXT: frintx s20, s26
-; CHECK-NEXT: fcvtzs x9, s23
-; CHECK-NEXT: mov h23, v3.h[2]
-; CHECK-NEXT: fcvt s26, h27
-; CHECK-NEXT: fcvtzs x15, s24
-; CHECK-NEXT: fcvtzs x10, s25
-; CHECK-NEXT: fcvt s24, h28
-; CHECK-NEXT: mov h25, v3.h[3]
-; CHECK-NEXT: fcvtzs x14, s17
-; CHECK-NEXT: frintx s21, s21
-; CHECK-NEXT: fmov d17, x12
-; CHECK-NEXT: fcvtzs x12, s16
-; CHECK-NEXT: fmov d16, x13
-; CHECK-NEXT: fcvtzs x13, s22
-; CHECK-NEXT: fcvt s22, h3
-; CHECK-NEXT: mov h3, v3.h[1]
-; CHECK-NEXT: mov h27, v0.h[2]
-; CHECK-NEXT: mov h28, v2.h[3]
-; CHECK-NEXT: fcvt s23, h23
-; CHECK-NEXT: frintx s26, s26
-; CHECK-NEXT: fcvtzs x16, s20
-; CHECK-NEXT: frintx s20, s24
-; CHECK-NEXT: fcvt s24, h25
-; CHECK-NEXT: fcvtzs x11, s18
-; CHECK-NEXT: fmov d18, x14
-; CHECK-NEXT: fcvtzs x14, s21
-; CHECK-NEXT: frintx s22, s22
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvt s25, h27
-; CHECK-NEXT: fcvt s27, h28
-; CHECK-NEXT: frintx s23, s23
-; CHECK-NEXT: mov h21, v1.h[3]
-; CHECK-NEXT: fmov d2, x15
-; CHECK-NEXT: fcvtzs x15, s26
-; CHECK-NEXT: fmov d26, x13
-; CHECK-NEXT: mov h1, v1.h[1]
-; CHECK-NEXT: fcvtzs x13, s20
-; CHECK-NEXT: frintx s20, s24
-; CHECK-NEXT: fmov d24, x14
-; CHECK-NEXT: fcvtzs x14, s22
-; CHECK-NEXT: frintx s3, s3
-; CHECK-NEXT: fmov d22, x16
-; CHECK-NEXT: frintx s27, s27
-; CHECK-NEXT: fcvtzs x16, s23
-; CHECK-NEXT: fcvt s21, h21
-; CHECK-NEXT: frintx s25, s25
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: mov h23, v7.h[2]
-; CHECK-NEXT: mov v22.d[1], x15
-; CHECK-NEXT: fcvtzs x15, s20
-; CHECK-NEXT: fmov d20, x13
-; CHECK-NEXT: fcvtzs x13, s3
-; CHECK-NEXT: fmov d3, x14
-; CHECK-NEXT: fcvtzs x14, s27
-; CHECK-NEXT: fmov d27, x16
-; CHECK-NEXT: frintx s21, s21
-; CHECK-NEXT: mov h7, v7.h[3]
-; CHECK-NEXT: frintx s1, s1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvt s23, h23
-; CHECK-NEXT: fcvt s19, h19
-; CHECK-NEXT: mov v27.d[1], x15
-; CHECK-NEXT: fcvtzs x15, s25
-; CHECK-NEXT: mov h25, v6.h[3]
-; CHECK-NEXT: mov h6, v6.h[1]
-; CHECK-NEXT: mov v3.d[1], x13
-; CHECK-NEXT: fcvtzs x13, s21
-; CHECK-NEXT: mov h21, v5.h[1]
-; CHECK-NEXT: mov h5, v5.h[3]
-; CHECK-NEXT: mov v20.d[1], x14
-; CHECK-NEXT: fcvtzs x14, s1
-; CHECK-NEXT: mov h1, v4.h[1]
-; CHECK-NEXT: frintx s0, s0
-; CHECK-NEXT: fcvt s25, h25
-; CHECK-NEXT: fcvt s7, h7
-; CHECK-NEXT: stp q3, q27, [x8, #192]
-; CHECK-NEXT: fcvt s6, h6
-; CHECK-NEXT: mov h3, v4.h[3]
-; CHECK-NEXT: stp q22, q20, [x8, #128]
-; CHECK-NEXT: fcvt s21, h21
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: mov v24.d[1], x13
-; CHECK-NEXT: mov v26.d[1], x14
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: frintx s22, s25
-; CHECK-NEXT: fmov d20, x12
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: frintx s6, s6
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvtzs x12, s0
-; CHECK-NEXT: frintx s5, s5
-; CHECK-NEXT: frintx s21, s21
-; CHECK-NEXT: fmov d0, x11
-; CHECK-NEXT: stp q26, q24, [x8, #64]
-; CHECK-NEXT: fmov d24, x15
-; CHECK-NEXT: frintx s4, s4
-; CHECK-NEXT: fcvtzs x11, s22
-; CHECK-NEXT: frintx s22, s23
-; CHECK-NEXT: frintx s1, s1
-; CHECK-NEXT: fcvtzs x13, s6
-; CHECK-NEXT: frintx s3, s3
-; CHECK-NEXT: frintx s6, s7
-; CHECK-NEXT: fcvtzs x14, s5
-; CHECK-NEXT: mov v24.d[1], x12
-; CHECK-NEXT: frintx s5, s19
-; CHECK-NEXT: fcvtzs x12, s21
-; CHECK-NEXT: mov v0.d[1], x10
-; CHECK-NEXT: fcvtzs x10, s4
-; CHECK-NEXT: mov v20.d[1], x11
-; CHECK-NEXT: fcvtzs x11, s22
-; CHECK-NEXT: mov v2.d[1], x13
-; CHECK-NEXT: fcvtzs x15, s3
-; CHECK-NEXT: fcvtzs x13, s1
-; CHECK-NEXT: mov v18.d[1], x14
-; CHECK-NEXT: fcvtzs x14, s6
-; CHECK-NEXT: stp q0, q24, [x8]
-; CHECK-NEXT: mov v17.d[1], x12
-; CHECK-NEXT: fcvtzs x12, s5
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: fmov d1, x11
-; CHECK-NEXT: stp q2, q20, [x8, #224]
-; CHECK-NEXT: fmov d2, x9
-; CHECK-NEXT: mov v16.d[1], x15
-; CHECK-NEXT: stp q17, q18, [x8, #160]
-; CHECK-NEXT: mov v0.d[1], x13
-; CHECK-NEXT: mov v1.d[1], x14
-; CHECK-NEXT: mov v2.d[1], x12
-; CHECK-NEXT: stp q0, q16, [x8, #96]
-; CHECK-NEXT: stp q2, q1, [x8, #32]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v32i64_v32f16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v4.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: ext v5.16b, v2.16b, v2.16b, #8
+; CHECK-SD-NEXT: ext v6.16b, v3.16b, v3.16b, #8
+; CHECK-SD-NEXT: ext v7.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: mov h19, v0.h[1]
+; CHECK-SD-NEXT: fcvt s21, h0
+; CHECK-SD-NEXT: mov h23, v1.h[2]
+; CHECK-SD-NEXT: fcvt s22, h1
+; CHECK-SD-NEXT: fcvt s26, h2
+; CHECK-SD-NEXT: mov h27, v2.h[1]
+; CHECK-SD-NEXT: mov h28, v2.h[2]
+; CHECK-SD-NEXT: mov h16, v4.h[2]
+; CHECK-SD-NEXT: fcvt s17, h5
+; CHECK-SD-NEXT: mov h18, v5.h[2]
+; CHECK-SD-NEXT: mov h20, v6.h[2]
+; CHECK-SD-NEXT: fcvt s24, h7
+; CHECK-SD-NEXT: fcvt s25, h6
+; CHECK-SD-NEXT: fcvt s19, h19
+; CHECK-SD-NEXT: frintx s22, s22
+; CHECK-SD-NEXT: fcvt s16, h16
+; CHECK-SD-NEXT: frintx s17, s17
+; CHECK-SD-NEXT: fcvt s18, h18
+; CHECK-SD-NEXT: fcvt s20, h20
+; CHECK-SD-NEXT: frintx s16, s16
+; CHECK-SD-NEXT: fcvtzs x12, s17
+; CHECK-SD-NEXT: frintx s17, s18
+; CHECK-SD-NEXT: frintx s18, s21
+; CHECK-SD-NEXT: fcvt s21, h23
+; CHECK-SD-NEXT: frintx s23, s24
+; CHECK-SD-NEXT: frintx s24, s25
+; CHECK-SD-NEXT: frintx s25, s19
+; CHECK-SD-NEXT: mov h19, v7.h[1]
+; CHECK-SD-NEXT: fcvtzs x13, s16
+; CHECK-SD-NEXT: frintx s16, s20
+; CHECK-SD-NEXT: frintx s20, s26
+; CHECK-SD-NEXT: fcvtzs x9, s23
+; CHECK-SD-NEXT: mov h23, v3.h[2]
+; CHECK-SD-NEXT: fcvt s26, h27
+; CHECK-SD-NEXT: fcvtzs x15, s24
+; CHECK-SD-NEXT: fcvtzs x10, s25
+; CHECK-SD-NEXT: fcvt s24, h28
+; CHECK-SD-NEXT: mov h25, v3.h[3]
+; CHECK-SD-NEXT: fcvtzs x14, s17
+; CHECK-SD-NEXT: frintx s21, s21
+; CHECK-SD-NEXT: fmov d17, x12
+; CHECK-SD-NEXT: fcvtzs x12, s16
+; CHECK-SD-NEXT: fmov d16, x13
+; CHECK-SD-NEXT: fcvtzs x13, s22
+; CHECK-SD-NEXT: fcvt s22, h3
+; CHECK-SD-NEXT: mov h3, v3.h[1]
+; CHECK-SD-NEXT: mov h27, v0.h[2]
+; CHECK-SD-NEXT: mov h28, v2.h[3]
+; CHECK-SD-NEXT: fcvt s23, h23
+; CHECK-SD-NEXT: frintx s26, s26
+; CHECK-SD-NEXT: fcvtzs x16, s20
+; CHECK-SD-NEXT: frintx s20, s24
+; CHECK-SD-NEXT: fcvt s24, h25
+; CHECK-SD-NEXT: fcvtzs x11, s18
+; CHECK-SD-NEXT: fmov d18, x14
+; CHECK-SD-NEXT: fcvtzs x14, s21
+; CHECK-SD-NEXT: frintx s22, s22
+; CHECK-SD-NEXT: fcvt s3, h3
+; CHECK-SD-NEXT: fcvt s25, h27
+; CHECK-SD-NEXT: fcvt s27, h28
+; CHECK-SD-NEXT: frintx s23, s23
+; CHECK-SD-NEXT: mov h21, v1.h[3]
+; CHECK-SD-NEXT: fmov d2, x15
+; CHECK-SD-NEXT: fcvtzs x15, s26
+; CHECK-SD-NEXT: fmov d26, x13
+; CHECK-SD-NEXT: mov h1, v1.h[1]
+; CHECK-SD-NEXT: fcvtzs x13, s20
+; CHECK-SD-NEXT: frintx s20, s24
+; CHECK-SD-NEXT: fmov d24, x14
+; CHECK-SD-NEXT: fcvtzs x14, s22
+; CHECK-SD-NEXT: frintx s3, s3
+; CHECK-SD-NEXT: fmov d22, x16
+; CHECK-SD-NEXT: frintx s27, s27
+; CHECK-SD-NEXT: fcvtzs x16, s23
+; CHECK-SD-NEXT: fcvt s21, h21
+; CHECK-SD-NEXT: frintx s25, s25
+; CHECK-SD-NEXT: fcvt s1, h1
+; CHECK-SD-NEXT: mov h0, v0.h[3]
+; CHECK-SD-NEXT: mov h23, v7.h[2]
+; CHECK-SD-NEXT: mov v22.d[1], x15
+; CHECK-SD-NEXT: fcvtzs x15, s20
+; CHECK-SD-NEXT: fmov d20, x13
+; CHECK-SD-NEXT: fcvtzs x13, s3
+; CHECK-SD-NEXT: fmov d3, x14
+; CHECK-SD-NEXT: fcvtzs x14, s27
+; CHECK-SD-NEXT: fmov d27, x16
+; CHECK-SD-NEXT: frintx s21, s21
+; CHECK-SD-NEXT: mov h7, v7.h[3]
+; CHECK-SD-NEXT: frintx s1, s1
+; CHECK-SD-NEXT: fcvt s0, h0
+; CHECK-SD-NEXT: fcvt s23, h23
+; CHECK-SD-NEXT: fcvt s19, h19
+; CHECK-SD-NEXT: mov v27.d[1], x15
+; CHECK-SD-NEXT: fcvtzs x15, s25
+; CHECK-SD-NEXT: mov h25, v6.h[3]
+; CHECK-SD-NEXT: mov h6, v6.h[1]
+; CHECK-SD-NEXT: mov v3.d[1], x13
+; CHECK-SD-NEXT: fcvtzs x13, s21
+; CHECK-SD-NEXT: mov h21, v5.h[1]
+; CHECK-SD-NEXT: mov h5, v5.h[3]
+; CHECK-SD-NEXT: mov v20.d[1], x14
+; CHECK-SD-NEXT: fcvtzs x14, s1
+; CHECK-SD-NEXT: mov h1, v4.h[1]
+; CHECK-SD-NEXT: frintx s0, s0
+; CHECK-SD-NEXT: fcvt s25, h25
+; CHECK-SD-NEXT: fcvt s7, h7
+; CHECK-SD-NEXT: stp q3, q27, [x8, #192]
+; CHECK-SD-NEXT: fcvt s6, h6
+; CHECK-SD-NEXT: mov h3, v4.h[3]
+; CHECK-SD-NEXT: stp q22, q20, [x8, #128]
+; CHECK-SD-NEXT: fcvt s21, h21
+; CHECK-SD-NEXT: fcvt s5, h5
+; CHECK-SD-NEXT: mov v24.d[1], x13
+; CHECK-SD-NEXT: mov v26.d[1], x14
+; CHECK-SD-NEXT: fcvt s4, h4
+; CHECK-SD-NEXT: frintx s22, s25
+; CHECK-SD-NEXT: fmov d20, x12
+; CHECK-SD-NEXT: fcvt s1, h1
+; CHECK-SD-NEXT: frintx s6, s6
+; CHECK-SD-NEXT: fcvt s3, h3
+; CHECK-SD-NEXT: fcvtzs x12, s0
+; CHECK-SD-NEXT: frintx s5, s5
+; CHECK-SD-NEXT: frintx s21, s21
+; CHECK-SD-NEXT: fmov d0, x11
+; CHECK-SD-NEXT: stp q26, q24, [x8, #64]
+; CHECK-SD-NEXT: fmov d24, x15
+; CHECK-SD-NEXT: frintx s4, s4
+; CHECK-SD-NEXT: fcvtzs x11, s22
+; CHECK-SD-NEXT: frintx s22, s23
+; CHECK-SD-NEXT: frintx s1, s1
+; CHECK-SD-NEXT: fcvtzs x13, s6
+; CHECK-SD-NEXT: frintx s3, s3
+; CHECK-SD-NEXT: frintx s6, s7
+; CHECK-SD-NEXT: fcvtzs x14, s5
+; CHECK-SD-NEXT: mov v24.d[1], x12
+; CHECK-SD-NEXT: frintx s5, s19
+; CHECK-SD-NEXT: fcvtzs x12, s21
+; CHECK-SD-NEXT: mov v0.d[1], x10
+; CHECK-SD-NEXT: fcvtzs x10, s4
+; CHECK-SD-NEXT: mov v20.d[1], x11
+; CHECK-SD-NEXT: fcvtzs x11, s22
+; CHECK-SD-NEXT: mov v2.d[1], x13
+; CHECK-SD-NEXT: fcvtzs x15, s3
+; CHECK-SD-NEXT: fcvtzs x13, s1
+; CHECK-SD-NEXT: mov v18.d[1], x14
+; CHECK-SD-NEXT: fcvtzs x14, s6
+; CHECK-SD-NEXT: stp q0, q24, [x8]
+; CHECK-SD-NEXT: mov v17.d[1], x12
+; CHECK-SD-NEXT: fcvtzs x12, s5
+; CHECK-SD-NEXT: fmov d0, x10
+; CHECK-SD-NEXT: fmov d1, x11
+; CHECK-SD-NEXT: stp q2, q20, [x8, #224]
+; CHECK-SD-NEXT: fmov d2, x9
+; CHECK-SD-NEXT: mov v16.d[1], x15
+; CHECK-SD-NEXT: stp q17, q18, [x8, #160]
+; CHECK-SD-NEXT: mov v0.d[1], x13
+; CHECK-SD-NEXT: mov v1.d[1], x14
+; CHECK-SD-NEXT: mov v2.d[1], x12
+; CHECK-SD-NEXT: stp q0, q16, [x8, #96]
+; CHECK-SD-NEXT: stp q2, q1, [x8, #32]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v32i64_v32f16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtl v4.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: fcvtl v5.4s, v1.4h
+; CHECK-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-GI-NEXT: fcvtl v6.4s, v2.4h
+; CHECK-GI-NEXT: fcvtl2 v2.4s, v2.8h
+; CHECK-GI-NEXT: fcvtl v7.4s, v3.4h
+; CHECK-GI-NEXT: fcvtl2 v3.4s, v3.8h
+; CHECK-GI-NEXT: frintx v4.4s, v4.4s
+; CHECK-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-GI-NEXT: frintx v5.4s, v5.4s
+; CHECK-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-GI-NEXT: frintx v6.4s, v6.4s
+; CHECK-GI-NEXT: frintx v2.4s, v2.4s
+; CHECK-GI-NEXT: frintx v7.4s, v7.4s
+; CHECK-GI-NEXT: frintx v3.4s, v3.4s
+; CHECK-GI-NEXT: fcvtn v4.4h, v4.4s
+; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-GI-NEXT: fcvtn v5.4h, v5.4s
+; CHECK-GI-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-GI-NEXT: fcvtn v6.4h, v6.4s
+; CHECK-GI-NEXT: fcvtn v2.4h, v2.4s
+; CHECK-GI-NEXT: fcvtn v7.4h, v7.4s
+; CHECK-GI-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-GI-NEXT: fcvtl v4.4s, v4.4h
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl v5.4s, v5.4h
+; CHECK-GI-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-GI-NEXT: fcvtl v6.4s, v6.4h
+; CHECK-GI-NEXT: fcvtl v2.4s, v2.4h
+; CHECK-GI-NEXT: fcvtl v7.4s, v7.4h
+; CHECK-GI-NEXT: fcvtl v3.4s, v3.4h
+; CHECK-GI-NEXT: fcvtl v16.2d, v4.2s
+; CHECK-GI-NEXT: fcvtl2 v4.2d, v4.4s
+; CHECK-GI-NEXT: fcvtl v17.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-GI-NEXT: fcvtl v18.2d, v5.2s
+; CHECK-GI-NEXT: fcvtl2 v5.2d, v5.4s
+; CHECK-GI-NEXT: fcvtl v19.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-GI-NEXT: fcvtl v20.2d, v6.2s
+; CHECK-GI-NEXT: fcvtl2 v6.2d, v6.4s
+; CHECK-GI-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-GI-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: fcvtzs v18.2d, v18.2d
+; CHECK-GI-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-GI-NEXT: stp q16, q4, [x8]
+; CHECK-GI-NEXT: fcvtzs v16.2d, v19.2d
+; CHECK-GI-NEXT: fcvtl v4.2d, v2.2s
+; CHECK-GI-NEXT: stp q17, q0, [x8, #32]
+; CHECK-GI-NEXT: fcvtl2 v2.2d, v2.4s
+; CHECK-GI-NEXT: fcvtl v0.2d, v7.2s
+; CHECK-GI-NEXT: stp q18, q5, [x8, #64]
+; CHECK-GI-NEXT: fcvtl2 v5.2d, v7.4s
+; CHECK-GI-NEXT: fcvtl v7.2d, v3.2s
+; CHECK-GI-NEXT: fcvtzs v17.2d, v20.2d
+; CHECK-GI-NEXT: stp q16, q1, [x8, #96]
+; CHECK-GI-NEXT: fcvtl2 v1.2d, v3.4s
+; CHECK-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: fcvtzs v3.2d, v5.2d
+; CHECK-GI-NEXT: fcvtzs v5.2d, v7.2d
+; CHECK-GI-NEXT: stp q17, q6, [x8, #128]
+; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-NEXT: stp q4, q2, [x8, #160]
+; CHECK-GI-NEXT: stp q0, q3, [x8, #192]
+; CHECK-GI-NEXT: stp q5, q1, [x8, #224]
+; CHECK-GI-NEXT: ret
%a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x)
ret <32 x i64> %a
}
declare <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half>)
define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) nounwind {
-; CHECK-LABEL: llrint_v1i64_v1f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: frintx s0, s0
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v1i64_v1f32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: frintx s0, s0
+; CHECK-SD-NEXT: fcvtzs x8, s0
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v1i64_v1f32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: frintx s0, s0
+; CHECK-GI-NEXT: fcvtzs x8, s0
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ret
%a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x)
ret <1 x i64> %a
}
@@ -396,149 +558,248 @@ define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) nounwind {
declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>)
define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) nounwind {
-; CHECK-LABEL: llrint_v4i64_v4f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: frintx v0.2s, v0.2s
-; CHECK-NEXT: frintx v1.2s, v1.2s
-; CHECK-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-NEXT: fcvtl v1.2d, v1.2s
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v4i64_v4f32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: frintx v0.2s, v0.2s
+; CHECK-SD-NEXT: frintx v1.2s, v1.2s
+; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v4i64_v4f32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-GI-NEXT: fcvtzs v0.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-GI-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)
ret <4 x i64> %a
}
declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>)
define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) nounwind {
-; CHECK-LABEL: llrint_v8i64_v8f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: frintx v0.2s, v0.2s
-; CHECK-NEXT: frintx v1.2s, v1.2s
-; CHECK-NEXT: frintx v2.2s, v2.2s
-; CHECK-NEXT: frintx v3.2s, v3.2s
-; CHECK-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-NEXT: fcvtl v1.2d, v1.2s
-; CHECK-NEXT: fcvtl v4.2d, v2.2s
-; CHECK-NEXT: fcvtl v3.2d, v3.2s
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: fcvtzs v2.2d, v1.2d
-; CHECK-NEXT: fcvtzs v1.2d, v4.2d
-; CHECK-NEXT: fcvtzs v3.2d, v3.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v8i64_v8f32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: frintx v0.2s, v0.2s
+; CHECK-SD-NEXT: frintx v1.2s, v1.2s
+; CHECK-SD-NEXT: frintx v2.2s, v2.2s
+; CHECK-SD-NEXT: frintx v3.2s, v3.2s
+; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s
+; CHECK-SD-NEXT: fcvtl v4.2d, v2.2s
+; CHECK-SD-NEXT: fcvtl v3.2d, v3.2s
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: fcvtzs v2.2d, v1.2d
+; CHECK-SD-NEXT: fcvtzs v1.2d, v4.2d
+; CHECK-SD-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v8i64_v8f32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v3.2d, v0.4s
+; CHECK-GI-NEXT: fcvtl v4.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v5.2d, v1.4s
+; CHECK-GI-NEXT: fcvtzs v0.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v3.2d
+; CHECK-GI-NEXT: fcvtzs v2.2d, v4.2d
+; CHECK-GI-NEXT: fcvtzs v3.2d, v5.2d
+; CHECK-GI-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)
ret <8 x i64> %a
}
declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)
define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) nounwind {
-; CHECK-LABEL: llrint_v16i64_v16f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: ext v5.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v6.16b, v2.16b, v2.16b, #8
-; CHECK-NEXT: ext v7.16b, v3.16b, v3.16b, #8
-; CHECK-NEXT: frintx v0.2s, v0.2s
-; CHECK-NEXT: frintx v1.2s, v1.2s
-; CHECK-NEXT: frintx v2.2s, v2.2s
-; CHECK-NEXT: frintx v3.2s, v3.2s
-; CHECK-NEXT: frintx v5.2s, v5.2s
-; CHECK-NEXT: frintx v4.2s, v4.2s
-; CHECK-NEXT: frintx v6.2s, v6.2s
-; CHECK-NEXT: frintx v7.2s, v7.2s
-; CHECK-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-NEXT: fcvtl v1.2d, v1.2s
-; CHECK-NEXT: fcvtl v16.2d, v2.2s
-; CHECK-NEXT: fcvtl v18.2d, v3.2s
-; CHECK-NEXT: fcvtl v5.2d, v5.2s
-; CHECK-NEXT: fcvtl v17.2d, v4.2s
-; CHECK-NEXT: fcvtl v19.2d, v6.2s
-; CHECK-NEXT: fcvtl v7.2d, v7.2s
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: fcvtzs v2.2d, v1.2d
-; CHECK-NEXT: fcvtzs v4.2d, v16.2d
-; CHECK-NEXT: fcvtzs v6.2d, v18.2d
-; CHECK-NEXT: fcvtzs v1.2d, v5.2d
-; CHECK-NEXT: fcvtzs v3.2d, v17.2d
-; CHECK-NEXT: fcvtzs v5.2d, v19.2d
-; CHECK-NEXT: fcvtzs v7.2d, v7.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v16i64_v16f32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v4.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: ext v5.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: ext v6.16b, v2.16b, v2.16b, #8
+; CHECK-SD-NEXT: ext v7.16b, v3.16b, v3.16b, #8
+; CHECK-SD-NEXT: frintx v0.2s, v0.2s
+; CHECK-SD-NEXT: frintx v1.2s, v1.2s
+; CHECK-SD-NEXT: frintx v2.2s, v2.2s
+; CHECK-SD-NEXT: frintx v3.2s, v3.2s
+; CHECK-SD-NEXT: frintx v5.2s, v5.2s
+; CHECK-SD-NEXT: frintx v4.2s, v4.2s
+; CHECK-SD-NEXT: frintx v6.2s, v6.2s
+; CHECK-SD-NEXT: frintx v7.2s, v7.2s
+; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s
+; CHECK-SD-NEXT: fcvtl v16.2d, v2.2s
+; CHECK-SD-NEXT: fcvtl v18.2d, v3.2s
+; CHECK-SD-NEXT: fcvtl v5.2d, v5.2s
+; CHECK-SD-NEXT: fcvtl v17.2d, v4.2s
+; CHECK-SD-NEXT: fcvtl v19.2d, v6.2s
+; CHECK-SD-NEXT: fcvtl v7.2d, v7.2s
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: fcvtzs v2.2d, v1.2d
+; CHECK-SD-NEXT: fcvtzs v4.2d, v16.2d
+; CHECK-SD-NEXT: fcvtzs v6.2d, v18.2d
+; CHECK-SD-NEXT: fcvtzs v1.2d, v5.2d
+; CHECK-SD-NEXT: fcvtzs v3.2d, v17.2d
+; CHECK-SD-NEXT: fcvtzs v5.2d, v19.2d
+; CHECK-SD-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v16i64_v16f32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-GI-NEXT: frintx v2.4s, v2.4s
+; CHECK-GI-NEXT: frintx v3.4s, v3.4s
+; CHECK-GI-NEXT: fcvtl v4.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v5.2d, v0.4s
+; CHECK-GI-NEXT: fcvtl v6.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v7.2d, v1.4s
+; CHECK-GI-NEXT: fcvtl v16.2d, v2.2s
+; CHECK-GI-NEXT: fcvtl2 v17.2d, v2.4s
+; CHECK-GI-NEXT: fcvtl v18.2d, v3.2s
+; CHECK-GI-NEXT: fcvtl2 v19.2d, v3.4s
+; CHECK-GI-NEXT: fcvtzs v0.2d, v4.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v5.2d
+; CHECK-GI-NEXT: fcvtzs v2.2d, v6.2d
+; CHECK-GI-NEXT: fcvtzs v3.2d, v7.2d
+; CHECK-GI-NEXT: fcvtzs v4.2d, v16.2d
+; CHECK-GI-NEXT: fcvtzs v5.2d, v17.2d
+; CHECK-GI-NEXT: fcvtzs v6.2d, v18.2d
+; CHECK-GI-NEXT: fcvtzs v7.2d, v19.2d
+; CHECK-GI-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)
ret <16 x i64> %a
}
declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)
define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) nounwind {
-; CHECK-LABEL: llrint_v32i64_v32f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext v16.16b, v7.16b, v7.16b, #8
-; CHECK-NEXT: ext v17.16b, v6.16b, v6.16b, #8
-; CHECK-NEXT: frintx v7.2s, v7.2s
-; CHECK-NEXT: frintx v6.2s, v6.2s
-; CHECK-NEXT: ext v18.16b, v5.16b, v5.16b, #8
-; CHECK-NEXT: ext v21.16b, v4.16b, v4.16b, #8
-; CHECK-NEXT: ext v22.16b, v2.16b, v2.16b, #8
-; CHECK-NEXT: frintx v5.2s, v5.2s
-; CHECK-NEXT: ext v23.16b, v3.16b, v3.16b, #8
-; CHECK-NEXT: frintx v4.2s, v4.2s
-; CHECK-NEXT: ext v19.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: ext v20.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT: frintx v16.2s, v16.2s
-; CHECK-NEXT: frintx v17.2s, v17.2s
-; CHECK-NEXT: fcvtl v7.2d, v7.2s
-; CHECK-NEXT: fcvtl v6.2d, v6.2s
-; CHECK-NEXT: frintx v18.2s, v18.2s
-; CHECK-NEXT: frintx v21.2s, v21.2s
-; CHECK-NEXT: frintx v2.2s, v2.2s
-; CHECK-NEXT: frintx v3.2s, v3.2s
-; CHECK-NEXT: fcvtl v5.2d, v5.2s
-; CHECK-NEXT: frintx v23.2s, v23.2s
-; CHECK-NEXT: fcvtl v4.2d, v4.2s
-; CHECK-NEXT: frintx v1.2s, v1.2s
-; CHECK-NEXT: fcvtl v16.2d, v16.2s
-; CHECK-NEXT: fcvtl v17.2d, v17.2s
-; CHECK-NEXT: fcvtzs v7.2d, v7.2d
-; CHECK-NEXT: fcvtzs v6.2d, v6.2d
-; CHECK-NEXT: fcvtl v18.2d, v18.2s
-; CHECK-NEXT: fcvtl v21.2d, v21.2s
-; CHECK-NEXT: frintx v20.2s, v20.2s
-; CHECK-NEXT: fcvtl v3.2d, v3.2s
-; CHECK-NEXT: fcvtzs v5.2d, v5.2d
-; CHECK-NEXT: frintx v0.2s, v0.2s
-; CHECK-NEXT: fcvtl v2.2d, v2.2s
-; CHECK-NEXT: fcvtzs v4.2d, v4.2d
-; CHECK-NEXT: fcvtzs v16.2d, v16.2d
-; CHECK-NEXT: fcvtzs v17.2d, v17.2d
-; CHECK-NEXT: fcvtl v1.2d, v1.2s
-; CHECK-NEXT: fcvtzs v3.2d, v3.2d
-; CHECK-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-NEXT: fcvtzs v2.2d, v2.2d
-; CHECK-NEXT: stp q6, q17, [x8, #192]
-; CHECK-NEXT: fcvtl v6.2d, v23.2s
-; CHECK-NEXT: frintx v17.2s, v19.2s
-; CHECK-NEXT: stp q7, q16, [x8, #224]
-; CHECK-NEXT: frintx v7.2s, v22.2s
-; CHECK-NEXT: fcvtzs v16.2d, v18.2d
-; CHECK-NEXT: fcvtzs v18.2d, v21.2d
-; CHECK-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: fcvtzs v6.2d, v6.2d
-; CHECK-NEXT: stp q5, q16, [x8, #160]
-; CHECK-NEXT: fcvtl v7.2d, v7.2s
-; CHECK-NEXT: fcvtl v5.2d, v20.2s
-; CHECK-NEXT: stp q4, q18, [x8, #128]
-; CHECK-NEXT: fcvtl v4.2d, v17.2s
-; CHECK-NEXT: stp q3, q6, [x8, #96]
-; CHECK-NEXT: fcvtzs v7.2d, v7.2d
-; CHECK-NEXT: fcvtzs v3.2d, v5.2d
-; CHECK-NEXT: stp q1, q3, [x8, #32]
-; CHECK-NEXT: stp q2, q7, [x8, #64]
-; CHECK-NEXT: fcvtzs v2.2d, v4.2d
-; CHECK-NEXT: stp q0, q2, [x8]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v32i64_v32f32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v16.16b, v7.16b, v7.16b, #8
+; CHECK-SD-NEXT: ext v17.16b, v6.16b, v6.16b, #8
+; CHECK-SD-NEXT: frintx v7.2s, v7.2s
+; CHECK-SD-NEXT: frintx v6.2s, v6.2s
+; CHECK-SD-NEXT: ext v18.16b, v5.16b, v5.16b, #8
+; CHECK-SD-NEXT: ext v21.16b, v4.16b, v4.16b, #8
+; CHECK-SD-NEXT: ext v22.16b, v2.16b, v2.16b, #8
+; CHECK-SD-NEXT: frintx v5.2s, v5.2s
+; CHECK-SD-NEXT: ext v23.16b, v3.16b, v3.16b, #8
+; CHECK-SD-NEXT: frintx v4.2s, v4.2s
+; CHECK-SD-NEXT: ext v19.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: ext v20.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: frintx v16.2s, v16.2s
+; CHECK-SD-NEXT: frintx v17.2s, v17.2s
+; CHECK-SD-NEXT: fcvtl v7.2d, v7.2s
+; CHECK-SD-NEXT: fcvtl v6.2d, v6.2s
+; CHECK-SD-NEXT: frintx v18.2s, v18.2s
+; CHECK-SD-NEXT: frintx v21.2s, v21.2s
+; CHECK-SD-NEXT: frintx v2.2s, v2.2s
+; CHECK-SD-NEXT: frintx v3.2s, v3.2s
+; CHECK-SD-NEXT: fcvtl v5.2d, v5.2s
+; CHECK-SD-NEXT: frintx v23.2s, v23.2s
+; CHECK-SD-NEXT: fcvtl v4.2d, v4.2s
+; CHECK-SD-NEXT: frintx v1.2s, v1.2s
+; CHECK-SD-NEXT: fcvtl v16.2d, v16.2s
+; CHECK-SD-NEXT: fcvtl v17.2d, v17.2s
+; CHECK-SD-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-SD-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-SD-NEXT: fcvtl v18.2d, v18.2s
+; CHECK-SD-NEXT: fcvtl v21.2d, v21.2s
+; CHECK-SD-NEXT: frintx v20.2s, v20.2s
+; CHECK-SD-NEXT: fcvtl v3.2d, v3.2s
+; CHECK-SD-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-SD-NEXT: frintx v0.2s, v0.2s
+; CHECK-SD-NEXT: fcvtl v2.2d, v2.2s
+; CHECK-SD-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-SD-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-SD-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s
+; CHECK-SD-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-SD-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-SD-NEXT: stp q6, q17, [x8, #192]
+; CHECK-SD-NEXT: fcvtl v6.2d, v23.2s
+; CHECK-SD-NEXT: frintx v17.2s, v19.2s
+; CHECK-SD-NEXT: stp q7, q16, [x8, #224]
+; CHECK-SD-NEXT: frintx v7.2s, v22.2s
+; CHECK-SD-NEXT: fcvtzs v16.2d, v18.2d
+; CHECK-SD-NEXT: fcvtzs v18.2d, v21.2d
+; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-SD-NEXT: stp q5, q16, [x8, #160]
+; CHECK-SD-NEXT: fcvtl v7.2d, v7.2s
+; CHECK-SD-NEXT: fcvtl v5.2d, v20.2s
+; CHECK-SD-NEXT: stp q4, q18, [x8, #128]
+; CHECK-SD-NEXT: fcvtl v4.2d, v17.2s
+; CHECK-SD-NEXT: stp q3, q6, [x8, #96]
+; CHECK-SD-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-SD-NEXT: fcvtzs v3.2d, v5.2d
+; CHECK-SD-NEXT: stp q1, q3, [x8, #32]
+; CHECK-SD-NEXT: stp q2, q7, [x8, #64]
+; CHECK-SD-NEXT: fcvtzs v2.2d, v4.2d
+; CHECK-SD-NEXT: stp q0, q2, [x8]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v32i64_v32f32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-GI-NEXT: frintx v2.4s, v2.4s
+; CHECK-GI-NEXT: frintx v3.4s, v3.4s
+; CHECK-GI-NEXT: frintx v4.4s, v4.4s
+; CHECK-GI-NEXT: frintx v5.4s, v5.4s
+; CHECK-GI-NEXT: frintx v6.4s, v6.4s
+; CHECK-GI-NEXT: frintx v7.4s, v7.4s
+; CHECK-GI-NEXT: fcvtl v16.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-GI-NEXT: fcvtl v17.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-GI-NEXT: fcvtl v18.2d, v2.2s
+; CHECK-GI-NEXT: fcvtl2 v2.2d, v2.4s
+; CHECK-GI-NEXT: fcvtl v19.2d, v3.2s
+; CHECK-GI-NEXT: fcvtl2 v3.2d, v3.4s
+; CHECK-GI-NEXT: fcvtl v20.2d, v4.2s
+; CHECK-GI-NEXT: fcvtl2 v4.2d, v4.4s
+; CHECK-GI-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzs v18.2d, v18.2d
+; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-GI-NEXT: stp q16, q0, [x8]
+; CHECK-GI-NEXT: fcvtl v0.2d, v5.2s
+; CHECK-GI-NEXT: fcvtzs v16.2d, v19.2d
+; CHECK-GI-NEXT: stp q17, q1, [x8, #32]
+; CHECK-GI-NEXT: fcvtl2 v5.2d, v5.4s
+; CHECK-GI-NEXT: fcvtl v1.2d, v6.2s
+; CHECK-GI-NEXT: stp q18, q2, [x8, #64]
+; CHECK-GI-NEXT: fcvtzs v17.2d, v20.2d
+; CHECK-GI-NEXT: fcvtl2 v2.2d, v6.4s
+; CHECK-GI-NEXT: fcvtl v6.2d, v7.2s
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: stp q16, q3, [x8, #96]
+; CHECK-GI-NEXT: fcvtl2 v3.2d, v7.4s
+; CHECK-GI-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-NEXT: stp q17, q4, [x8, #128]
+; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v4.2d, v6.2d
+; CHECK-GI-NEXT: stp q0, q5, [x8, #160]
+; CHECK-GI-NEXT: fcvtzs v0.2d, v3.2d
+; CHECK-GI-NEXT: stp q1, q2, [x8, #192]
+; CHECK-GI-NEXT: stp q4, q0, [x8, #224]
+; CHECK-GI-NEXT: ret
%a = call <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float> %x)
ret <32 x i64> %a
}
@@ -623,53 +884,101 @@ define <16 x i64> @llrint_v16f64(<16 x double> %x) nounwind {
declare <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double>)
define <32 x i64> @llrint_v32f64(<32 x double> %x) nounwind {
-; CHECK-LABEL: llrint_v32f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldp q17, q16, [sp, #96]
-; CHECK-NEXT: frintx v7.2d, v7.2d
-; CHECK-NEXT: ldp q19, q18, [sp, #64]
-; CHECK-NEXT: frintx v6.2d, v6.2d
-; CHECK-NEXT: ldp q21, q20, [sp, #32]
-; CHECK-NEXT: frintx v5.2d, v5.2d
-; CHECK-NEXT: frintx v16.2d, v16.2d
-; CHECK-NEXT: frintx v17.2d, v17.2d
-; CHECK-NEXT: frintx v4.2d, v4.2d
-; CHECK-NEXT: frintx v18.2d, v18.2d
-; CHECK-NEXT: frintx v19.2d, v19.2d
-; CHECK-NEXT: frintx v3.2d, v3.2d
-; CHECK-NEXT: ldp q23, q22, [sp]
-; CHECK-NEXT: frintx v20.2d, v20.2d
-; CHECK-NEXT: frintx v21.2d, v21.2d
-; CHECK-NEXT: frintx v2.2d, v2.2d
-; CHECK-NEXT: frintx v1.2d, v1.2d
-; CHECK-NEXT: fcvtzs v16.2d, v16.2d
-; CHECK-NEXT: fcvtzs v17.2d, v17.2d
-; CHECK-NEXT: frintx v0.2d, v0.2d
-; CHECK-NEXT: frintx v22.2d, v22.2d
-; CHECK-NEXT: fcvtzs v18.2d, v18.2d
-; CHECK-NEXT: frintx v23.2d, v23.2d
-; CHECK-NEXT: fcvtzs v19.2d, v19.2d
-; CHECK-NEXT: fcvtzs v20.2d, v20.2d
-; CHECK-NEXT: fcvtzs v7.2d, v7.2d
-; CHECK-NEXT: fcvtzs v6.2d, v6.2d
-; CHECK-NEXT: fcvtzs v5.2d, v5.2d
-; CHECK-NEXT: fcvtzs v4.2d, v4.2d
-; CHECK-NEXT: stp q17, q16, [x8, #224]
-; CHECK-NEXT: fcvtzs v16.2d, v21.2d
-; CHECK-NEXT: fcvtzs v3.2d, v3.2d
-; CHECK-NEXT: fcvtzs v17.2d, v22.2d
-; CHECK-NEXT: fcvtzs v2.2d, v2.2d
-; CHECK-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-NEXT: stp q19, q18, [x8, #192]
-; CHECK-NEXT: fcvtzs v18.2d, v23.2d
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: stp q4, q5, [x8, #64]
-; CHECK-NEXT: stp q6, q7, [x8, #96]
-; CHECK-NEXT: stp q2, q3, [x8, #32]
-; CHECK-NEXT: stp q0, q1, [x8]
-; CHECK-NEXT: stp q18, q17, [x8, #128]
-; CHECK-NEXT: stp q16, q20, [x8, #160]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v32f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldp q17, q16, [sp, #96]
+; CHECK-SD-NEXT: frintx v7.2d, v7.2d
+; CHECK-SD-NEXT: ldp q19, q18, [sp, #64]
+; CHECK-SD-NEXT: frintx v6.2d, v6.2d
+; CHECK-SD-NEXT: ldp q21, q20, [sp, #32]
+; CHECK-SD-NEXT: frintx v5.2d, v5.2d
+; CHECK-SD-NEXT: frintx v16.2d, v16.2d
+; CHECK-SD-NEXT: frintx v17.2d, v17.2d
+; CHECK-SD-NEXT: frintx v4.2d, v4.2d
+; CHECK-SD-NEXT: frintx v18.2d, v18.2d
+; CHECK-SD-NEXT: frintx v19.2d, v19.2d
+; CHECK-SD-NEXT: frintx v3.2d, v3.2d
+; CHECK-SD-NEXT: ldp q23, q22, [sp]
+; CHECK-SD-NEXT: frintx v20.2d, v20.2d
+; CHECK-SD-NEXT: frintx v21.2d, v21.2d
+; CHECK-SD-NEXT: frintx v2.2d, v2.2d
+; CHECK-SD-NEXT: frintx v1.2d, v1.2d
+; CHECK-SD-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-SD-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-SD-NEXT: frintx v0.2d, v0.2d
+; CHECK-SD-NEXT: frintx v22.2d, v22.2d
+; CHECK-SD-NEXT: fcvtzs v18.2d, v18.2d
+; CHECK-SD-NEXT: frintx v23.2d, v23.2d
+; CHECK-SD-NEXT: fcvtzs v19.2d, v19.2d
+; CHECK-SD-NEXT: fcvtzs v20.2d, v20.2d
+; CHECK-SD-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-SD-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-SD-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-SD-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-SD-NEXT: stp q17, q16, [x8, #224]
+; CHECK-SD-NEXT: fcvtzs v16.2d, v21.2d
+; CHECK-SD-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-SD-NEXT: fcvtzs v17.2d, v22.2d
+; CHECK-SD-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-SD-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-SD-NEXT: stp q19, q18, [x8, #192]
+; CHECK-SD-NEXT: fcvtzs v18.2d, v23.2d
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: stp q4, q5, [x8, #64]
+; CHECK-SD-NEXT: stp q6, q7, [x8, #96]
+; CHECK-SD-NEXT: stp q2, q3, [x8, #32]
+; CHECK-SD-NEXT: stp q0, q1, [x8]
+; CHECK-SD-NEXT: stp q18, q17, [x8, #128]
+; CHECK-SD-NEXT: stp q16, q20, [x8, #160]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v32f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: frintx v0.2d, v0.2d
+; CHECK-GI-NEXT: frintx v1.2d, v1.2d
+; CHECK-GI-NEXT: frintx v2.2d, v2.2d
+; CHECK-GI-NEXT: frintx v3.2d, v3.2d
+; CHECK-GI-NEXT: ldp q16, q17, [sp]
+; CHECK-GI-NEXT: frintx v4.2d, v4.2d
+; CHECK-GI-NEXT: frintx v5.2d, v5.2d
+; CHECK-GI-NEXT: frintx v6.2d, v6.2d
+; CHECK-GI-NEXT: frintx v7.2d, v7.2d
+; CHECK-GI-NEXT: ldp q18, q19, [sp, #32]
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-GI-NEXT: ldp q20, q21, [sp, #64]
+; CHECK-GI-NEXT: frintx v16.2d, v16.2d
+; CHECK-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-GI-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-GI-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-GI-NEXT: ldp q22, q23, [sp, #96]
+; CHECK-GI-NEXT: stp q0, q1, [x8]
+; CHECK-GI-NEXT: frintx v0.2d, v17.2d
+; CHECK-GI-NEXT: frintx v1.2d, v18.2d
+; CHECK-GI-NEXT: stp q2, q3, [x8, #32]
+; CHECK-GI-NEXT: frintx v2.2d, v19.2d
+; CHECK-GI-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-GI-NEXT: frintx v3.2d, v20.2d
+; CHECK-GI-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-GI-NEXT: stp q4, q5, [x8, #64]
+; CHECK-GI-NEXT: frintx v4.2d, v21.2d
+; CHECK-GI-NEXT: frintx v5.2d, v22.2d
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-NEXT: stp q6, q7, [x8, #96]
+; CHECK-GI-NEXT: frintx v6.2d, v23.2d
+; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-GI-NEXT: stp q16, q0, [x8, #128]
+; CHECK-GI-NEXT: fcvtzs v0.2d, v5.2d
+; CHECK-GI-NEXT: stp q1, q2, [x8, #160]
+; CHECK-GI-NEXT: fcvtzs v1.2d, v6.2d
+; CHECK-GI-NEXT: stp q3, q4, [x8, #192]
+; CHECK-GI-NEXT: stp q0, q1, [x8, #224]
+; CHECK-GI-NEXT: ret
%a = call <32 x i64> @llvm.llrint.v32i64.v16f64(<32 x double> %x)
ret <32 x i64> %a
}
@@ -689,230 +998,510 @@ define <1 x i64> @llrint_v1i64_v1f128(<1 x fp128> %x) nounwind {
declare <1 x i64> @llvm.llrint.v1i64.v1f128(<1 x fp128>)
define <2 x i64> @llrint_v2i64_v2f128(<2 x fp128> %x) nounwind {
-; CHECK-LABEL: llrint_v2i64_v2f128:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v2i64_v2f128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Spill
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v2i64_v2f128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #48
+; CHECK-GI-NEXT: stp x30, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: fmov d0, x19
+; CHECK-GI-NEXT: ldp x30, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.d[1], x0
+; CHECK-GI-NEXT: add sp, sp, #48
+; CHECK-GI-NEXT: ret
%a = call <2 x i64> @llvm.llrint.v2i64.v2f128(<2 x fp128> %x)
ret <2 x i64> %a
}
declare <2 x i64> @llvm.llrint.v2i64.v2f128(<2 x fp128>)
define <4 x i64> @llrint_v4i64_v4f128(<4 x fp128> %x) nounwind {
-; CHECK-LABEL: llrint_v4i64_v4f128:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-NEXT: stp q3, q2, [sp, #32] // 32-byte Folded Spill
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d1, x0
-; CHECK-NEXT: ldp q0, q4, [sp, #16] // 32-byte Folded Reload
-; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
-; CHECK-NEXT: mov v1.d[1], v4.d[0]
-; CHECK-NEXT: add sp, sp, #80
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v4i64_v4f128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #80
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-SD-NEXT: stp q3, q2, [sp, #32] // 32-byte Folded Spill
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d1, x0
+; CHECK-SD-NEXT: ldp q0, q4, [sp, #16] // 32-byte Folded Reload
+; CHECK-SD-NEXT: ldr x30, [sp, #64] // 8-byte Reload
+; CHECK-SD-NEXT: mov v1.d[1], v4.d[0]
+; CHECK-SD-NEXT: add sp, sp, #80
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v4i64_v4f128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #96
+; CHECK-GI-NEXT: stp x30, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp q2, q1, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: str q3, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: mov x20, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: mov x21, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: fmov d0, x19
+; CHECK-GI-NEXT: fmov d1, x21
+; CHECK-GI-NEXT: ldp x30, x21, [sp, #64] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v1.d[1], x0
+; CHECK-GI-NEXT: add sp, sp, #96
+; CHECK-GI-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f128(<4 x fp128> %x)
ret <4 x i64> %a
}
declare <4 x i64> @llvm.llrint.v4i64.v4f128(<4 x fp128>)
define <8 x i64> @llrint_v8i64_v8f128(<8 x fp128> %x) nounwind {
-; CHECK-LABEL: llrint_v8i64_v8f128:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #144
-; CHECK-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: str x30, [sp, #128] // 8-byte Spill
-; CHECK-NEXT: stp q3, q2, [sp, #16] // 32-byte Folded Spill
-; CHECK-NEXT: stp q5, q4, [sp, #48] // 32-byte Folded Spill
-; CHECK-NEXT: stp q7, q6, [sp, #96] // 32-byte Folded Spill
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #80] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #80] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #80] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #64] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #112] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d3, x0
-; CHECK-NEXT: ldp q0, q1, [sp, #80] // 32-byte Folded Reload
-; CHECK-NEXT: ldr q2, [sp, #64] // 16-byte Reload
-; CHECK-NEXT: ldr x30, [sp, #128] // 8-byte Reload
-; CHECK-NEXT: mov v3.d[1], v1.d[0]
-; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Reload
-; CHECK-NEXT: add sp, sp, #144
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v8i64_v8f128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #144
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: str x30, [sp, #128] // 8-byte Spill
+; CHECK-SD-NEXT: stp q3, q2, [sp, #16] // 32-byte Folded Spill
+; CHECK-SD-NEXT: stp q5, q4, [sp, #48] // 32-byte Folded Spill
+; CHECK-SD-NEXT: stp q7, q6, [sp, #96] // 32-byte Folded Spill
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #80] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d3, x0
+; CHECK-SD-NEXT: ldp q0, q1, [sp, #80] // 32-byte Folded Reload
+; CHECK-SD-NEXT: ldr q2, [sp, #64] // 16-byte Reload
+; CHECK-SD-NEXT: ldr x30, [sp, #128] // 8-byte Reload
+; CHECK-SD-NEXT: mov v3.d[1], v1.d[0]
+; CHECK-SD-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-SD-NEXT: add sp, sp, #144
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v8i64_v8f128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #192
+; CHECK-GI-NEXT: stp x30, x25, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x24, x23, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #160] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp q6, q5, [sp] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q4, q3, [sp, #32] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q2, q1, [sp, #64] // 32-byte Folded Spill
+; CHECK-GI-NEXT: str q7, [sp, #112] // 16-byte Spill
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: mov x20, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: mov x21, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: mov x22, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: mov x23, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-GI-NEXT: mov x24, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-GI-NEXT: mov x25, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: fmov d0, x19
+; CHECK-GI-NEXT: fmov d1, x21
+; CHECK-GI-NEXT: fmov d2, x23
+; CHECK-GI-NEXT: fmov d3, x25
+; CHECK-GI-NEXT: ldp x30, x25, [sp, #128] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.d[1], x20
+; CHECK-GI-NEXT: mov v1.d[1], x22
+; CHECK-GI-NEXT: mov v2.d[1], x24
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v3.d[1], x0
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x24, x23, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: add sp, sp, #192
+; CHECK-GI-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f128(<8 x fp128> %x)
ret <8 x i64> %a
}
declare <8 x i64> @llvm.llrint.v8i64.v8f128(<8 x fp128>)
define <16 x i64> @llrint_v16f128(<16 x fp128> %x) nounwind {
-; CHECK-LABEL: llrint_v16f128:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #272
-; CHECK-NEXT: str q2, [sp, #160] // 16-byte Spill
-; CHECK-NEXT: ldr q2, [sp, #368]
-; CHECK-NEXT: stp q0, q3, [sp] // 32-byte Folded Spill
-; CHECK-NEXT: mov v0.16b, v1.16b
-; CHECK-NEXT: str q2, [sp, #240] // 16-byte Spill
-; CHECK-NEXT: ldr q2, [sp, #384]
-; CHECK-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
-; CHECK-NEXT: str q2, [sp, #224] // 16-byte Spill
-; CHECK-NEXT: ldr q2, [sp, #336]
-; CHECK-NEXT: stp q5, q7, [sp, #32] // 32-byte Folded Spill
-; CHECK-NEXT: str q2, [sp, #192] // 16-byte Spill
-; CHECK-NEXT: ldr q2, [sp, #352]
-; CHECK-NEXT: str q2, [sp, #176] // 16-byte Spill
-; CHECK-NEXT: ldr q2, [sp, #304]
-; CHECK-NEXT: str q2, [sp, #144] // 16-byte Spill
-; CHECK-NEXT: ldr q2, [sp, #320]
-; CHECK-NEXT: stp q4, q2, [sp, #112] // 32-byte Folded Spill
-; CHECK-NEXT: ldr q2, [sp, #272]
-; CHECK-NEXT: stp q6, q2, [sp, #80] // 32-byte Folded Spill
-; CHECK-NEXT: ldr q2, [sp, #288]
-; CHECK-NEXT: str q2, [sp, #64] // 16-byte Spill
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #208] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #208] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #208] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #160] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #160] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #112] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #112] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #80] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #64] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #64] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #128] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #128] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #144] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #128] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #144] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #176] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #176] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #192] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ldr q1, [sp, #176] // 16-byte Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: str q0, [sp, #192] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #224] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: str q0, [sp, #224] // 16-byte Spill
-; CHECK-NEXT: ldr q0, [sp, #240] // 16-byte Reload
-; CHECK-NEXT: bl llrintl
-; CHECK-NEXT: fmov d7, x0
-; CHECK-NEXT: ldp q0, q1, [sp, #208] // 32-byte Folded Reload
-; CHECK-NEXT: ldp q4, q2, [sp, #96] // 32-byte Folded Reload
-; CHECK-NEXT: ldr q3, [sp, #80] // 16-byte Reload
-; CHECK-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
-; CHECK-NEXT: ldr q6, [sp, #192] // 16-byte Reload
-; CHECK-NEXT: mov v7.d[1], v1.d[0]
-; CHECK-NEXT: ldp q5, q1, [sp, #144] // 32-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #272
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: llrint_v16f128:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #272
+; CHECK-SD-NEXT: str q2, [sp, #160] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q2, [sp, #368]
+; CHECK-SD-NEXT: stp q0, q3, [sp] // 32-byte Folded Spill
+; CHECK-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NEXT: str q2, [sp, #240] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q2, [sp, #384]
+; CHECK-SD-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
+; CHECK-SD-NEXT: str q2, [sp, #224] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q2, [sp, #336]
+; CHECK-SD-NEXT: stp q5, q7, [sp, #32] // 32-byte Folded Spill
+; CHECK-SD-NEXT: str q2, [sp, #192] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q2, [sp, #352]
+; CHECK-SD-NEXT: str q2, [sp, #176] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q2, [sp, #304]
+; CHECK-SD-NEXT: str q2, [sp, #144] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q2, [sp, #320]
+; CHECK-SD-NEXT: stp q4, q2, [sp, #112] // 32-byte Folded Spill
+; CHECK-SD-NEXT: ldr q2, [sp, #272]
+; CHECK-SD-NEXT: stp q6, q2, [sp, #80] // 32-byte Folded Spill
+; CHECK-SD-NEXT: ldr q2, [sp, #288]
+; CHECK-SD-NEXT: str q2, [sp, #64] // 16-byte Spill
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #208] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #160] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #160] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #128] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #128] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #144] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #128] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #144] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #176] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #176] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: ldr q1, [sp, #176] // 16-byte Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: str q0, [sp, #192] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: str q0, [sp, #224] // 16-byte Spill
+; CHECK-SD-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-SD-NEXT: bl llrintl
+; CHECK-SD-NEXT: fmov d7, x0
+; CHECK-SD-NEXT: ldp q0, q1, [sp, #208] // 32-byte Folded Reload
+; CHECK-SD-NEXT: ldp q4, q2, [sp, #96] // 32-byte Folded Reload
+; CHECK-SD-NEXT: ldr q3, [sp, #80] // 16-byte Reload
+; CHECK-SD-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldr q6, [sp, #192] // 16-byte Reload
+; CHECK-SD-NEXT: mov v7.d[1], v1.d[0]
+; CHECK-SD-NEXT: ldp q5, q1, [sp, #144] // 32-byte Folded Reload
+; CHECK-SD-NEXT: add sp, sp, #272
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: llrint_v16f128:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #384
+; CHECK-GI-NEXT: stp q6, q5, [sp, #160] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q4, q3, [sp, #192] // 32-byte Folded Spill
+; CHECK-GI-NEXT: stp q2, q1, [sp, #224] // 32-byte Folded Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #384]
+; CHECK-GI-NEXT: stp x29, x30, [sp, #288] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp q1, q7, [sp, #128] // 32-byte Folded Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #400]
+; CHECK-GI-NEXT: stp x28, x27, [sp, #304] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str q1, [sp, #112] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #416]
+; CHECK-GI-NEXT: stp x26, x25, [sp, #320] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str q1, [sp, #96] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #432]
+; CHECK-GI-NEXT: stp x24, x23, [sp, #336] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #448]
+; CHECK-GI-NEXT: stp x22, x21, [sp, #352] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #464]
+; CHECK-GI-NEXT: stp x20, x19, [sp, #368] // 16-byte Folded Spill
+; CHECK-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #480]
+; CHECK-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q1, [sp, #496]
+; CHECK-GI-NEXT: str q1, [sp, #272] // 16-byte Spill
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #256] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #240] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #224] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #208] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #192] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #176] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #176] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #160] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #160] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #144] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #144] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #128] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #128] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #272] // 16-byte Reload
+; CHECK-GI-NEXT: bl rintl
+; CHECK-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-GI-NEXT: ldr q0, [sp, #256] // 16-byte Reload
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-GI-NEXT: str x0, [sp, #256] // 8-byte Spill
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-GI-NEXT: str x0, [sp, #272] // 8-byte Spill
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #208] // 16-byte Reload
+; CHECK-GI-NEXT: str x0, [sp, #240] // 8-byte Spill
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-GI-NEXT: str x0, [sp, #224] // 8-byte Spill
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #176] // 16-byte Reload
+; CHECK-GI-NEXT: mov x24, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #160] // 16-byte Reload
+; CHECK-GI-NEXT: mov x23, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #144] // 16-byte Reload
+; CHECK-GI-NEXT: mov x25, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #128] // 16-byte Reload
+; CHECK-GI-NEXT: mov x26, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-GI-NEXT: mov x27, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-GI-NEXT: mov x28, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-GI-NEXT: mov x29, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-GI-NEXT: mov x20, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-GI-NEXT: mov x21, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-GI-NEXT: mov x22, x0
+; CHECK-GI-NEXT: bl __fixtfdi
+; CHECK-GI-NEXT: fmov d2, x24
+; CHECK-GI-NEXT: fmov d3, x25
+; CHECK-GI-NEXT: ldr d0, [sp, #256] // 8-byte Reload
+; CHECK-GI-NEXT: fmov d4, x27
+; CHECK-GI-NEXT: fmov d5, x29
+; CHECK-GI-NEXT: ldr x8, [sp, #272] // 8-byte Reload
+; CHECK-GI-NEXT: fmov d6, x20
+; CHECK-GI-NEXT: fmov d7, x22
+; CHECK-GI-NEXT: ldr d1, [sp, #240] // 8-byte Reload
+; CHECK-GI-NEXT: mov v0.d[1], x8
+; CHECK-GI-NEXT: ldr x8, [sp, #224] // 8-byte Reload
+; CHECK-GI-NEXT: mov v2.d[1], x23
+; CHECK-GI-NEXT: mov v3.d[1], x26
+; CHECK-GI-NEXT: mov v4.d[1], x28
+; CHECK-GI-NEXT: mov v5.d[1], x19
+; CHECK-GI-NEXT: mov v6.d[1], x21
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #368] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #352] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v1.d[1], x8
+; CHECK-GI-NEXT: ldp x24, x23, [sp, #336] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v7.d[1], x0
+; CHECK-GI-NEXT: ldp x26, x25, [sp, #320] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x28, x27, [sp, #304] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload
+; CHECK-GI-NEXT: add sp, sp, #384
+; CHECK-GI-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f128(<16 x fp128> %x)
ret <16 x i64> %a
}
diff --git a/llvm/test/CodeGen/AArch64/vector-lrint.ll b/llvm/test/CodeGen/AArch64/vector-lrint.ll
index 305f8cd67a044..6abed634d9c7c 100644
--- a/llvm/test/CodeGen/AArch64/vector-lrint.ll
+++ b/llvm/test/CodeGen/AArch64/vector-lrint.ll
@@ -10,51 +10,6 @@
; RUN: -global-isel -global-isel-abort=2 2>&1 |\
; RUN: FileCheck %s --check-prefixes=CHECK-i64,CHECK-i64-GI
-; CHECK-i32-GI: warning: Instruction selection used fallback path for lrint_v2f16
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f16
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f16
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16f16
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32f16
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f32
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f32
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f32
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16f32
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32f32
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f64
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f64
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f64
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16f64
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32f64
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v1fp128
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2fp128
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4fp128
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8fp128
-; CHECK-i32-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16fp128
-;
-; CHECK-i64-GI: warning: Instruction selection used fallback path for lrint_v2f16
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f16
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f16
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16f16
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32f16
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f32
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f32
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f32
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16f32
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32f32
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f64
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f64
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f64
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16f64
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32f64
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2fp128
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4fp128
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8fp128
-; CHECK-i64-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16fp128
-;
-;
-;
-
-
define <1 x iXLen> @lrint_v1f16(<1 x half> %x) nounwind {
; CHECK-i32-LABEL: lrint_v1f16:
; CHECK-i32: // %bb.0:
@@ -77,682 +32,936 @@ define <1 x iXLen> @lrint_v1f16(<1 x half> %x) nounwind {
declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half>)
define <2 x iXLen> @lrint_v2f16(<2 x half> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v2f16:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-i32-NEXT: mov h1, v0.h[1]
-; CHECK-i32-NEXT: fcvt s0, h0
-; CHECK-i32-NEXT: fcvt s1, h1
-; CHECK-i32-NEXT: frintx s0, s0
-; CHECK-i32-NEXT: frintx s1, s1
-; CHECK-i32-NEXT: fcvtzs w8, s0
-; CHECK-i32-NEXT: fcvtzs w9, s1
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: mov v0.s[1], w9
-; CHECK-i32-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v2f16:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-i32-SD-NEXT: mov h1, v0.h[1]
+; CHECK-i32-SD-NEXT: fcvt s0, h0
+; CHECK-i32-SD-NEXT: fcvt s1, h1
+; CHECK-i32-SD-NEXT: frintx s0, s0
+; CHECK-i32-SD-NEXT: frintx s1, s1
+; CHECK-i32-SD-NEXT: fcvtzs w8, s0
+; CHECK-i32-SD-NEXT: fcvtzs w9, s1
+; CHECK-i32-SD-NEXT: fmov s0, w8
+; CHECK-i32-SD-NEXT: mov v0.s[1], w9
+; CHECK-i32-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-i32-SD-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v2f16:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-i64-NEXT: mov h1, v0.h[1]
-; CHECK-i64-NEXT: fcvt s0, h0
-; CHECK-i64-NEXT: fcvt s1, h1
-; CHECK-i64-NEXT: frintx s0, s0
-; CHECK-i64-NEXT: frintx s1, s1
-; CHECK-i64-NEXT: fcvtzs x8, s0
-; CHECK-i64-NEXT: fcvtzs x9, s1
-; CHECK-i64-NEXT: fmov d0, x8
-; CHECK-i64-NEXT: mov v0.d[1], x9
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v2f16:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-i64-SD-NEXT: mov h1, v0.h[1]
+; CHECK-i64-SD-NEXT: fcvt s0, h0
+; CHECK-i64-SD-NEXT: fcvt s1, h1
+; CHECK-i64-SD-NEXT: frintx s0, s0
+; CHECK-i64-SD-NEXT: frintx s1, s1
+; CHECK-i64-SD-NEXT: fcvtzs x8, s0
+; CHECK-i64-SD-NEXT: fcvtzs x9, s1
+; CHECK-i64-SD-NEXT: fmov d0, x8
+; CHECK-i64-SD-NEXT: mov v0.d[1], x9
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v2f16:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i32-GI-NEXT: frintx v0.2s, v0.2s
+; CHECK-i32-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-i32-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i32-GI-NEXT: fcvtzs v0.2s, v0.2s
+; CHECK-i32-GI-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v2f16:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i64-GI-NEXT: frintx v0.2s, v0.2s
+; CHECK-i64-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-i64-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i64-GI-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-GI-NEXT: ret
%a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half> %x)
ret <2 x iXLen> %a
}
declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half>)
define <4 x iXLen> @lrint_v4f16(<4 x half> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v4f16:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-i32-NEXT: mov h1, v0.h[1]
-; CHECK-i32-NEXT: fcvt s2, h0
-; CHECK-i32-NEXT: mov h3, v0.h[2]
-; CHECK-i32-NEXT: mov h0, v0.h[3]
-; CHECK-i32-NEXT: fcvt s1, h1
-; CHECK-i32-NEXT: frintx s2, s2
-; CHECK-i32-NEXT: fcvt s3, h3
-; CHECK-i32-NEXT: frintx s1, s1
-; CHECK-i32-NEXT: fcvtzs w8, s2
-; CHECK-i32-NEXT: fcvt s2, h0
-; CHECK-i32-NEXT: fcvtzs w9, s1
-; CHECK-i32-NEXT: frintx s1, s3
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: mov v0.s[1], w9
-; CHECK-i32-NEXT: fcvtzs w8, s1
-; CHECK-i32-NEXT: frintx s1, s2
-; CHECK-i32-NEXT: mov v0.s[2], w8
-; CHECK-i32-NEXT: fcvtzs w8, s1
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v4f16:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-i32-SD-NEXT: mov h1, v0.h[1]
+; CHECK-i32-SD-NEXT: fcvt s2, h0
+; CHECK-i32-SD-NEXT: mov h3, v0.h[2]
+; CHECK-i32-SD-NEXT: mov h0, v0.h[3]
+; CHECK-i32-SD-NEXT: fcvt s1, h1
+; CHECK-i32-SD-NEXT: frintx s2, s2
+; CHECK-i32-SD-NEXT: fcvt s3, h3
+; CHECK-i32-SD-NEXT: frintx s1, s1
+; CHECK-i32-SD-NEXT: fcvtzs w8, s2
+; CHECK-i32-SD-NEXT: fcvt s2, h0
+; CHECK-i32-SD-NEXT: fcvtzs w9, s1
+; CHECK-i32-SD-NEXT: frintx s1, s3
+; CHECK-i32-SD-NEXT: fmov s0, w8
+; CHECK-i32-SD-NEXT: mov v0.s[1], w9
+; CHECK-i32-SD-NEXT: fcvtzs w8, s1
+; CHECK-i32-SD-NEXT: frintx s1, s2
+; CHECK-i32-SD-NEXT: mov v0.s[2], w8
+; CHECK-i32-SD-NEXT: fcvtzs w8, s1
+; CHECK-i32-SD-NEXT: mov v0.s[3], w8
+; CHECK-i32-SD-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v4f16:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-i64-NEXT: mov h1, v0.h[2]
-; CHECK-i64-NEXT: mov h2, v0.h[1]
-; CHECK-i64-NEXT: mov h3, v0.h[3]
-; CHECK-i64-NEXT: fcvt s0, h0
-; CHECK-i64-NEXT: fcvt s1, h1
-; CHECK-i64-NEXT: fcvt s2, h2
-; CHECK-i64-NEXT: fcvt s3, h3
-; CHECK-i64-NEXT: frintx s0, s0
-; CHECK-i64-NEXT: frintx s1, s1
-; CHECK-i64-NEXT: frintx s2, s2
-; CHECK-i64-NEXT: frintx s3, s3
-; CHECK-i64-NEXT: fcvtzs x8, s0
-; CHECK-i64-NEXT: fcvtzs x9, s1
-; CHECK-i64-NEXT: fcvtzs x10, s2
-; CHECK-i64-NEXT: fcvtzs x11, s3
-; CHECK-i64-NEXT: fmov d0, x8
-; CHECK-i64-NEXT: fmov d1, x9
-; CHECK-i64-NEXT: mov v0.d[1], x10
-; CHECK-i64-NEXT: mov v1.d[1], x11
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v4f16:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-i64-SD-NEXT: mov h1, v0.h[2]
+; CHECK-i64-SD-NEXT: mov h2, v0.h[1]
+; CHECK-i64-SD-NEXT: mov h3, v0.h[3]
+; CHECK-i64-SD-NEXT: fcvt s0, h0
+; CHECK-i64-SD-NEXT: fcvt s1, h1
+; CHECK-i64-SD-NEXT: fcvt s2, h2
+; CHECK-i64-SD-NEXT: fcvt s3, h3
+; CHECK-i64-SD-NEXT: frintx s0, s0
+; CHECK-i64-SD-NEXT: frintx s1, s1
+; CHECK-i64-SD-NEXT: frintx s2, s2
+; CHECK-i64-SD-NEXT: frintx s3, s3
+; CHECK-i64-SD-NEXT: fcvtzs x8, s0
+; CHECK-i64-SD-NEXT: fcvtzs x9, s1
+; CHECK-i64-SD-NEXT: fcvtzs x10, s2
+; CHECK-i64-SD-NEXT: fcvtzs x11, s3
+; CHECK-i64-SD-NEXT: fmov d0, x8
+; CHECK-i64-SD-NEXT: fmov d1, x9
+; CHECK-i64-SD-NEXT: mov v0.d[1], x10
+; CHECK-i64-SD-NEXT: mov v1.d[1], x11
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v4f16:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i32-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i32-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-i32-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i32-GI-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-i32-GI-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v4f16:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i64-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i64-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-i64-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i64-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v1.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-i64-GI-NEXT: ret
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x)
ret <4 x iXLen> %a
}
declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half>)
define <8 x iXLen> @lrint_v8f16(<8 x half> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v8f16:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-i32-NEXT: mov h3, v0.h[1]
-; CHECK-i32-NEXT: fcvt s6, h0
-; CHECK-i32-NEXT: mov h4, v0.h[2]
-; CHECK-i32-NEXT: mov h0, v0.h[3]
-; CHECK-i32-NEXT: mov h2, v1.h[1]
-; CHECK-i32-NEXT: fcvt s5, h1
-; CHECK-i32-NEXT: mov h7, v1.h[2]
-; CHECK-i32-NEXT: fcvt s3, h3
-; CHECK-i32-NEXT: frintx s6, s6
-; CHECK-i32-NEXT: fcvt s4, h4
-; CHECK-i32-NEXT: mov h1, v1.h[3]
-; CHECK-i32-NEXT: fcvt s2, h2
-; CHECK-i32-NEXT: frintx s5, s5
-; CHECK-i32-NEXT: fcvt s7, h7
-; CHECK-i32-NEXT: frintx s3, s3
-; CHECK-i32-NEXT: fcvtzs w9, s6
-; CHECK-i32-NEXT: frintx s4, s4
-; CHECK-i32-NEXT: frintx s2, s2
-; CHECK-i32-NEXT: fcvtzs w8, s5
-; CHECK-i32-NEXT: fcvt s5, h1
-; CHECK-i32-NEXT: fcvtzs w11, s3
-; CHECK-i32-NEXT: fcvt s3, h0
-; CHECK-i32-NEXT: fmov s0, w9
-; CHECK-i32-NEXT: fcvtzs w12, s4
-; CHECK-i32-NEXT: fcvtzs w10, s2
-; CHECK-i32-NEXT: frintx s2, s7
-; CHECK-i32-NEXT: fmov s1, w8
-; CHECK-i32-NEXT: mov v0.s[1], w11
-; CHECK-i32-NEXT: fcvtzs w8, s2
-; CHECK-i32-NEXT: mov v1.s[1], w10
-; CHECK-i32-NEXT: frintx s2, s3
-; CHECK-i32-NEXT: frintx s3, s5
-; CHECK-i32-NEXT: mov v0.s[2], w12
-; CHECK-i32-NEXT: mov v1.s[2], w8
-; CHECK-i32-NEXT: fcvtzs w9, s2
-; CHECK-i32-NEXT: fcvtzs w8, s3
-; CHECK-i32-NEXT: mov v0.s[3], w9
-; CHECK-i32-NEXT: mov v1.s[3], w8
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v8f16:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-i32-SD-NEXT: mov h3, v0.h[1]
+; CHECK-i32-SD-NEXT: fcvt s6, h0
+; CHECK-i32-SD-NEXT: mov h4, v0.h[2]
+; CHECK-i32-SD-NEXT: mov h0, v0.h[3]
+; CHECK-i32-SD-NEXT: mov h2, v1.h[1]
+; CHECK-i32-SD-NEXT: fcvt s5, h1
+; CHECK-i32-SD-NEXT: mov h7, v1.h[2]
+; CHECK-i32-SD-NEXT: fcvt s3, h3
+; CHECK-i32-SD-NEXT: frintx s6, s6
+; CHECK-i32-SD-NEXT: fcvt s4, h4
+; CHECK-i32-SD-NEXT: mov h1, v1.h[3]
+; CHECK-i32-SD-NEXT: fcvt s2, h2
+; CHECK-i32-SD-NEXT: frintx s5, s5
+; CHECK-i32-SD-NEXT: fcvt s7, h7
+; CHECK-i32-SD-NEXT: frintx s3, s3
+; CHECK-i32-SD-NEXT: fcvtzs w9, s6
+; CHECK-i32-SD-NEXT: frintx s4, s4
+; CHECK-i32-SD-NEXT: frintx s2, s2
+; CHECK-i32-SD-NEXT: fcvtzs w8, s5
+; CHECK-i32-SD-NEXT: fcvt s5, h1
+; CHECK-i32-SD-NEXT: fcvtzs w11, s3
+; CHECK-i32-SD-NEXT: fcvt s3, h0
+; CHECK-i32-SD-NEXT: fmov s0, w9
+; CHECK-i32-SD-NEXT: fcvtzs w12, s4
+; CHECK-i32-SD-NEXT: fcvtzs w10, s2
+; CHECK-i32-SD-NEXT: frintx s2, s7
+; CHECK-i32-SD-NEXT: fmov s1, w8
+; CHECK-i32-SD-NEXT: mov v0.s[1], w11
+; CHECK-i32-SD-NEXT: fcvtzs w8, s2
+; CHECK-i32-SD-NEXT: mov v1.s[1], w10
+; CHECK-i32-SD-NEXT: frintx s2, s3
+; CHECK-i32-SD-NEXT: frintx s3, s5
+; CHECK-i32-SD-NEXT: mov v0.s[2], w12
+; CHECK-i32-SD-NEXT: mov v1.s[2], w8
+; CHECK-i32-SD-NEXT: fcvtzs w9, s2
+; CHECK-i32-SD-NEXT: fcvtzs w8, s3
+; CHECK-i32-SD-NEXT: mov v0.s[3], w9
+; CHECK-i32-SD-NEXT: mov v1.s[3], w8
+; CHECK-i32-SD-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v8f16:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-i64-NEXT: mov h4, v0.h[2]
-; CHECK-i64-NEXT: mov h3, v0.h[1]
-; CHECK-i64-NEXT: mov h7, v0.h[3]
-; CHECK-i64-NEXT: fcvt s0, h0
-; CHECK-i64-NEXT: mov h2, v1.h[2]
-; CHECK-i64-NEXT: mov h5, v1.h[1]
-; CHECK-i64-NEXT: mov h6, v1.h[3]
-; CHECK-i64-NEXT: fcvt s1, h1
-; CHECK-i64-NEXT: fcvt s4, h4
-; CHECK-i64-NEXT: fcvt s3, h3
-; CHECK-i64-NEXT: fcvt s7, h7
-; CHECK-i64-NEXT: frintx s0, s0
-; CHECK-i64-NEXT: fcvt s2, h2
-; CHECK-i64-NEXT: fcvt s5, h5
-; CHECK-i64-NEXT: fcvt s6, h6
-; CHECK-i64-NEXT: frintx s1, s1
-; CHECK-i64-NEXT: frintx s4, s4
-; CHECK-i64-NEXT: frintx s3, s3
-; CHECK-i64-NEXT: frintx s7, s7
-; CHECK-i64-NEXT: fcvtzs x9, s0
-; CHECK-i64-NEXT: frintx s2, s2
-; CHECK-i64-NEXT: frintx s5, s5
-; CHECK-i64-NEXT: frintx s6, s6
-; CHECK-i64-NEXT: fcvtzs x8, s1
-; CHECK-i64-NEXT: fcvtzs x12, s4
-; CHECK-i64-NEXT: fcvtzs x11, s3
-; CHECK-i64-NEXT: fcvtzs x15, s7
-; CHECK-i64-NEXT: fmov d0, x9
-; CHECK-i64-NEXT: fcvtzs x10, s2
-; CHECK-i64-NEXT: fcvtzs x13, s5
-; CHECK-i64-NEXT: fcvtzs x14, s6
-; CHECK-i64-NEXT: fmov d2, x8
-; CHECK-i64-NEXT: fmov d1, x12
-; CHECK-i64-NEXT: mov v0.d[1], x11
-; CHECK-i64-NEXT: fmov d3, x10
-; CHECK-i64-NEXT: mov v2.d[1], x13
-; CHECK-i64-NEXT: mov v1.d[1], x15
-; CHECK-i64-NEXT: mov v3.d[1], x14
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v8f16:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-i64-SD-NEXT: mov h4, v0.h[2]
+; CHECK-i64-SD-NEXT: mov h3, v0.h[1]
+; CHECK-i64-SD-NEXT: mov h7, v0.h[3]
+; CHECK-i64-SD-NEXT: fcvt s0, h0
+; CHECK-i64-SD-NEXT: mov h2, v1.h[2]
+; CHECK-i64-SD-NEXT: mov h5, v1.h[1]
+; CHECK-i64-SD-NEXT: mov h6, v1.h[3]
+; CHECK-i64-SD-NEXT: fcvt s1, h1
+; CHECK-i64-SD-NEXT: fcvt s4, h4
+; CHECK-i64-SD-NEXT: fcvt s3, h3
+; CHECK-i64-SD-NEXT: fcvt s7, h7
+; CHECK-i64-SD-NEXT: frintx s0, s0
+; CHECK-i64-SD-NEXT: fcvt s2, h2
+; CHECK-i64-SD-NEXT: fcvt s5, h5
+; CHECK-i64-SD-NEXT: fcvt s6, h6
+; CHECK-i64-SD-NEXT: frintx s1, s1
+; CHECK-i64-SD-NEXT: frintx s4, s4
+; CHECK-i64-SD-NEXT: frintx s3, s3
+; CHECK-i64-SD-NEXT: frintx s7, s7
+; CHECK-i64-SD-NEXT: fcvtzs x9, s0
+; CHECK-i64-SD-NEXT: frintx s2, s2
+; CHECK-i64-SD-NEXT: frintx s5, s5
+; CHECK-i64-SD-NEXT: frintx s6, s6
+; CHECK-i64-SD-NEXT: fcvtzs x8, s1
+; CHECK-i64-SD-NEXT: fcvtzs x12, s4
+; CHECK-i64-SD-NEXT: fcvtzs x11, s3
+; CHECK-i64-SD-NEXT: fcvtzs x15, s7
+; CHECK-i64-SD-NEXT: fmov d0, x9
+; CHECK-i64-SD-NEXT: fcvtzs x10, s2
+; CHECK-i64-SD-NEXT: fcvtzs x13, s5
+; CHECK-i64-SD-NEXT: fcvtzs x14, s6
+; CHECK-i64-SD-NEXT: fmov d2, x8
+; CHECK-i64-SD-NEXT: fmov d1, x12
+; CHECK-i64-SD-NEXT: mov v0.d[1], x11
+; CHECK-i64-SD-NEXT: fmov d3, x10
+; CHECK-i64-SD-NEXT: mov v2.d[1], x13
+; CHECK-i64-SD-NEXT: mov v1.d[1], x15
+; CHECK-i64-SD-NEXT: mov v3.d[1], x14
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v8f16:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-i32-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-i32-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-i32-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i32-GI-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-i32-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-i32-GI-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-i32-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-i32-GI-NEXT: fcvtzs v0.4s, v1.4s
+; CHECK-i32-GI-NEXT: fcvtzs v1.4s, v2.4s
+; CHECK-i32-GI-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v8f16:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-i64-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-i64-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-i64-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i64-GI-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-i64-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-i64-GI-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-i64-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i64-GI-NEXT: fcvtl v2.2d, v1.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-i64-GI-NEXT: fcvtl v3.2d, v0.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v4.2d, v0.4s
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v2.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i64-GI-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-i64-GI-NEXT: fcvtzs v3.2d, v4.2d
+; CHECK-i64-GI-NEXT: ret
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x)
ret <8 x iXLen> %a
}
declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half>)
define <16 x iXLen> @lrint_v16f16(<16 x half> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v16f16:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-i32-NEXT: ext v3.16b, v1.16b, v1.16b, #8
-; CHECK-i32-NEXT: mov h18, v0.h[1]
-; CHECK-i32-NEXT: mov h19, v1.h[1]
-; CHECK-i32-NEXT: fcvt s20, h0
-; CHECK-i32-NEXT: mov h21, v0.h[2]
-; CHECK-i32-NEXT: mov h0, v0.h[3]
-; CHECK-i32-NEXT: mov h4, v2.h[1]
-; CHECK-i32-NEXT: mov h5, v2.h[2]
-; CHECK-i32-NEXT: fcvt s6, h2
-; CHECK-i32-NEXT: fcvt s7, h3
-; CHECK-i32-NEXT: mov h16, v3.h[1]
-; CHECK-i32-NEXT: mov h17, v3.h[2]
-; CHECK-i32-NEXT: fcvt s18, h18
-; CHECK-i32-NEXT: fcvt s19, h19
-; CHECK-i32-NEXT: mov h2, v2.h[3]
-; CHECK-i32-NEXT: fcvt s4, h4
-; CHECK-i32-NEXT: fcvt s5, h5
-; CHECK-i32-NEXT: frintx s6, s6
-; CHECK-i32-NEXT: frintx s7, s7
-; CHECK-i32-NEXT: fcvt s16, h16
-; CHECK-i32-NEXT: fcvt s17, h17
-; CHECK-i32-NEXT: frintx s18, s18
-; CHECK-i32-NEXT: fcvt s2, h2
-; CHECK-i32-NEXT: frintx s4, s4
-; CHECK-i32-NEXT: frintx s5, s5
-; CHECK-i32-NEXT: fcvtzs w8, s6
-; CHECK-i32-NEXT: fcvt s6, h1
-; CHECK-i32-NEXT: fcvtzs w9, s7
-; CHECK-i32-NEXT: mov h7, v1.h[2]
-; CHECK-i32-NEXT: frintx s16, s16
-; CHECK-i32-NEXT: fcvtzs w15, s18
-; CHECK-i32-NEXT: fcvtzs w10, s4
-; CHECK-i32-NEXT: frintx s4, s17
-; CHECK-i32-NEXT: fcvtzs w11, s5
-; CHECK-i32-NEXT: frintx s5, s20
-; CHECK-i32-NEXT: fcvt s17, h21
-; CHECK-i32-NEXT: frintx s6, s6
-; CHECK-i32-NEXT: fcvtzs w12, s16
-; CHECK-i32-NEXT: frintx s16, s19
-; CHECK-i32-NEXT: fcvt s7, h7
-; CHECK-i32-NEXT: mov h19, v1.h[3]
-; CHECK-i32-NEXT: fmov s1, w8
-; CHECK-i32-NEXT: fcvtzs w13, s4
-; CHECK-i32-NEXT: mov h4, v3.h[3]
-; CHECK-i32-NEXT: fmov s3, w9
-; CHECK-i32-NEXT: fcvtzs w14, s5
-; CHECK-i32-NEXT: frintx s5, s17
-; CHECK-i32-NEXT: fcvtzs w16, s6
-; CHECK-i32-NEXT: fcvt s17, h0
-; CHECK-i32-NEXT: fcvtzs w8, s16
-; CHECK-i32-NEXT: frintx s6, s7
-; CHECK-i32-NEXT: fcvt s7, h19
-; CHECK-i32-NEXT: mov v1.s[1], w10
-; CHECK-i32-NEXT: mov v3.s[1], w12
-; CHECK-i32-NEXT: fcvt s4, h4
-; CHECK-i32-NEXT: fcvtzs w9, s5
-; CHECK-i32-NEXT: fmov s0, w14
-; CHECK-i32-NEXT: frintx s5, s2
-; CHECK-i32-NEXT: fmov s2, w16
-; CHECK-i32-NEXT: frintx s16, s17
-; CHECK-i32-NEXT: fcvtzs w10, s6
-; CHECK-i32-NEXT: frintx s6, s7
-; CHECK-i32-NEXT: mov v1.s[2], w11
-; CHECK-i32-NEXT: mov v3.s[2], w13
-; CHECK-i32-NEXT: mov v0.s[1], w15
-; CHECK-i32-NEXT: frintx s4, s4
-; CHECK-i32-NEXT: mov v2.s[1], w8
-; CHECK-i32-NEXT: fcvtzs w8, s5
-; CHECK-i32-NEXT: fcvtzs w12, s16
-; CHECK-i32-NEXT: mov v0.s[2], w9
-; CHECK-i32-NEXT: fcvtzs w9, s4
-; CHECK-i32-NEXT: mov v2.s[2], w10
-; CHECK-i32-NEXT: fcvtzs w10, s6
-; CHECK-i32-NEXT: mov v1.s[3], w8
-; CHECK-i32-NEXT: mov v0.s[3], w12
-; CHECK-i32-NEXT: mov v3.s[3], w9
-; CHECK-i32-NEXT: mov v2.s[3], w10
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v16f16:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-i32-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-i32-SD-NEXT: mov h18, v0.h[1]
+; CHECK-i32-SD-NEXT: mov h19, v1.h[1]
+; CHECK-i32-SD-NEXT: fcvt s20, h0
+; CHECK-i32-SD-NEXT: mov h21, v0.h[2]
+; CHECK-i32-SD-NEXT: mov h0, v0.h[3]
+; CHECK-i32-SD-NEXT: mov h4, v2.h[1]
+; CHECK-i32-SD-NEXT: mov h5, v2.h[2]
+; CHECK-i32-SD-NEXT: fcvt s6, h2
+; CHECK-i32-SD-NEXT: fcvt s7, h3
+; CHECK-i32-SD-NEXT: mov h16, v3.h[1]
+; CHECK-i32-SD-NEXT: mov h17, v3.h[2]
+; CHECK-i32-SD-NEXT: fcvt s18, h18
+; CHECK-i32-SD-NEXT: fcvt s19, h19
+; CHECK-i32-SD-NEXT: mov h2, v2.h[3]
+; CHECK-i32-SD-NEXT: fcvt s4, h4
+; CHECK-i32-SD-NEXT: fcvt s5, h5
+; CHECK-i32-SD-NEXT: frintx s6, s6
+; CHECK-i32-SD-NEXT: frintx s7, s7
+; CHECK-i32-SD-NEXT: fcvt s16, h16
+; CHECK-i32-SD-NEXT: fcvt s17, h17
+; CHECK-i32-SD-NEXT: frintx s18, s18
+; CHECK-i32-SD-NEXT: fcvt s2, h2
+; CHECK-i32-SD-NEXT: frintx s4, s4
+; CHECK-i32-SD-NEXT: frintx s5, s5
+; CHECK-i32-SD-NEXT: fcvtzs w8, s6
+; CHECK-i32-SD-NEXT: fcvt s6, h1
+; CHECK-i32-SD-NEXT: fcvtzs w9, s7
+; CHECK-i32-SD-NEXT: mov h7, v1.h[2]
+; CHECK-i32-SD-NEXT: frintx s16, s16
+; CHECK-i32-SD-NEXT: fcvtzs w15, s18
+; CHECK-i32-SD-NEXT: fcvtzs w10, s4
+; CHECK-i32-SD-NEXT: frintx s4, s17
+; CHECK-i32-SD-NEXT: fcvtzs w11, s5
+; CHECK-i32-SD-NEXT: frintx s5, s20
+; CHECK-i32-SD-NEXT: fcvt s17, h21
+; CHECK-i32-SD-NEXT: frintx s6, s6
+; CHECK-i32-SD-NEXT: fcvtzs w12, s16
+; CHECK-i32-SD-NEXT: frintx s16, s19
+; CHECK-i32-SD-NEXT: fcvt s7, h7
+; CHECK-i32-SD-NEXT: mov h19, v1.h[3]
+; CHECK-i32-SD-NEXT: fmov s1, w8
+; CHECK-i32-SD-NEXT: fcvtzs w13, s4
+; CHECK-i32-SD-NEXT: mov h4, v3.h[3]
+; CHECK-i32-SD-NEXT: fmov s3, w9
+; CHECK-i32-SD-NEXT: fcvtzs w14, s5
+; CHECK-i32-SD-NEXT: frintx s5, s17
+; CHECK-i32-SD-NEXT: fcvtzs w16, s6
+; CHECK-i32-SD-NEXT: fcvt s17, h0
+; CHECK-i32-SD-NEXT: fcvtzs w8, s16
+; CHECK-i32-SD-NEXT: frintx s6, s7
+; CHECK-i32-SD-NEXT: fcvt s7, h19
+; CHECK-i32-SD-NEXT: mov v1.s[1], w10
+; CHECK-i32-SD-NEXT: mov v3.s[1], w12
+; CHECK-i32-SD-NEXT: fcvt s4, h4
+; CHECK-i32-SD-NEXT: fcvtzs w9, s5
+; CHECK-i32-SD-NEXT: fmov s0, w14
+; CHECK-i32-SD-NEXT: frintx s5, s2
+; CHECK-i32-SD-NEXT: fmov s2, w16
+; CHECK-i32-SD-NEXT: frintx s16, s17
+; CHECK-i32-SD-NEXT: fcvtzs w10, s6
+; CHECK-i32-SD-NEXT: frintx s6, s7
+; CHECK-i32-SD-NEXT: mov v1.s[2], w11
+; CHECK-i32-SD-NEXT: mov v3.s[2], w13
+; CHECK-i32-SD-NEXT: mov v0.s[1], w15
+; CHECK-i32-SD-NEXT: frintx s4, s4
+; CHECK-i32-SD-NEXT: mov v2.s[1], w8
+; CHECK-i32-SD-NEXT: fcvtzs w8, s5
+; CHECK-i32-SD-NEXT: fcvtzs w12, s16
+; CHECK-i32-SD-NEXT: mov v0.s[2], w9
+; CHECK-i32-SD-NEXT: fcvtzs w9, s4
+; CHECK-i32-SD-NEXT: mov v2.s[2], w10
+; CHECK-i32-SD-NEXT: fcvtzs w10, s6
+; CHECK-i32-SD-NEXT: mov v1.s[3], w8
+; CHECK-i32-SD-NEXT: mov v0.s[3], w12
+; CHECK-i32-SD-NEXT: mov v3.s[3], w9
+; CHECK-i32-SD-NEXT: mov v2.s[3], w10
+; CHECK-i32-SD-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v16f16:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-i64-NEXT: ext v3.16b, v1.16b, v1.16b, #8
-; CHECK-i64-NEXT: mov h17, v0.h[1]
-; CHECK-i64-NEXT: mov h19, v0.h[2]
-; CHECK-i64-NEXT: fcvt s18, h0
-; CHECK-i64-NEXT: mov h0, v0.h[3]
-; CHECK-i64-NEXT: mov h4, v2.h[1]
-; CHECK-i64-NEXT: mov h5, v2.h[2]
-; CHECK-i64-NEXT: fcvt s7, h3
-; CHECK-i64-NEXT: fcvt s6, h2
-; CHECK-i64-NEXT: mov h16, v3.h[2]
-; CHECK-i64-NEXT: mov h2, v2.h[3]
-; CHECK-i64-NEXT: fcvt s17, h17
-; CHECK-i64-NEXT: fcvt s19, h19
-; CHECK-i64-NEXT: frintx s18, s18
-; CHECK-i64-NEXT: fcvt s0, h0
-; CHECK-i64-NEXT: fcvt s4, h4
-; CHECK-i64-NEXT: fcvt s5, h5
-; CHECK-i64-NEXT: frintx s7, s7
-; CHECK-i64-NEXT: frintx s6, s6
-; CHECK-i64-NEXT: fcvt s16, h16
-; CHECK-i64-NEXT: fcvt s2, h2
-; CHECK-i64-NEXT: frintx s17, s17
-; CHECK-i64-NEXT: frintx s19, s19
-; CHECK-i64-NEXT: fcvtzs x13, s18
-; CHECK-i64-NEXT: frintx s0, s0
-; CHECK-i64-NEXT: frintx s4, s4
-; CHECK-i64-NEXT: frintx s5, s5
-; CHECK-i64-NEXT: fcvtzs x9, s7
-; CHECK-i64-NEXT: mov h7, v1.h[2]
-; CHECK-i64-NEXT: fcvtzs x8, s6
-; CHECK-i64-NEXT: mov h6, v1.h[1]
-; CHECK-i64-NEXT: frintx s16, s16
-; CHECK-i64-NEXT: fcvtzs x14, s17
-; CHECK-i64-NEXT: fcvtzs x15, s19
-; CHECK-i64-NEXT: fcvtzs x10, s4
-; CHECK-i64-NEXT: mov h4, v3.h[1]
-; CHECK-i64-NEXT: fcvtzs x11, s5
-; CHECK-i64-NEXT: mov h5, v1.h[3]
-; CHECK-i64-NEXT: mov h3, v3.h[3]
-; CHECK-i64-NEXT: fcvt s1, h1
-; CHECK-i64-NEXT: fcvt s7, h7
-; CHECK-i64-NEXT: fcvt s6, h6
-; CHECK-i64-NEXT: fcvtzs x12, s16
-; CHECK-i64-NEXT: frintx s16, s2
-; CHECK-i64-NEXT: fmov d2, x8
-; CHECK-i64-NEXT: fcvt s4, h4
-; CHECK-i64-NEXT: fcvt s3, h3
-; CHECK-i64-NEXT: fcvt s5, h5
-; CHECK-i64-NEXT: frintx s1, s1
-; CHECK-i64-NEXT: frintx s7, s7
-; CHECK-i64-NEXT: frintx s17, s6
-; CHECK-i64-NEXT: fmov d6, x9
-; CHECK-i64-NEXT: mov v2.d[1], x10
-; CHECK-i64-NEXT: frintx s4, s4
-; CHECK-i64-NEXT: frintx s18, s3
-; CHECK-i64-NEXT: frintx s5, s5
-; CHECK-i64-NEXT: fcvtzs x8, s1
-; CHECK-i64-NEXT: fcvtzs x9, s7
-; CHECK-i64-NEXT: fmov d3, x11
-; CHECK-i64-NEXT: fcvtzs x11, s0
-; CHECK-i64-NEXT: fmov d7, x12
-; CHECK-i64-NEXT: fcvtzs x12, s16
-; CHECK-i64-NEXT: fcvtzs x16, s17
-; CHECK-i64-NEXT: fcvtzs x17, s4
-; CHECK-i64-NEXT: fmov d0, x13
-; CHECK-i64-NEXT: fmov d1, x15
-; CHECK-i64-NEXT: fcvtzs x18, s18
-; CHECK-i64-NEXT: fcvtzs x0, s5
-; CHECK-i64-NEXT: fmov d4, x8
-; CHECK-i64-NEXT: fmov d5, x9
-; CHECK-i64-NEXT: mov v0.d[1], x14
-; CHECK-i64-NEXT: mov v1.d[1], x11
-; CHECK-i64-NEXT: mov v3.d[1], x12
-; CHECK-i64-NEXT: mov v4.d[1], x16
-; CHECK-i64-NEXT: mov v6.d[1], x17
-; CHECK-i64-NEXT: mov v7.d[1], x18
-; CHECK-i64-NEXT: mov v5.d[1], x0
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v16f16:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-i64-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-i64-SD-NEXT: mov h17, v0.h[1]
+; CHECK-i64-SD-NEXT: mov h19, v0.h[2]
+; CHECK-i64-SD-NEXT: fcvt s18, h0
+; CHECK-i64-SD-NEXT: mov h0, v0.h[3]
+; CHECK-i64-SD-NEXT: mov h4, v2.h[1]
+; CHECK-i64-SD-NEXT: mov h5, v2.h[2]
+; CHECK-i64-SD-NEXT: fcvt s7, h3
+; CHECK-i64-SD-NEXT: fcvt s6, h2
+; CHECK-i64-SD-NEXT: mov h16, v3.h[2]
+; CHECK-i64-SD-NEXT: mov h2, v2.h[3]
+; CHECK-i64-SD-NEXT: fcvt s17, h17
+; CHECK-i64-SD-NEXT: fcvt s19, h19
+; CHECK-i64-SD-NEXT: frintx s18, s18
+; CHECK-i64-SD-NEXT: fcvt s0, h0
+; CHECK-i64-SD-NEXT: fcvt s4, h4
+; CHECK-i64-SD-NEXT: fcvt s5, h5
+; CHECK-i64-SD-NEXT: frintx s7, s7
+; CHECK-i64-SD-NEXT: frintx s6, s6
+; CHECK-i64-SD-NEXT: fcvt s16, h16
+; CHECK-i64-SD-NEXT: fcvt s2, h2
+; CHECK-i64-SD-NEXT: frintx s17, s17
+; CHECK-i64-SD-NEXT: frintx s19, s19
+; CHECK-i64-SD-NEXT: fcvtzs x13, s18
+; CHECK-i64-SD-NEXT: frintx s0, s0
+; CHECK-i64-SD-NEXT: frintx s4, s4
+; CHECK-i64-SD-NEXT: frintx s5, s5
+; CHECK-i64-SD-NEXT: fcvtzs x9, s7
+; CHECK-i64-SD-NEXT: mov h7, v1.h[2]
+; CHECK-i64-SD-NEXT: fcvtzs x8, s6
+; CHECK-i64-SD-NEXT: mov h6, v1.h[1]
+; CHECK-i64-SD-NEXT: frintx s16, s16
+; CHECK-i64-SD-NEXT: fcvtzs x14, s17
+; CHECK-i64-SD-NEXT: fcvtzs x15, s19
+; CHECK-i64-SD-NEXT: fcvtzs x10, s4
+; CHECK-i64-SD-NEXT: mov h4, v3.h[1]
+; CHECK-i64-SD-NEXT: fcvtzs x11, s5
+; CHECK-i64-SD-NEXT: mov h5, v1.h[3]
+; CHECK-i64-SD-NEXT: mov h3, v3.h[3]
+; CHECK-i64-SD-NEXT: fcvt s1, h1
+; CHECK-i64-SD-NEXT: fcvt s7, h7
+; CHECK-i64-SD-NEXT: fcvt s6, h6
+; CHECK-i64-SD-NEXT: fcvtzs x12, s16
+; CHECK-i64-SD-NEXT: frintx s16, s2
+; CHECK-i64-SD-NEXT: fmov d2, x8
+; CHECK-i64-SD-NEXT: fcvt s4, h4
+; CHECK-i64-SD-NEXT: fcvt s3, h3
+; CHECK-i64-SD-NEXT: fcvt s5, h5
+; CHECK-i64-SD-NEXT: frintx s1, s1
+; CHECK-i64-SD-NEXT: frintx s7, s7
+; CHECK-i64-SD-NEXT: frintx s17, s6
+; CHECK-i64-SD-NEXT: fmov d6, x9
+; CHECK-i64-SD-NEXT: mov v2.d[1], x10
+; CHECK-i64-SD-NEXT: frintx s4, s4
+; CHECK-i64-SD-NEXT: frintx s18, s3
+; CHECK-i64-SD-NEXT: frintx s5, s5
+; CHECK-i64-SD-NEXT: fcvtzs x8, s1
+; CHECK-i64-SD-NEXT: fcvtzs x9, s7
+; CHECK-i64-SD-NEXT: fmov d3, x11
+; CHECK-i64-SD-NEXT: fcvtzs x11, s0
+; CHECK-i64-SD-NEXT: fmov d7, x12
+; CHECK-i64-SD-NEXT: fcvtzs x12, s16
+; CHECK-i64-SD-NEXT: fcvtzs x16, s17
+; CHECK-i64-SD-NEXT: fcvtzs x17, s4
+; CHECK-i64-SD-NEXT: fmov d0, x13
+; CHECK-i64-SD-NEXT: fmov d1, x15
+; CHECK-i64-SD-NEXT: fcvtzs x18, s18
+; CHECK-i64-SD-NEXT: fcvtzs x0, s5
+; CHECK-i64-SD-NEXT: fmov d4, x8
+; CHECK-i64-SD-NEXT: fmov d5, x9
+; CHECK-i64-SD-NEXT: mov v0.d[1], x14
+; CHECK-i64-SD-NEXT: mov v1.d[1], x11
+; CHECK-i64-SD-NEXT: mov v3.d[1], x12
+; CHECK-i64-SD-NEXT: mov v4.d[1], x16
+; CHECK-i64-SD-NEXT: mov v6.d[1], x17
+; CHECK-i64-SD-NEXT: mov v7.d[1], x18
+; CHECK-i64-SD-NEXT: mov v5.d[1], x0
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v16f16:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-i32-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-i32-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-i32-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-i32-GI-NEXT: frintx v2.4s, v2.4s
+; CHECK-i32-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i32-GI-NEXT: frintx v3.4s, v3.4s
+; CHECK-i32-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-i32-GI-NEXT: fcvtn v2.4h, v2.4s
+; CHECK-i32-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-i32-GI-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-i32-GI-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-i32-GI-NEXT: fcvtl v2.4s, v2.4h
+; CHECK-i32-GI-NEXT: fcvtl v4.4s, v0.4h
+; CHECK-i32-GI-NEXT: fcvtl v3.4s, v3.4h
+; CHECK-i32-GI-NEXT: fcvtl v5.4s, v1.4h
+; CHECK-i32-GI-NEXT: fcvtzs v0.4s, v2.4s
+; CHECK-i32-GI-NEXT: fcvtzs v1.4s, v4.4s
+; CHECK-i32-GI-NEXT: fcvtzs v2.4s, v3.4s
+; CHECK-i32-GI-NEXT: fcvtzs v3.4s, v5.4s
+; CHECK-i32-GI-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v16f16:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-i64-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-i64-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-i64-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-i64-GI-NEXT: frintx v2.4s, v2.4s
+; CHECK-i64-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i64-GI-NEXT: frintx v3.4s, v3.4s
+; CHECK-i64-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-i64-GI-NEXT: fcvtn v2.4h, v2.4s
+; CHECK-i64-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-i64-GI-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-i64-GI-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-i64-GI-NEXT: fcvtl v2.4s, v2.4h
+; CHECK-i64-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i64-GI-NEXT: fcvtl v3.4s, v3.4h
+; CHECK-i64-GI-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-i64-GI-NEXT: fcvtl v4.2d, v2.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v2.2d, v2.4s
+; CHECK-i64-GI-NEXT: fcvtl v5.2d, v0.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v6.2d, v0.4s
+; CHECK-i64-GI-NEXT: fcvtl v7.2d, v3.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v16.2d, v3.4s
+; CHECK-i64-GI-NEXT: fcvtl v17.2d, v1.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v18.2d, v1.4s
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v4.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-i64-GI-NEXT: fcvtzs v2.2d, v5.2d
+; CHECK-i64-GI-NEXT: fcvtzs v3.2d, v6.2d
+; CHECK-i64-GI-NEXT: fcvtzs v4.2d, v7.2d
+; CHECK-i64-GI-NEXT: fcvtzs v5.2d, v16.2d
+; CHECK-i64-GI-NEXT: fcvtzs v6.2d, v17.2d
+; CHECK-i64-GI-NEXT: fcvtzs v7.2d, v18.2d
+; CHECK-i64-GI-NEXT: ret
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x)
ret <16 x iXLen> %a
}
declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half>)
define <32 x iXLen> @lrint_v32f16(<32 x half> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v32f16:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: ext v5.16b, v0.16b, v0.16b, #8
-; CHECK-i32-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-i32-NEXT: ext v17.16b, v2.16b, v2.16b, #8
-; CHECK-i32-NEXT: mov h6, v5.h[1]
-; CHECK-i32-NEXT: fcvt s7, h5
-; CHECK-i32-NEXT: mov h16, v5.h[2]
-; CHECK-i32-NEXT: mov h5, v5.h[3]
-; CHECK-i32-NEXT: mov h18, v4.h[1]
-; CHECK-i32-NEXT: mov h20, v4.h[3]
-; CHECK-i32-NEXT: mov h19, v4.h[2]
-; CHECK-i32-NEXT: fcvt s21, h4
-; CHECK-i32-NEXT: mov h23, v17.h[1]
-; CHECK-i32-NEXT: ext v4.16b, v3.16b, v3.16b, #8
-; CHECK-i32-NEXT: fcvt s22, h17
-; CHECK-i32-NEXT: fcvt s6, h6
-; CHECK-i32-NEXT: frintx s7, s7
-; CHECK-i32-NEXT: fcvt s16, h16
-; CHECK-i32-NEXT: fcvt s5, h5
-; CHECK-i32-NEXT: fcvt s18, h18
-; CHECK-i32-NEXT: fcvt s20, h20
-; CHECK-i32-NEXT: fcvt s19, h19
-; CHECK-i32-NEXT: frintx s22, s22
-; CHECK-i32-NEXT: frintx s6, s6
-; CHECK-i32-NEXT: fcvtzs w12, s7
-; CHECK-i32-NEXT: frintx s7, s16
-; CHECK-i32-NEXT: frintx s5, s5
-; CHECK-i32-NEXT: frintx s16, s21
-; CHECK-i32-NEXT: fcvt s21, h23
-; CHECK-i32-NEXT: frintx s18, s18
-; CHECK-i32-NEXT: frintx s20, s20
-; CHECK-i32-NEXT: frintx s19, s19
-; CHECK-i32-NEXT: fcvtzs w15, s22
-; CHECK-i32-NEXT: mov h22, v1.h[2]
-; CHECK-i32-NEXT: fcvtzs w17, s6
-; CHECK-i32-NEXT: mov h6, v17.h[2]
-; CHECK-i32-NEXT: mov h17, v17.h[3]
-; CHECK-i32-NEXT: fcvtzs w9, s7
-; CHECK-i32-NEXT: mov h7, v4.h[2]
-; CHECK-i32-NEXT: fcvtzs w8, s5
-; CHECK-i32-NEXT: mov h5, v4.h[1]
-; CHECK-i32-NEXT: fcvtzs w13, s16
-; CHECK-i32-NEXT: frintx s16, s21
-; CHECK-i32-NEXT: fcvtzs w14, s18
-; CHECK-i32-NEXT: fcvtzs w10, s20
-; CHECK-i32-NEXT: fcvt s18, h4
-; CHECK-i32-NEXT: fcvt s6, h6
-; CHECK-i32-NEXT: fcvt s17, h17
-; CHECK-i32-NEXT: mov h20, v0.h[2]
-; CHECK-i32-NEXT: fcvt s7, h7
-; CHECK-i32-NEXT: fcvtzs w11, s19
-; CHECK-i32-NEXT: mov h19, v0.h[1]
-; CHECK-i32-NEXT: fcvt s5, h5
-; CHECK-i32-NEXT: fcvtzs w0, s16
-; CHECK-i32-NEXT: mov h21, v1.h[1]
-; CHECK-i32-NEXT: frintx s18, s18
-; CHECK-i32-NEXT: mov h4, v4.h[3]
-; CHECK-i32-NEXT: frintx s6, s6
-; CHECK-i32-NEXT: frintx s16, s17
-; CHECK-i32-NEXT: mov h17, v0.h[3]
-; CHECK-i32-NEXT: fcvt s0, h0
-; CHECK-i32-NEXT: fcvt s19, h19
-; CHECK-i32-NEXT: frintx s5, s5
-; CHECK-i32-NEXT: fcvtzs w2, s18
-; CHECK-i32-NEXT: fcvt s18, h21
-; CHECK-i32-NEXT: fcvt s21, h2
-; CHECK-i32-NEXT: fcvtzs w18, s6
-; CHECK-i32-NEXT: frintx s6, s7
-; CHECK-i32-NEXT: fcvt s7, h20
-; CHECK-i32-NEXT: fcvtzs w16, s16
-; CHECK-i32-NEXT: fcvt s16, h17
-; CHECK-i32-NEXT: fcvt s17, h1
-; CHECK-i32-NEXT: frintx s0, s0
-; CHECK-i32-NEXT: fcvtzs w3, s5
-; CHECK-i32-NEXT: frintx s5, s19
-; CHECK-i32-NEXT: fcvt s19, h22
-; CHECK-i32-NEXT: mov h1, v1.h[3]
-; CHECK-i32-NEXT: fcvtzs w1, s6
-; CHECK-i32-NEXT: frintx s6, s7
-; CHECK-i32-NEXT: mov h7, v2.h[1]
-; CHECK-i32-NEXT: frintx s17, s17
-; CHECK-i32-NEXT: frintx s20, s16
-; CHECK-i32-NEXT: fmov s16, w12
-; CHECK-i32-NEXT: fcvtzs w4, s0
-; CHECK-i32-NEXT: frintx s0, s18
-; CHECK-i32-NEXT: fcvtzs w5, s5
-; CHECK-i32-NEXT: frintx s5, s19
-; CHECK-i32-NEXT: frintx s18, s21
-; CHECK-i32-NEXT: fcvt s19, h3
-; CHECK-i32-NEXT: fcvtzs w12, s6
-; CHECK-i32-NEXT: fcvt s6, h7
-; CHECK-i32-NEXT: mov h7, v3.h[1]
-; CHECK-i32-NEXT: fcvtzs w6, s17
-; CHECK-i32-NEXT: fmov s17, w13
-; CHECK-i32-NEXT: mov v16.s[1], w17
-; CHECK-i32-NEXT: fcvtzs w17, s20
-; CHECK-i32-NEXT: fcvtzs w7, s0
-; CHECK-i32-NEXT: mov h0, v2.h[2]
-; CHECK-i32-NEXT: mov h20, v3.h[2]
-; CHECK-i32-NEXT: fcvtzs w13, s5
-; CHECK-i32-NEXT: fmov s5, w15
-; CHECK-i32-NEXT: frintx s6, s6
-; CHECK-i32-NEXT: fcvt s7, h7
-; CHECK-i32-NEXT: mov v17.s[1], w14
-; CHECK-i32-NEXT: fcvtzs w14, s18
-; CHECK-i32-NEXT: frintx s18, s19
-; CHECK-i32-NEXT: mov h2, v2.h[3]
-; CHECK-i32-NEXT: fcvt s0, h0
-; CHECK-i32-NEXT: mov h3, v3.h[3]
-; CHECK-i32-NEXT: mov v5.s[1], w0
-; CHECK-i32-NEXT: fcvt s19, h20
-; CHECK-i32-NEXT: fcvt s1, h1
-; CHECK-i32-NEXT: mov v16.s[2], w9
-; CHECK-i32-NEXT: fcvtzs w15, s6
-; CHECK-i32-NEXT: frintx s6, s7
-; CHECK-i32-NEXT: fmov s7, w2
-; CHECK-i32-NEXT: fcvtzs w0, s18
-; CHECK-i32-NEXT: fcvt s20, h2
-; CHECK-i32-NEXT: fcvt s18, h4
-; CHECK-i32-NEXT: frintx s21, s0
-; CHECK-i32-NEXT: fcvt s3, h3
-; CHECK-i32-NEXT: fmov s0, w4
-; CHECK-i32-NEXT: frintx s19, s19
-; CHECK-i32-NEXT: fmov s2, w6
-; CHECK-i32-NEXT: fmov s4, w14
-; CHECK-i32-NEXT: fcvtzs w2, s6
-; CHECK-i32-NEXT: mov v7.s[1], w3
-; CHECK-i32-NEXT: frintx s1, s1
-; CHECK-i32-NEXT: fmov s6, w0
-; CHECK-i32-NEXT: mov v0.s[1], w5
-; CHECK-i32-NEXT: frintx s20, s20
-; CHECK-i32-NEXT: mov v2.s[1], w7
-; CHECK-i32-NEXT: fcvtzs w3, s21
-; CHECK-i32-NEXT: mov v4.s[1], w15
-; CHECK-i32-NEXT: fcvtzs w14, s19
-; CHECK-i32-NEXT: frintx s18, s18
-; CHECK-i32-NEXT: frintx s3, s3
-; CHECK-i32-NEXT: mov v6.s[1], w2
-; CHECK-i32-NEXT: mov v17.s[2], w11
-; CHECK-i32-NEXT: fcvtzs w15, s1
-; CHECK-i32-NEXT: fcvtzs w0, s20
-; CHECK-i32-NEXT: mov v5.s[2], w18
-; CHECK-i32-NEXT: mov v0.s[2], w12
-; CHECK-i32-NEXT: mov v7.s[2], w1
-; CHECK-i32-NEXT: mov v2.s[2], w13
-; CHECK-i32-NEXT: mov v4.s[2], w3
-; CHECK-i32-NEXT: fcvtzs w9, s18
-; CHECK-i32-NEXT: fcvtzs w11, s3
-; CHECK-i32-NEXT: mov v16.s[3], w8
-; CHECK-i32-NEXT: mov v6.s[2], w14
-; CHECK-i32-NEXT: mov v17.s[3], w10
-; CHECK-i32-NEXT: mov v0.s[3], w17
-; CHECK-i32-NEXT: mov v5.s[3], w16
-; CHECK-i32-NEXT: mov v2.s[3], w15
-; CHECK-i32-NEXT: mov v4.s[3], w0
-; CHECK-i32-NEXT: mov v7.s[3], w9
-; CHECK-i32-NEXT: mov v1.16b, v16.16b
-; CHECK-i32-NEXT: mov v6.s[3], w11
-; CHECK-i32-NEXT: mov v3.16b, v17.16b
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v32f16:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: ext v5.16b, v0.16b, v0.16b, #8
+; CHECK-i32-SD-NEXT: ext v4.16b, v1.16b, v1.16b, #8
+; CHECK-i32-SD-NEXT: ext v17.16b, v2.16b, v2.16b, #8
+; CHECK-i32-SD-NEXT: mov h6, v5.h[1]
+; CHECK-i32-SD-NEXT: fcvt s7, h5
+; CHECK-i32-SD-NEXT: mov h16, v5.h[2]
+; CHECK-i32-SD-NEXT: mov h5, v5.h[3]
+; CHECK-i32-SD-NEXT: mov h18, v4.h[1]
+; CHECK-i32-SD-NEXT: mov h20, v4.h[3]
+; CHECK-i32-SD-NEXT: mov h19, v4.h[2]
+; CHECK-i32-SD-NEXT: fcvt s21, h4
+; CHECK-i32-SD-NEXT: mov h23, v17.h[1]
+; CHECK-i32-SD-NEXT: ext v4.16b, v3.16b, v3.16b, #8
+; CHECK-i32-SD-NEXT: fcvt s22, h17
+; CHECK-i32-SD-NEXT: fcvt s6, h6
+; CHECK-i32-SD-NEXT: frintx s7, s7
+; CHECK-i32-SD-NEXT: fcvt s16, h16
+; CHECK-i32-SD-NEXT: fcvt s5, h5
+; CHECK-i32-SD-NEXT: fcvt s18, h18
+; CHECK-i32-SD-NEXT: fcvt s20, h20
+; CHECK-i32-SD-NEXT: fcvt s19, h19
+; CHECK-i32-SD-NEXT: frintx s22, s22
+; CHECK-i32-SD-NEXT: frintx s6, s6
+; CHECK-i32-SD-NEXT: fcvtzs w12, s7
+; CHECK-i32-SD-NEXT: frintx s7, s16
+; CHECK-i32-SD-NEXT: frintx s5, s5
+; CHECK-i32-SD-NEXT: frintx s16, s21
+; CHECK-i32-SD-NEXT: fcvt s21, h23
+; CHECK-i32-SD-NEXT: frintx s18, s18
+; CHECK-i32-SD-NEXT: frintx s20, s20
+; CHECK-i32-SD-NEXT: frintx s19, s19
+; CHECK-i32-SD-NEXT: fcvtzs w15, s22
+; CHECK-i32-SD-NEXT: mov h22, v1.h[2]
+; CHECK-i32-SD-NEXT: fcvtzs w17, s6
+; CHECK-i32-SD-NEXT: mov h6, v17.h[2]
+; CHECK-i32-SD-NEXT: mov h17, v17.h[3]
+; CHECK-i32-SD-NEXT: fcvtzs w9, s7
+; CHECK-i32-SD-NEXT: mov h7, v4.h[2]
+; CHECK-i32-SD-NEXT: fcvtzs w8, s5
+; CHECK-i32-SD-NEXT: mov h5, v4.h[1]
+; CHECK-i32-SD-NEXT: fcvtzs w13, s16
+; CHECK-i32-SD-NEXT: frintx s16, s21
+; CHECK-i32-SD-NEXT: fcvtzs w14, s18
+; CHECK-i32-SD-NEXT: fcvtzs w10, s20
+; CHECK-i32-SD-NEXT: fcvt s18, h4
+; CHECK-i32-SD-NEXT: fcvt s6, h6
+; CHECK-i32-SD-NEXT: fcvt s17, h17
+; CHECK-i32-SD-NEXT: mov h20, v0.h[2]
+; CHECK-i32-SD-NEXT: fcvt s7, h7
+; CHECK-i32-SD-NEXT: fcvtzs w11, s19
+; CHECK-i32-SD-NEXT: mov h19, v0.h[1]
+; CHECK-i32-SD-NEXT: fcvt s5, h5
+; CHECK-i32-SD-NEXT: fcvtzs w0, s16
+; CHECK-i32-SD-NEXT: mov h21, v1.h[1]
+; CHECK-i32-SD-NEXT: frintx s18, s18
+; CHECK-i32-SD-NEXT: mov h4, v4.h[3]
+; CHECK-i32-SD-NEXT: frintx s6, s6
+; CHECK-i32-SD-NEXT: frintx s16, s17
+; CHECK-i32-SD-NEXT: mov h17, v0.h[3]
+; CHECK-i32-SD-NEXT: fcvt s0, h0
+; CHECK-i32-SD-NEXT: fcvt s19, h19
+; CHECK-i32-SD-NEXT: frintx s5, s5
+; CHECK-i32-SD-NEXT: fcvtzs w2, s18
+; CHECK-i32-SD-NEXT: fcvt s18, h21
+; CHECK-i32-SD-NEXT: fcvt s21, h2
+; CHECK-i32-SD-NEXT: fcvtzs w18, s6
+; CHECK-i32-SD-NEXT: frintx s6, s7
+; CHECK-i32-SD-NEXT: fcvt s7, h20
+; CHECK-i32-SD-NEXT: fcvtzs w16, s16
+; CHECK-i32-SD-NEXT: fcvt s16, h17
+; CHECK-i32-SD-NEXT: fcvt s17, h1
+; CHECK-i32-SD-NEXT: frintx s0, s0
+; CHECK-i32-SD-NEXT: fcvtzs w3, s5
+; CHECK-i32-SD-NEXT: frintx s5, s19
+; CHECK-i32-SD-NEXT: fcvt s19, h22
+; CHECK-i32-SD-NEXT: mov h1, v1.h[3]
+; CHECK-i32-SD-NEXT: fcvtzs w1, s6
+; CHECK-i32-SD-NEXT: frintx s6, s7
+; CHECK-i32-SD-NEXT: mov h7, v2.h[1]
+; CHECK-i32-SD-NEXT: frintx s17, s17
+; CHECK-i32-SD-NEXT: frintx s20, s16
+; CHECK-i32-SD-NEXT: fmov s16, w12
+; CHECK-i32-SD-NEXT: fcvtzs w4, s0
+; CHECK-i32-SD-NEXT: frintx s0, s18
+; CHECK-i32-SD-NEXT: fcvtzs w5, s5
+; CHECK-i32-SD-NEXT: frintx s5, s19
+; CHECK-i32-SD-NEXT: frintx s18, s21
+; CHECK-i32-SD-NEXT: fcvt s19, h3
+; CHECK-i32-SD-NEXT: fcvtzs w12, s6
+; CHECK-i32-SD-NEXT: fcvt s6, h7
+; CHECK-i32-SD-NEXT: mov h7, v3.h[1]
+; CHECK-i32-SD-NEXT: fcvtzs w6, s17
+; CHECK-i32-SD-NEXT: fmov s17, w13
+; CHECK-i32-SD-NEXT: mov v16.s[1], w17
+; CHECK-i32-SD-NEXT: fcvtzs w17, s20
+; CHECK-i32-SD-NEXT: fcvtzs w7, s0
+; CHECK-i32-SD-NEXT: mov h0, v2.h[2]
+; CHECK-i32-SD-NEXT: mov h20, v3.h[2]
+; CHECK-i32-SD-NEXT: fcvtzs w13, s5
+; CHECK-i32-SD-NEXT: fmov s5, w15
+; CHECK-i32-SD-NEXT: frintx s6, s6
+; CHECK-i32-SD-NEXT: fcvt s7, h7
+; CHECK-i32-SD-NEXT: mov v17.s[1], w14
+; CHECK-i32-SD-NEXT: fcvtzs w14, s18
+; CHECK-i32-SD-NEXT: frintx s18, s19
+; CHECK-i32-SD-NEXT: mov h2, v2.h[3]
+; CHECK-i32-SD-NEXT: fcvt s0, h0
+; CHECK-i32-SD-NEXT: mov h3, v3.h[3]
+; CHECK-i32-SD-NEXT: mov v5.s[1], w0
+; CHECK-i32-SD-NEXT: fcvt s19, h20
+; CHECK-i32-SD-NEXT: fcvt s1, h1
+; CHECK-i32-SD-NEXT: mov v16.s[2], w9
+; CHECK-i32-SD-NEXT: fcvtzs w15, s6
+; CHECK-i32-SD-NEXT: frintx s6, s7
+; CHECK-i32-SD-NEXT: fmov s7, w2
+; CHECK-i32-SD-NEXT: fcvtzs w0, s18
+; CHECK-i32-SD-NEXT: fcvt s20, h2
+; CHECK-i32-SD-NEXT: fcvt s18, h4
+; CHECK-i32-SD-NEXT: frintx s21, s0
+; CHECK-i32-SD-NEXT: fcvt s3, h3
+; CHECK-i32-SD-NEXT: fmov s0, w4
+; CHECK-i32-SD-NEXT: frintx s19, s19
+; CHECK-i32-SD-NEXT: fmov s2, w6
+; CHECK-i32-SD-NEXT: fmov s4, w14
+; CHECK-i32-SD-NEXT: fcvtzs w2, s6
+; CHECK-i32-SD-NEXT: mov v7.s[1], w3
+; CHECK-i32-SD-NEXT: frintx s1, s1
+; CHECK-i32-SD-NEXT: fmov s6, w0
+; CHECK-i32-SD-NEXT: mov v0.s[1], w5
+; CHECK-i32-SD-NEXT: frintx s20, s20
+; CHECK-i32-SD-NEXT: mov v2.s[1], w7
+; CHECK-i32-SD-NEXT: fcvtzs w3, s21
+; CHECK-i32-SD-NEXT: mov v4.s[1], w15
+; CHECK-i32-SD-NEXT: fcvtzs w14, s19
+; CHECK-i32-SD-NEXT: frintx s18, s18
+; CHECK-i32-SD-NEXT: frintx s3, s3
+; CHECK-i32-SD-NEXT: mov v6.s[1], w2
+; CHECK-i32-SD-NEXT: mov v17.s[2], w11
+; CHECK-i32-SD-NEXT: fcvtzs w15, s1
+; CHECK-i32-SD-NEXT: fcvtzs w0, s20
+; CHECK-i32-SD-NEXT: mov v5.s[2], w18
+; CHECK-i32-SD-NEXT: mov v0.s[2], w12
+; CHECK-i32-SD-NEXT: mov v7.s[2], w1
+; CHECK-i32-SD-NEXT: mov v2.s[2], w13
+; CHECK-i32-SD-NEXT: mov v4.s[2], w3
+; CHECK-i32-SD-NEXT: fcvtzs w9, s18
+; CHECK-i32-SD-NEXT: fcvtzs w11, s3
+; CHECK-i32-SD-NEXT: mov v16.s[3], w8
+; CHECK-i32-SD-NEXT: mov v6.s[2], w14
+; CHECK-i32-SD-NEXT: mov v17.s[3], w10
+; CHECK-i32-SD-NEXT: mov v0.s[3], w17
+; CHECK-i32-SD-NEXT: mov v5.s[3], w16
+; CHECK-i32-SD-NEXT: mov v2.s[3], w15
+; CHECK-i32-SD-NEXT: mov v4.s[3], w0
+; CHECK-i32-SD-NEXT: mov v7.s[3], w9
+; CHECK-i32-SD-NEXT: mov v1.16b, v16.16b
+; CHECK-i32-SD-NEXT: mov v6.s[3], w11
+; CHECK-i32-SD-NEXT: mov v3.16b, v17.16b
+; CHECK-i32-SD-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v32f16:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-i64-NEXT: ext v5.16b, v2.16b, v2.16b, #8
-; CHECK-i64-NEXT: ext v6.16b, v3.16b, v3.16b, #8
-; CHECK-i64-NEXT: ext v7.16b, v0.16b, v0.16b, #8
-; CHECK-i64-NEXT: mov h19, v0.h[1]
-; CHECK-i64-NEXT: fcvt s21, h0
-; CHECK-i64-NEXT: mov h23, v1.h[2]
-; CHECK-i64-NEXT: fcvt s22, h1
-; CHECK-i64-NEXT: fcvt s26, h2
-; CHECK-i64-NEXT: mov h27, v2.h[1]
-; CHECK-i64-NEXT: mov h28, v2.h[2]
-; CHECK-i64-NEXT: mov h16, v4.h[2]
-; CHECK-i64-NEXT: fcvt s17, h5
-; CHECK-i64-NEXT: mov h18, v5.h[2]
-; CHECK-i64-NEXT: mov h20, v6.h[2]
-; CHECK-i64-NEXT: fcvt s24, h7
-; CHECK-i64-NEXT: fcvt s25, h6
-; CHECK-i64-NEXT: fcvt s19, h19
-; CHECK-i64-NEXT: frintx s22, s22
-; CHECK-i64-NEXT: fcvt s16, h16
-; CHECK-i64-NEXT: frintx s17, s17
-; CHECK-i64-NEXT: fcvt s18, h18
-; CHECK-i64-NEXT: fcvt s20, h20
-; CHECK-i64-NEXT: frintx s16, s16
-; CHECK-i64-NEXT: fcvtzs x12, s17
-; CHECK-i64-NEXT: frintx s17, s18
-; CHECK-i64-NEXT: frintx s18, s21
-; CHECK-i64-NEXT: fcvt s21, h23
-; CHECK-i64-NEXT: frintx s23, s24
-; CHECK-i64-NEXT: frintx s24, s25
-; CHECK-i64-NEXT: frintx s25, s19
-; CHECK-i64-NEXT: mov h19, v7.h[1]
-; CHECK-i64-NEXT: fcvtzs x13, s16
-; CHECK-i64-NEXT: frintx s16, s20
-; CHECK-i64-NEXT: frintx s20, s26
-; CHECK-i64-NEXT: fcvtzs x9, s23
-; CHECK-i64-NEXT: mov h23, v3.h[2]
-; CHECK-i64-NEXT: fcvt s26, h27
-; CHECK-i64-NEXT: fcvtzs x15, s24
-; CHECK-i64-NEXT: fcvtzs x10, s25
-; CHECK-i64-NEXT: fcvt s24, h28
-; CHECK-i64-NEXT: mov h25, v3.h[3]
-; CHECK-i64-NEXT: fcvtzs x14, s17
-; CHECK-i64-NEXT: frintx s21, s21
-; CHECK-i64-NEXT: fmov d17, x12
-; CHECK-i64-NEXT: fcvtzs x12, s16
-; CHECK-i64-NEXT: fmov d16, x13
-; CHECK-i64-NEXT: fcvtzs x13, s22
-; CHECK-i64-NEXT: fcvt s22, h3
-; CHECK-i64-NEXT: mov h3, v3.h[1]
-; CHECK-i64-NEXT: mov h27, v0.h[2]
-; CHECK-i64-NEXT: mov h28, v2.h[3]
-; CHECK-i64-NEXT: fcvt s23, h23
-; CHECK-i64-NEXT: frintx s26, s26
-; CHECK-i64-NEXT: fcvtzs x16, s20
-; CHECK-i64-NEXT: frintx s20, s24
-; CHECK-i64-NEXT: fcvt s24, h25
-; CHECK-i64-NEXT: fcvtzs x11, s18
-; CHECK-i64-NEXT: fmov d18, x14
-; CHECK-i64-NEXT: fcvtzs x14, s21
-; CHECK-i64-NEXT: frintx s22, s22
-; CHECK-i64-NEXT: fcvt s3, h3
-; CHECK-i64-NEXT: fcvt s25, h27
-; CHECK-i64-NEXT: fcvt s27, h28
-; CHECK-i64-NEXT: frintx s23, s23
-; CHECK-i64-NEXT: mov h21, v1.h[3]
-; CHECK-i64-NEXT: fmov d2, x15
-; CHECK-i64-NEXT: fcvtzs x15, s26
-; CHECK-i64-NEXT: fmov d26, x13
-; CHECK-i64-NEXT: mov h1, v1.h[1]
-; CHECK-i64-NEXT: fcvtzs x13, s20
-; CHECK-i64-NEXT: frintx s20, s24
-; CHECK-i64-NEXT: fmov d24, x14
-; CHECK-i64-NEXT: fcvtzs x14, s22
-; CHECK-i64-NEXT: frintx s3, s3
-; CHECK-i64-NEXT: fmov d22, x16
-; CHECK-i64-NEXT: frintx s27, s27
-; CHECK-i64-NEXT: fcvtzs x16, s23
-; CHECK-i64-NEXT: fcvt s21, h21
-; CHECK-i64-NEXT: frintx s25, s25
-; CHECK-i64-NEXT: fcvt s1, h1
-; CHECK-i64-NEXT: mov h0, v0.h[3]
-; CHECK-i64-NEXT: mov h23, v7.h[2]
-; CHECK-i64-NEXT: mov v22.d[1], x15
-; CHECK-i64-NEXT: fcvtzs x15, s20
-; CHECK-i64-NEXT: fmov d20, x13
-; CHECK-i64-NEXT: fcvtzs x13, s3
-; CHECK-i64-NEXT: fmov d3, x14
-; CHECK-i64-NEXT: fcvtzs x14, s27
-; CHECK-i64-NEXT: fmov d27, x16
-; CHECK-i64-NEXT: frintx s21, s21
-; CHECK-i64-NEXT: mov h7, v7.h[3]
-; CHECK-i64-NEXT: frintx s1, s1
-; CHECK-i64-NEXT: fcvt s0, h0
-; CHECK-i64-NEXT: fcvt s23, h23
-; CHECK-i64-NEXT: fcvt s19, h19
-; CHECK-i64-NEXT: mov v27.d[1], x15
-; CHECK-i64-NEXT: fcvtzs x15, s25
-; CHECK-i64-NEXT: mov h25, v6.h[3]
-; CHECK-i64-NEXT: mov h6, v6.h[1]
-; CHECK-i64-NEXT: mov v3.d[1], x13
-; CHECK-i64-NEXT: fcvtzs x13, s21
-; CHECK-i64-NEXT: mov h21, v5.h[1]
-; CHECK-i64-NEXT: mov h5, v5.h[3]
-; CHECK-i64-NEXT: mov v20.d[1], x14
-; CHECK-i64-NEXT: fcvtzs x14, s1
-; CHECK-i64-NEXT: mov h1, v4.h[1]
-; CHECK-i64-NEXT: frintx s0, s0
-; CHECK-i64-NEXT: fcvt s25, h25
-; CHECK-i64-NEXT: fcvt s7, h7
-; CHECK-i64-NEXT: stp q3, q27, [x8, #192]
-; CHECK-i64-NEXT: fcvt s6, h6
-; CHECK-i64-NEXT: mov h3, v4.h[3]
-; CHECK-i64-NEXT: stp q22, q20, [x8, #128]
-; CHECK-i64-NEXT: fcvt s21, h21
-; CHECK-i64-NEXT: fcvt s5, h5
-; CHECK-i64-NEXT: mov v24.d[1], x13
-; CHECK-i64-NEXT: mov v26.d[1], x14
-; CHECK-i64-NEXT: fcvt s4, h4
-; CHECK-i64-NEXT: frintx s22, s25
-; CHECK-i64-NEXT: fmov d20, x12
-; CHECK-i64-NEXT: fcvt s1, h1
-; CHECK-i64-NEXT: frintx s6, s6
-; CHECK-i64-NEXT: fcvt s3, h3
-; CHECK-i64-NEXT: fcvtzs x12, s0
-; CHECK-i64-NEXT: frintx s5, s5
-; CHECK-i64-NEXT: frintx s21, s21
-; CHECK-i64-NEXT: fmov d0, x11
-; CHECK-i64-NEXT: stp q26, q24, [x8, #64]
-; CHECK-i64-NEXT: fmov d24, x15
-; CHECK-i64-NEXT: frintx s4, s4
-; CHECK-i64-NEXT: fcvtzs x11, s22
-; CHECK-i64-NEXT: frintx s22, s23
-; CHECK-i64-NEXT: frintx s1, s1
-; CHECK-i64-NEXT: fcvtzs x13, s6
-; CHECK-i64-NEXT: frintx s3, s3
-; CHECK-i64-NEXT: frintx s6, s7
-; CHECK-i64-NEXT: fcvtzs x14, s5
-; CHECK-i64-NEXT: mov v24.d[1], x12
-; CHECK-i64-NEXT: frintx s5, s19
-; CHECK-i64-NEXT: fcvtzs x12, s21
-; CHECK-i64-NEXT: mov v0.d[1], x10
-; CHECK-i64-NEXT: fcvtzs x10, s4
-; CHECK-i64-NEXT: mov v20.d[1], x11
-; CHECK-i64-NEXT: fcvtzs x11, s22
-; CHECK-i64-NEXT: mov v2.d[1], x13
-; CHECK-i64-NEXT: fcvtzs x15, s3
-; CHECK-i64-NEXT: fcvtzs x13, s1
-; CHECK-i64-NEXT: mov v18.d[1], x14
-; CHECK-i64-NEXT: fcvtzs x14, s6
-; CHECK-i64-NEXT: stp q0, q24, [x8]
-; CHECK-i64-NEXT: mov v17.d[1], x12
-; CHECK-i64-NEXT: fcvtzs x12, s5
-; CHECK-i64-NEXT: fmov d0, x10
-; CHECK-i64-NEXT: fmov d1, x11
-; CHECK-i64-NEXT: stp q2, q20, [x8, #224]
-; CHECK-i64-NEXT: fmov d2, x9
-; CHECK-i64-NEXT: mov v16.d[1], x15
-; CHECK-i64-NEXT: stp q17, q18, [x8, #160]
-; CHECK-i64-NEXT: mov v0.d[1], x13
-; CHECK-i64-NEXT: mov v1.d[1], x14
-; CHECK-i64-NEXT: mov v2.d[1], x12
-; CHECK-i64-NEXT: stp q0, q16, [x8, #96]
-; CHECK-i64-NEXT: stp q2, q1, [x8, #32]
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v32f16:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: ext v4.16b, v1.16b, v1.16b, #8
+; CHECK-i64-SD-NEXT: ext v5.16b, v2.16b, v2.16b, #8
+; CHECK-i64-SD-NEXT: ext v6.16b, v3.16b, v3.16b, #8
+; CHECK-i64-SD-NEXT: ext v7.16b, v0.16b, v0.16b, #8
+; CHECK-i64-SD-NEXT: mov h19, v0.h[1]
+; CHECK-i64-SD-NEXT: fcvt s21, h0
+; CHECK-i64-SD-NEXT: mov h23, v1.h[2]
+; CHECK-i64-SD-NEXT: fcvt s22, h1
+; CHECK-i64-SD-NEXT: fcvt s26, h2
+; CHECK-i64-SD-NEXT: mov h27, v2.h[1]
+; CHECK-i64-SD-NEXT: mov h28, v2.h[2]
+; CHECK-i64-SD-NEXT: mov h16, v4.h[2]
+; CHECK-i64-SD-NEXT: fcvt s17, h5
+; CHECK-i64-SD-NEXT: mov h18, v5.h[2]
+; CHECK-i64-SD-NEXT: mov h20, v6.h[2]
+; CHECK-i64-SD-NEXT: fcvt s24, h7
+; CHECK-i64-SD-NEXT: fcvt s25, h6
+; CHECK-i64-SD-NEXT: fcvt s19, h19
+; CHECK-i64-SD-NEXT: frintx s22, s22
+; CHECK-i64-SD-NEXT: fcvt s16, h16
+; CHECK-i64-SD-NEXT: frintx s17, s17
+; CHECK-i64-SD-NEXT: fcvt s18, h18
+; CHECK-i64-SD-NEXT: fcvt s20, h20
+; CHECK-i64-SD-NEXT: frintx s16, s16
+; CHECK-i64-SD-NEXT: fcvtzs x12, s17
+; CHECK-i64-SD-NEXT: frintx s17, s18
+; CHECK-i64-SD-NEXT: frintx s18, s21
+; CHECK-i64-SD-NEXT: fcvt s21, h23
+; CHECK-i64-SD-NEXT: frintx s23, s24
+; CHECK-i64-SD-NEXT: frintx s24, s25
+; CHECK-i64-SD-NEXT: frintx s25, s19
+; CHECK-i64-SD-NEXT: mov h19, v7.h[1]
+; CHECK-i64-SD-NEXT: fcvtzs x13, s16
+; CHECK-i64-SD-NEXT: frintx s16, s20
+; CHECK-i64-SD-NEXT: frintx s20, s26
+; CHECK-i64-SD-NEXT: fcvtzs x9, s23
+; CHECK-i64-SD-NEXT: mov h23, v3.h[2]
+; CHECK-i64-SD-NEXT: fcvt s26, h27
+; CHECK-i64-SD-NEXT: fcvtzs x15, s24
+; CHECK-i64-SD-NEXT: fcvtzs x10, s25
+; CHECK-i64-SD-NEXT: fcvt s24, h28
+; CHECK-i64-SD-NEXT: mov h25, v3.h[3]
+; CHECK-i64-SD-NEXT: fcvtzs x14, s17
+; CHECK-i64-SD-NEXT: frintx s21, s21
+; CHECK-i64-SD-NEXT: fmov d17, x12
+; CHECK-i64-SD-NEXT: fcvtzs x12, s16
+; CHECK-i64-SD-NEXT: fmov d16, x13
+; CHECK-i64-SD-NEXT: fcvtzs x13, s22
+; CHECK-i64-SD-NEXT: fcvt s22, h3
+; CHECK-i64-SD-NEXT: mov h3, v3.h[1]
+; CHECK-i64-SD-NEXT: mov h27, v0.h[2]
+; CHECK-i64-SD-NEXT: mov h28, v2.h[3]
+; CHECK-i64-SD-NEXT: fcvt s23, h23
+; CHECK-i64-SD-NEXT: frintx s26, s26
+; CHECK-i64-SD-NEXT: fcvtzs x16, s20
+; CHECK-i64-SD-NEXT: frintx s20, s24
+; CHECK-i64-SD-NEXT: fcvt s24, h25
+; CHECK-i64-SD-NEXT: fcvtzs x11, s18
+; CHECK-i64-SD-NEXT: fmov d18, x14
+; CHECK-i64-SD-NEXT: fcvtzs x14, s21
+; CHECK-i64-SD-NEXT: frintx s22, s22
+; CHECK-i64-SD-NEXT: fcvt s3, h3
+; CHECK-i64-SD-NEXT: fcvt s25, h27
+; CHECK-i64-SD-NEXT: fcvt s27, h28
+; CHECK-i64-SD-NEXT: frintx s23, s23
+; CHECK-i64-SD-NEXT: mov h21, v1.h[3]
+; CHECK-i64-SD-NEXT: fmov d2, x15
+; CHECK-i64-SD-NEXT: fcvtzs x15, s26
+; CHECK-i64-SD-NEXT: fmov d26, x13
+; CHECK-i64-SD-NEXT: mov h1, v1.h[1]
+; CHECK-i64-SD-NEXT: fcvtzs x13, s20
+; CHECK-i64-SD-NEXT: frintx s20, s24
+; CHECK-i64-SD-NEXT: fmov d24, x14
+; CHECK-i64-SD-NEXT: fcvtzs x14, s22
+; CHECK-i64-SD-NEXT: frintx s3, s3
+; CHECK-i64-SD-NEXT: fmov d22, x16
+; CHECK-i64-SD-NEXT: frintx s27, s27
+; CHECK-i64-SD-NEXT: fcvtzs x16, s23
+; CHECK-i64-SD-NEXT: fcvt s21, h21
+; CHECK-i64-SD-NEXT: frintx s25, s25
+; CHECK-i64-SD-NEXT: fcvt s1, h1
+; CHECK-i64-SD-NEXT: mov h0, v0.h[3]
+; CHECK-i64-SD-NEXT: mov h23, v7.h[2]
+; CHECK-i64-SD-NEXT: mov v22.d[1], x15
+; CHECK-i64-SD-NEXT: fcvtzs x15, s20
+; CHECK-i64-SD-NEXT: fmov d20, x13
+; CHECK-i64-SD-NEXT: fcvtzs x13, s3
+; CHECK-i64-SD-NEXT: fmov d3, x14
+; CHECK-i64-SD-NEXT: fcvtzs x14, s27
+; CHECK-i64-SD-NEXT: fmov d27, x16
+; CHECK-i64-SD-NEXT: frintx s21, s21
+; CHECK-i64-SD-NEXT: mov h7, v7.h[3]
+; CHECK-i64-SD-NEXT: frintx s1, s1
+; CHECK-i64-SD-NEXT: fcvt s0, h0
+; CHECK-i64-SD-NEXT: fcvt s23, h23
+; CHECK-i64-SD-NEXT: fcvt s19, h19
+; CHECK-i64-SD-NEXT: mov v27.d[1], x15
+; CHECK-i64-SD-NEXT: fcvtzs x15, s25
+; CHECK-i64-SD-NEXT: mov h25, v6.h[3]
+; CHECK-i64-SD-NEXT: mov h6, v6.h[1]
+; CHECK-i64-SD-NEXT: mov v3.d[1], x13
+; CHECK-i64-SD-NEXT: fcvtzs x13, s21
+; CHECK-i64-SD-NEXT: mov h21, v5.h[1]
+; CHECK-i64-SD-NEXT: mov h5, v5.h[3]
+; CHECK-i64-SD-NEXT: mov v20.d[1], x14
+; CHECK-i64-SD-NEXT: fcvtzs x14, s1
+; CHECK-i64-SD-NEXT: mov h1, v4.h[1]
+; CHECK-i64-SD-NEXT: frintx s0, s0
+; CHECK-i64-SD-NEXT: fcvt s25, h25
+; CHECK-i64-SD-NEXT: fcvt s7, h7
+; CHECK-i64-SD-NEXT: stp q3, q27, [x8, #192]
+; CHECK-i64-SD-NEXT: fcvt s6, h6
+; CHECK-i64-SD-NEXT: mov h3, v4.h[3]
+; CHECK-i64-SD-NEXT: stp q22, q20, [x8, #128]
+; CHECK-i64-SD-NEXT: fcvt s21, h21
+; CHECK-i64-SD-NEXT: fcvt s5, h5
+; CHECK-i64-SD-NEXT: mov v24.d[1], x13
+; CHECK-i64-SD-NEXT: mov v26.d[1], x14
+; CHECK-i64-SD-NEXT: fcvt s4, h4
+; CHECK-i64-SD-NEXT: frintx s22, s25
+; CHECK-i64-SD-NEXT: fmov d20, x12
+; CHECK-i64-SD-NEXT: fcvt s1, h1
+; CHECK-i64-SD-NEXT: frintx s6, s6
+; CHECK-i64-SD-NEXT: fcvt s3, h3
+; CHECK-i64-SD-NEXT: fcvtzs x12, s0
+; CHECK-i64-SD-NEXT: frintx s5, s5
+; CHECK-i64-SD-NEXT: frintx s21, s21
+; CHECK-i64-SD-NEXT: fmov d0, x11
+; CHECK-i64-SD-NEXT: stp q26, q24, [x8, #64]
+; CHECK-i64-SD-NEXT: fmov d24, x15
+; CHECK-i64-SD-NEXT: frintx s4, s4
+; CHECK-i64-SD-NEXT: fcvtzs x11, s22
+; CHECK-i64-SD-NEXT: frintx s22, s23
+; CHECK-i64-SD-NEXT: frintx s1, s1
+; CHECK-i64-SD-NEXT: fcvtzs x13, s6
+; CHECK-i64-SD-NEXT: frintx s3, s3
+; CHECK-i64-SD-NEXT: frintx s6, s7
+; CHECK-i64-SD-NEXT: fcvtzs x14, s5
+; CHECK-i64-SD-NEXT: mov v24.d[1], x12
+; CHECK-i64-SD-NEXT: frintx s5, s19
+; CHECK-i64-SD-NEXT: fcvtzs x12, s21
+; CHECK-i64-SD-NEXT: mov v0.d[1], x10
+; CHECK-i64-SD-NEXT: fcvtzs x10, s4
+; CHECK-i64-SD-NEXT: mov v20.d[1], x11
+; CHECK-i64-SD-NEXT: fcvtzs x11, s22
+; CHECK-i64-SD-NEXT: mov v2.d[1], x13
+; CHECK-i64-SD-NEXT: fcvtzs x15, s3
+; CHECK-i64-SD-NEXT: fcvtzs x13, s1
+; CHECK-i64-SD-NEXT: mov v18.d[1], x14
+; CHECK-i64-SD-NEXT: fcvtzs x14, s6
+; CHECK-i64-SD-NEXT: stp q0, q24, [x8]
+; CHECK-i64-SD-NEXT: mov v17.d[1], x12
+; CHECK-i64-SD-NEXT: fcvtzs x12, s5
+; CHECK-i64-SD-NEXT: fmov d0, x10
+; CHECK-i64-SD-NEXT: fmov d1, x11
+; CHECK-i64-SD-NEXT: stp q2, q20, [x8, #224]
+; CHECK-i64-SD-NEXT: fmov d2, x9
+; CHECK-i64-SD-NEXT: mov v16.d[1], x15
+; CHECK-i64-SD-NEXT: stp q17, q18, [x8, #160]
+; CHECK-i64-SD-NEXT: mov v0.d[1], x13
+; CHECK-i64-SD-NEXT: mov v1.d[1], x14
+; CHECK-i64-SD-NEXT: mov v2.d[1], x12
+; CHECK-i64-SD-NEXT: stp q0, q16, [x8, #96]
+; CHECK-i64-SD-NEXT: stp q2, q1, [x8, #32]
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v32f16:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: fcvtl v4.4s, v0.4h
+; CHECK-i32-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-i32-GI-NEXT: fcvtl v5.4s, v1.4h
+; CHECK-i32-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-i32-GI-NEXT: fcvtl v6.4s, v2.4h
+; CHECK-i32-GI-NEXT: fcvtl2 v2.4s, v2.8h
+; CHECK-i32-GI-NEXT: fcvtl v7.4s, v3.4h
+; CHECK-i32-GI-NEXT: fcvtl2 v3.4s, v3.8h
+; CHECK-i32-GI-NEXT: frintx v4.4s, v4.4s
+; CHECK-i32-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i32-GI-NEXT: frintx v5.4s, v5.4s
+; CHECK-i32-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-i32-GI-NEXT: frintx v6.4s, v6.4s
+; CHECK-i32-GI-NEXT: frintx v2.4s, v2.4s
+; CHECK-i32-GI-NEXT: frintx v7.4s, v7.4s
+; CHECK-i32-GI-NEXT: frintx v3.4s, v3.4s
+; CHECK-i32-GI-NEXT: fcvtn v4.4h, v4.4s
+; CHECK-i32-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-i32-GI-NEXT: fcvtn v5.4h, v5.4s
+; CHECK-i32-GI-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-i32-GI-NEXT: fcvtn v6.4h, v6.4s
+; CHECK-i32-GI-NEXT: fcvtn v2.4h, v2.4s
+; CHECK-i32-GI-NEXT: fcvtn v7.4h, v7.4s
+; CHECK-i32-GI-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-i32-GI-NEXT: fcvtl v4.4s, v4.4h
+; CHECK-i32-GI-NEXT: fcvtl v16.4s, v0.4h
+; CHECK-i32-GI-NEXT: fcvtl v5.4s, v5.4h
+; CHECK-i32-GI-NEXT: fcvtl v17.4s, v1.4h
+; CHECK-i32-GI-NEXT: fcvtl v6.4s, v6.4h
+; CHECK-i32-GI-NEXT: fcvtl v18.4s, v2.4h
+; CHECK-i32-GI-NEXT: fcvtl v7.4s, v7.4h
+; CHECK-i32-GI-NEXT: fcvtl v19.4s, v3.4h
+; CHECK-i32-GI-NEXT: fcvtzs v0.4s, v4.4s
+; CHECK-i32-GI-NEXT: fcvtzs v1.4s, v16.4s
+; CHECK-i32-GI-NEXT: fcvtzs v2.4s, v5.4s
+; CHECK-i32-GI-NEXT: fcvtzs v3.4s, v17.4s
+; CHECK-i32-GI-NEXT: fcvtzs v4.4s, v6.4s
+; CHECK-i32-GI-NEXT: fcvtzs v5.4s, v18.4s
+; CHECK-i32-GI-NEXT: fcvtzs v6.4s, v7.4s
+; CHECK-i32-GI-NEXT: fcvtzs v7.4s, v19.4s
+; CHECK-i32-GI-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v32f16:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: fcvtl v4.4s, v0.4h
+; CHECK-i64-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-i64-GI-NEXT: fcvtl v5.4s, v1.4h
+; CHECK-i64-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-i64-GI-NEXT: fcvtl v6.4s, v2.4h
+; CHECK-i64-GI-NEXT: fcvtl2 v2.4s, v2.8h
+; CHECK-i64-GI-NEXT: fcvtl v7.4s, v3.4h
+; CHECK-i64-GI-NEXT: fcvtl2 v3.4s, v3.8h
+; CHECK-i64-GI-NEXT: frintx v4.4s, v4.4s
+; CHECK-i64-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i64-GI-NEXT: frintx v5.4s, v5.4s
+; CHECK-i64-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-i64-GI-NEXT: frintx v6.4s, v6.4s
+; CHECK-i64-GI-NEXT: frintx v2.4s, v2.4s
+; CHECK-i64-GI-NEXT: frintx v7.4s, v7.4s
+; CHECK-i64-GI-NEXT: frintx v3.4s, v3.4s
+; CHECK-i64-GI-NEXT: fcvtn v4.4h, v4.4s
+; CHECK-i64-GI-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-i64-GI-NEXT: fcvtn v5.4h, v5.4s
+; CHECK-i64-GI-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-i64-GI-NEXT: fcvtn v6.4h, v6.4s
+; CHECK-i64-GI-NEXT: fcvtn v2.4h, v2.4s
+; CHECK-i64-GI-NEXT: fcvtn v7.4h, v7.4s
+; CHECK-i64-GI-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-i64-GI-NEXT: fcvtl v4.4s, v4.4h
+; CHECK-i64-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-i64-GI-NEXT: fcvtl v5.4s, v5.4h
+; CHECK-i64-GI-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-i64-GI-NEXT: fcvtl v6.4s, v6.4h
+; CHECK-i64-GI-NEXT: fcvtl v2.4s, v2.4h
+; CHECK-i64-GI-NEXT: fcvtl v7.4s, v7.4h
+; CHECK-i64-GI-NEXT: fcvtl v3.4s, v3.4h
+; CHECK-i64-GI-NEXT: fcvtl v16.2d, v4.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v4.2d, v4.4s
+; CHECK-i64-GI-NEXT: fcvtl v17.2d, v0.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-i64-GI-NEXT: fcvtl v18.2d, v5.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v5.2d, v5.4s
+; CHECK-i64-GI-NEXT: fcvtl v19.2d, v1.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-i64-GI-NEXT: fcvtl v20.2d, v6.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v6.2d, v6.4s
+; CHECK-i64-GI-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-i64-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-i64-GI-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-GI-NEXT: fcvtzs v18.2d, v18.2d
+; CHECK-i64-GI-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i64-GI-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-i64-GI-NEXT: stp q16, q4, [x8]
+; CHECK-i64-GI-NEXT: fcvtzs v16.2d, v19.2d
+; CHECK-i64-GI-NEXT: fcvtl v4.2d, v2.2s
+; CHECK-i64-GI-NEXT: stp q17, q0, [x8, #32]
+; CHECK-i64-GI-NEXT: fcvtl2 v2.2d, v2.4s
+; CHECK-i64-GI-NEXT: fcvtl v0.2d, v7.2s
+; CHECK-i64-GI-NEXT: stp q18, q5, [x8, #64]
+; CHECK-i64-GI-NEXT: fcvtl2 v5.2d, v7.4s
+; CHECK-i64-GI-NEXT: fcvtl v7.2d, v3.2s
+; CHECK-i64-GI-NEXT: fcvtzs v17.2d, v20.2d
+; CHECK-i64-GI-NEXT: stp q16, q1, [x8, #96]
+; CHECK-i64-GI-NEXT: fcvtl2 v1.2d, v3.4s
+; CHECK-i64-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-i64-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-GI-NEXT: fcvtzs v3.2d, v5.2d
+; CHECK-i64-GI-NEXT: fcvtzs v5.2d, v7.2d
+; CHECK-i64-GI-NEXT: stp q17, q6, [x8, #128]
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i64-GI-NEXT: stp q4, q2, [x8, #160]
+; CHECK-i64-GI-NEXT: stp q0, q3, [x8, #192]
+; CHECK-i64-GI-NEXT: stp q5, q1, [x8, #224]
+; CHECK-i64-GI-NEXT: ret
%a = call <32 x iXLen> @llvm.lrint.v32iXLen.v32f16(<32 x half> %x)
ret <32 x iXLen> %a
}
@@ -816,16 +1025,25 @@ define <4 x iXLen> @lrint_v4f32(<4 x float> %x) nounwind {
; CHECK-i32-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-i32-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v4f32:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-i64-NEXT: frintx v0.2s, v0.2s
-; CHECK-i64-NEXT: frintx v1.2s, v1.2s
-; CHECK-i64-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-i64-NEXT: fcvtl v1.2d, v1.2s
-; CHECK-i64-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-i64-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v4f32:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-i64-SD-NEXT: frintx v0.2s, v0.2s
+; CHECK-i64-SD-NEXT: frintx v1.2s, v1.2s
+; CHECK-i64-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-i64-SD-NEXT: fcvtl v1.2d, v1.2s
+; CHECK-i64-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-SD-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v4f32:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i64-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v1.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-i64-GI-NEXT: ret
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f32(<4 x float> %x)
ret <4 x iXLen> %a
}
@@ -840,23 +1058,37 @@ define <8 x iXLen> @lrint_v8f32(<8 x float> %x) nounwind {
; CHECK-i32-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-i32-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v8f32:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: ext v2.16b, v0.16b, v0.16b, #8
-; CHECK-i64-NEXT: ext v3.16b, v1.16b, v1.16b, #8
-; CHECK-i64-NEXT: frintx v0.2s, v0.2s
-; CHECK-i64-NEXT: frintx v1.2s, v1.2s
-; CHECK-i64-NEXT: frintx v2.2s, v2.2s
-; CHECK-i64-NEXT: frintx v3.2s, v3.2s
-; CHECK-i64-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-i64-NEXT: fcvtl v1.2d, v1.2s
-; CHECK-i64-NEXT: fcvtl v4.2d, v2.2s
-; CHECK-i64-NEXT: fcvtl v3.2d, v3.2s
-; CHECK-i64-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-i64-NEXT: fcvtzs v2.2d, v1.2d
-; CHECK-i64-NEXT: fcvtzs v1.2d, v4.2d
-; CHECK-i64-NEXT: fcvtzs v3.2d, v3.2d
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v8f32:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-i64-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-i64-SD-NEXT: frintx v0.2s, v0.2s
+; CHECK-i64-SD-NEXT: frintx v1.2s, v1.2s
+; CHECK-i64-SD-NEXT: frintx v2.2s, v2.2s
+; CHECK-i64-SD-NEXT: frintx v3.2s, v3.2s
+; CHECK-i64-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-i64-SD-NEXT: fcvtl v1.2d, v1.2s
+; CHECK-i64-SD-NEXT: fcvtl v4.2d, v2.2s
+; CHECK-i64-SD-NEXT: fcvtl v3.2d, v3.2s
+; CHECK-i64-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-SD-NEXT: fcvtzs v2.2d, v1.2d
+; CHECK-i64-SD-NEXT: fcvtzs v1.2d, v4.2d
+; CHECK-i64-SD-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v8f32:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i64-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-i64-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v3.2d, v0.4s
+; CHECK-i64-GI-NEXT: fcvtl v4.2d, v1.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v5.2d, v1.4s
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v2.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v3.2d
+; CHECK-i64-GI-NEXT: fcvtzs v2.2d, v4.2d
+; CHECK-i64-GI-NEXT: fcvtzs v3.2d, v5.2d
+; CHECK-i64-GI-NEXT: ret
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f32(<8 x float> %x)
ret <8 x iXLen> %a
}
@@ -875,37 +1107,61 @@ define <16 x iXLen> @lrint_v16f32(<16 x float> %x) nounwind {
; CHECK-i32-NEXT: fcvtzs v3.4s, v3.4s
; CHECK-i32-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v16f32:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-i64-NEXT: ext v5.16b, v0.16b, v0.16b, #8
-; CHECK-i64-NEXT: ext v6.16b, v2.16b, v2.16b, #8
-; CHECK-i64-NEXT: ext v7.16b, v3.16b, v3.16b, #8
-; CHECK-i64-NEXT: frintx v0.2s, v0.2s
-; CHECK-i64-NEXT: frintx v1.2s, v1.2s
-; CHECK-i64-NEXT: frintx v2.2s, v2.2s
-; CHECK-i64-NEXT: frintx v3.2s, v3.2s
-; CHECK-i64-NEXT: frintx v5.2s, v5.2s
-; CHECK-i64-NEXT: frintx v4.2s, v4.2s
-; CHECK-i64-NEXT: frintx v6.2s, v6.2s
-; CHECK-i64-NEXT: frintx v7.2s, v7.2s
-; CHECK-i64-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-i64-NEXT: fcvtl v1.2d, v1.2s
-; CHECK-i64-NEXT: fcvtl v16.2d, v2.2s
-; CHECK-i64-NEXT: fcvtl v18.2d, v3.2s
-; CHECK-i64-NEXT: fcvtl v5.2d, v5.2s
-; CHECK-i64-NEXT: fcvtl v17.2d, v4.2s
-; CHECK-i64-NEXT: fcvtl v19.2d, v6.2s
-; CHECK-i64-NEXT: fcvtl v7.2d, v7.2s
-; CHECK-i64-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-i64-NEXT: fcvtzs v2.2d, v1.2d
-; CHECK-i64-NEXT: fcvtzs v4.2d, v16.2d
-; CHECK-i64-NEXT: fcvtzs v6.2d, v18.2d
-; CHECK-i64-NEXT: fcvtzs v1.2d, v5.2d
-; CHECK-i64-NEXT: fcvtzs v3.2d, v17.2d
-; CHECK-i64-NEXT: fcvtzs v5.2d, v19.2d
-; CHECK-i64-NEXT: fcvtzs v7.2d, v7.2d
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v16f32:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: ext v4.16b, v1.16b, v1.16b, #8
+; CHECK-i64-SD-NEXT: ext v5.16b, v0.16b, v0.16b, #8
+; CHECK-i64-SD-NEXT: ext v6.16b, v2.16b, v2.16b, #8
+; CHECK-i64-SD-NEXT: ext v7.16b, v3.16b, v3.16b, #8
+; CHECK-i64-SD-NEXT: frintx v0.2s, v0.2s
+; CHECK-i64-SD-NEXT: frintx v1.2s, v1.2s
+; CHECK-i64-SD-NEXT: frintx v2.2s, v2.2s
+; CHECK-i64-SD-NEXT: frintx v3.2s, v3.2s
+; CHECK-i64-SD-NEXT: frintx v5.2s, v5.2s
+; CHECK-i64-SD-NEXT: frintx v4.2s, v4.2s
+; CHECK-i64-SD-NEXT: frintx v6.2s, v6.2s
+; CHECK-i64-SD-NEXT: frintx v7.2s, v7.2s
+; CHECK-i64-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-i64-SD-NEXT: fcvtl v1.2d, v1.2s
+; CHECK-i64-SD-NEXT: fcvtl v16.2d, v2.2s
+; CHECK-i64-SD-NEXT: fcvtl v18.2d, v3.2s
+; CHECK-i64-SD-NEXT: fcvtl v5.2d, v5.2s
+; CHECK-i64-SD-NEXT: fcvtl v17.2d, v4.2s
+; CHECK-i64-SD-NEXT: fcvtl v19.2d, v6.2s
+; CHECK-i64-SD-NEXT: fcvtl v7.2d, v7.2s
+; CHECK-i64-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-SD-NEXT: fcvtzs v2.2d, v1.2d
+; CHECK-i64-SD-NEXT: fcvtzs v4.2d, v16.2d
+; CHECK-i64-SD-NEXT: fcvtzs v6.2d, v18.2d
+; CHECK-i64-SD-NEXT: fcvtzs v1.2d, v5.2d
+; CHECK-i64-SD-NEXT: fcvtzs v3.2d, v17.2d
+; CHECK-i64-SD-NEXT: fcvtzs v5.2d, v19.2d
+; CHECK-i64-SD-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v16f32:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i64-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-i64-GI-NEXT: frintx v2.4s, v2.4s
+; CHECK-i64-GI-NEXT: frintx v3.4s, v3.4s
+; CHECK-i64-GI-NEXT: fcvtl v4.2d, v0.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v5.2d, v0.4s
+; CHECK-i64-GI-NEXT: fcvtl v6.2d, v1.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v7.2d, v1.4s
+; CHECK-i64-GI-NEXT: fcvtl v16.2d, v2.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v17.2d, v2.4s
+; CHECK-i64-GI-NEXT: fcvtl v18.2d, v3.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v19.2d, v3.4s
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v4.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v5.2d
+; CHECK-i64-GI-NEXT: fcvtzs v2.2d, v6.2d
+; CHECK-i64-GI-NEXT: fcvtzs v3.2d, v7.2d
+; CHECK-i64-GI-NEXT: fcvtzs v4.2d, v16.2d
+; CHECK-i64-GI-NEXT: fcvtzs v5.2d, v17.2d
+; CHECK-i64-GI-NEXT: fcvtzs v6.2d, v18.2d
+; CHECK-i64-GI-NEXT: fcvtzs v7.2d, v19.2d
+; CHECK-i64-GI-NEXT: ret
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float> %x)
ret <16 x iXLen> %a
}
@@ -932,73 +1188,125 @@ define <32 x iXLen> @lrint_v32f32(<32 x float> %x) nounwind {
; CHECK-i32-NEXT: fcvtzs v7.4s, v7.4s
; CHECK-i32-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v32f32:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: ext v16.16b, v7.16b, v7.16b, #8
-; CHECK-i64-NEXT: ext v17.16b, v6.16b, v6.16b, #8
-; CHECK-i64-NEXT: frintx v7.2s, v7.2s
-; CHECK-i64-NEXT: frintx v6.2s, v6.2s
-; CHECK-i64-NEXT: ext v18.16b, v5.16b, v5.16b, #8
-; CHECK-i64-NEXT: ext v21.16b, v4.16b, v4.16b, #8
-; CHECK-i64-NEXT: ext v22.16b, v2.16b, v2.16b, #8
-; CHECK-i64-NEXT: frintx v5.2s, v5.2s
-; CHECK-i64-NEXT: ext v23.16b, v3.16b, v3.16b, #8
-; CHECK-i64-NEXT: frintx v4.2s, v4.2s
-; CHECK-i64-NEXT: ext v19.16b, v0.16b, v0.16b, #8
-; CHECK-i64-NEXT: ext v20.16b, v1.16b, v1.16b, #8
-; CHECK-i64-NEXT: frintx v16.2s, v16.2s
-; CHECK-i64-NEXT: frintx v17.2s, v17.2s
-; CHECK-i64-NEXT: fcvtl v7.2d, v7.2s
-; CHECK-i64-NEXT: fcvtl v6.2d, v6.2s
-; CHECK-i64-NEXT: frintx v18.2s, v18.2s
-; CHECK-i64-NEXT: frintx v21.2s, v21.2s
-; CHECK-i64-NEXT: frintx v2.2s, v2.2s
-; CHECK-i64-NEXT: frintx v3.2s, v3.2s
-; CHECK-i64-NEXT: fcvtl v5.2d, v5.2s
-; CHECK-i64-NEXT: frintx v23.2s, v23.2s
-; CHECK-i64-NEXT: fcvtl v4.2d, v4.2s
-; CHECK-i64-NEXT: frintx v1.2s, v1.2s
-; CHECK-i64-NEXT: fcvtl v16.2d, v16.2s
-; CHECK-i64-NEXT: fcvtl v17.2d, v17.2s
-; CHECK-i64-NEXT: fcvtzs v7.2d, v7.2d
-; CHECK-i64-NEXT: fcvtzs v6.2d, v6.2d
-; CHECK-i64-NEXT: fcvtl v18.2d, v18.2s
-; CHECK-i64-NEXT: fcvtl v21.2d, v21.2s
-; CHECK-i64-NEXT: frintx v20.2s, v20.2s
-; CHECK-i64-NEXT: fcvtl v3.2d, v3.2s
-; CHECK-i64-NEXT: fcvtzs v5.2d, v5.2d
-; CHECK-i64-NEXT: frintx v0.2s, v0.2s
-; CHECK-i64-NEXT: fcvtl v2.2d, v2.2s
-; CHECK-i64-NEXT: fcvtzs v4.2d, v4.2d
-; CHECK-i64-NEXT: fcvtzs v16.2d, v16.2d
-; CHECK-i64-NEXT: fcvtzs v17.2d, v17.2d
-; CHECK-i64-NEXT: fcvtl v1.2d, v1.2s
-; CHECK-i64-NEXT: fcvtzs v3.2d, v3.2d
-; CHECK-i64-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-i64-NEXT: fcvtzs v2.2d, v2.2d
-; CHECK-i64-NEXT: stp q6, q17, [x8, #192]
-; CHECK-i64-NEXT: fcvtl v6.2d, v23.2s
-; CHECK-i64-NEXT: frintx v17.2s, v19.2s
-; CHECK-i64-NEXT: stp q7, q16, [x8, #224]
-; CHECK-i64-NEXT: frintx v7.2s, v22.2s
-; CHECK-i64-NEXT: fcvtzs v16.2d, v18.2d
-; CHECK-i64-NEXT: fcvtzs v18.2d, v21.2d
-; CHECK-i64-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-i64-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-i64-NEXT: fcvtzs v6.2d, v6.2d
-; CHECK-i64-NEXT: stp q5, q16, [x8, #160]
-; CHECK-i64-NEXT: fcvtl v7.2d, v7.2s
-; CHECK-i64-NEXT: fcvtl v5.2d, v20.2s
-; CHECK-i64-NEXT: stp q4, q18, [x8, #128]
-; CHECK-i64-NEXT: fcvtl v4.2d, v17.2s
-; CHECK-i64-NEXT: stp q3, q6, [x8, #96]
-; CHECK-i64-NEXT: fcvtzs v7.2d, v7.2d
-; CHECK-i64-NEXT: fcvtzs v3.2d, v5.2d
-; CHECK-i64-NEXT: stp q1, q3, [x8, #32]
-; CHECK-i64-NEXT: stp q2, q7, [x8, #64]
-; CHECK-i64-NEXT: fcvtzs v2.2d, v4.2d
-; CHECK-i64-NEXT: stp q0, q2, [x8]
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v32f32:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: ext v16.16b, v7.16b, v7.16b, #8
+; CHECK-i64-SD-NEXT: ext v17.16b, v6.16b, v6.16b, #8
+; CHECK-i64-SD-NEXT: frintx v7.2s, v7.2s
+; CHECK-i64-SD-NEXT: frintx v6.2s, v6.2s
+; CHECK-i64-SD-NEXT: ext v18.16b, v5.16b, v5.16b, #8
+; CHECK-i64-SD-NEXT: ext v21.16b, v4.16b, v4.16b, #8
+; CHECK-i64-SD-NEXT: ext v22.16b, v2.16b, v2.16b, #8
+; CHECK-i64-SD-NEXT: frintx v5.2s, v5.2s
+; CHECK-i64-SD-NEXT: ext v23.16b, v3.16b, v3.16b, #8
+; CHECK-i64-SD-NEXT: frintx v4.2s, v4.2s
+; CHECK-i64-SD-NEXT: ext v19.16b, v0.16b, v0.16b, #8
+; CHECK-i64-SD-NEXT: ext v20.16b, v1.16b, v1.16b, #8
+; CHECK-i64-SD-NEXT: frintx v16.2s, v16.2s
+; CHECK-i64-SD-NEXT: frintx v17.2s, v17.2s
+; CHECK-i64-SD-NEXT: fcvtl v7.2d, v7.2s
+; CHECK-i64-SD-NEXT: fcvtl v6.2d, v6.2s
+; CHECK-i64-SD-NEXT: frintx v18.2s, v18.2s
+; CHECK-i64-SD-NEXT: frintx v21.2s, v21.2s
+; CHECK-i64-SD-NEXT: frintx v2.2s, v2.2s
+; CHECK-i64-SD-NEXT: frintx v3.2s, v3.2s
+; CHECK-i64-SD-NEXT: fcvtl v5.2d, v5.2s
+; CHECK-i64-SD-NEXT: frintx v23.2s, v23.2s
+; CHECK-i64-SD-NEXT: fcvtl v4.2d, v4.2s
+; CHECK-i64-SD-NEXT: frintx v1.2s, v1.2s
+; CHECK-i64-SD-NEXT: fcvtl v16.2d, v16.2s
+; CHECK-i64-SD-NEXT: fcvtl v17.2d, v17.2s
+; CHECK-i64-SD-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-i64-SD-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-i64-SD-NEXT: fcvtl v18.2d, v18.2s
+; CHECK-i64-SD-NEXT: fcvtl v21.2d, v21.2s
+; CHECK-i64-SD-NEXT: frintx v20.2s, v20.2s
+; CHECK-i64-SD-NEXT: fcvtl v3.2d, v3.2s
+; CHECK-i64-SD-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-i64-SD-NEXT: frintx v0.2s, v0.2s
+; CHECK-i64-SD-NEXT: fcvtl v2.2d, v2.2s
+; CHECK-i64-SD-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-i64-SD-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-i64-SD-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-i64-SD-NEXT: fcvtl v1.2d, v1.2s
+; CHECK-i64-SD-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-i64-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-i64-SD-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-i64-SD-NEXT: stp q6, q17, [x8, #192]
+; CHECK-i64-SD-NEXT: fcvtl v6.2d, v23.2s
+; CHECK-i64-SD-NEXT: frintx v17.2s, v19.2s
+; CHECK-i64-SD-NEXT: stp q7, q16, [x8, #224]
+; CHECK-i64-SD-NEXT: frintx v7.2s, v22.2s
+; CHECK-i64-SD-NEXT: fcvtzs v16.2d, v18.2d
+; CHECK-i64-SD-NEXT: fcvtzs v18.2d, v21.2d
+; CHECK-i64-SD-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i64-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-SD-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-i64-SD-NEXT: stp q5, q16, [x8, #160]
+; CHECK-i64-SD-NEXT: fcvtl v7.2d, v7.2s
+; CHECK-i64-SD-NEXT: fcvtl v5.2d, v20.2s
+; CHECK-i64-SD-NEXT: stp q4, q18, [x8, #128]
+; CHECK-i64-SD-NEXT: fcvtl v4.2d, v17.2s
+; CHECK-i64-SD-NEXT: stp q3, q6, [x8, #96]
+; CHECK-i64-SD-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-i64-SD-NEXT: fcvtzs v3.2d, v5.2d
+; CHECK-i64-SD-NEXT: stp q1, q3, [x8, #32]
+; CHECK-i64-SD-NEXT: stp q2, q7, [x8, #64]
+; CHECK-i64-SD-NEXT: fcvtzs v2.2d, v4.2d
+; CHECK-i64-SD-NEXT: stp q0, q2, [x8]
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v32f32:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: frintx v0.4s, v0.4s
+; CHECK-i64-GI-NEXT: frintx v1.4s, v1.4s
+; CHECK-i64-GI-NEXT: frintx v2.4s, v2.4s
+; CHECK-i64-GI-NEXT: frintx v3.4s, v3.4s
+; CHECK-i64-GI-NEXT: frintx v4.4s, v4.4s
+; CHECK-i64-GI-NEXT: frintx v5.4s, v5.4s
+; CHECK-i64-GI-NEXT: frintx v6.4s, v6.4s
+; CHECK-i64-GI-NEXT: frintx v7.4s, v7.4s
+; CHECK-i64-GI-NEXT: fcvtl v16.2d, v0.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-i64-GI-NEXT: fcvtl v17.2d, v1.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-i64-GI-NEXT: fcvtl v18.2d, v2.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v2.2d, v2.4s
+; CHECK-i64-GI-NEXT: fcvtl v19.2d, v3.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v3.2d, v3.4s
+; CHECK-i64-GI-NEXT: fcvtl v20.2d, v4.2s
+; CHECK-i64-GI-NEXT: fcvtl2 v4.2d, v4.4s
+; CHECK-i64-GI-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-GI-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i64-GI-NEXT: fcvtzs v18.2d, v18.2d
+; CHECK-i64-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-i64-GI-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-i64-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-i64-GI-NEXT: stp q16, q0, [x8]
+; CHECK-i64-GI-NEXT: fcvtl v0.2d, v5.2s
+; CHECK-i64-GI-NEXT: fcvtzs v16.2d, v19.2d
+; CHECK-i64-GI-NEXT: stp q17, q1, [x8, #32]
+; CHECK-i64-GI-NEXT: fcvtl2 v5.2d, v5.4s
+; CHECK-i64-GI-NEXT: fcvtl v1.2d, v6.2s
+; CHECK-i64-GI-NEXT: stp q18, q2, [x8, #64]
+; CHECK-i64-GI-NEXT: fcvtzs v17.2d, v20.2d
+; CHECK-i64-GI-NEXT: fcvtl2 v2.2d, v6.4s
+; CHECK-i64-GI-NEXT: fcvtl v6.2d, v7.2s
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-GI-NEXT: stp q16, q3, [x8, #96]
+; CHECK-i64-GI-NEXT: fcvtl2 v3.2d, v7.4s
+; CHECK-i64-GI-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i64-GI-NEXT: stp q17, q4, [x8, #128]
+; CHECK-i64-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-i64-GI-NEXT: fcvtzs v4.2d, v6.2d
+; CHECK-i64-GI-NEXT: stp q0, q5, [x8, #160]
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v3.2d
+; CHECK-i64-GI-NEXT: stp q1, q2, [x8, #192]
+; CHECK-i64-GI-NEXT: stp q4, q0, [x8, #224]
+; CHECK-i64-GI-NEXT: ret
%a = call <32 x iXLen> @llvm.lrint.v32iXLen.v32f32(<32 x float> %x)
ret <32 x iXLen> %a
}
@@ -1024,43 +1332,50 @@ define <1 x iXLen> @lrint_v1f64(<1 x double> %x) nounwind {
declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f64(<1 x double>)
define <2 x iXLen> @lrint_v2f64(<2 x double> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v2f64:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: frintx v0.2d, v0.2d
-; CHECK-i32-NEXT: mov d1, v0.d[1]
-; CHECK-i32-NEXT: fcvtzs w8, d0
-; CHECK-i32-NEXT: fcvtzs w9, d1
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: mov v0.s[1], w9
-; CHECK-i32-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v2f64:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: frintx v0.2d, v0.2d
+; CHECK-i32-SD-NEXT: mov d1, v0.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w8, d0
+; CHECK-i32-SD-NEXT: fcvtzs w9, d1
+; CHECK-i32-SD-NEXT: fmov s0, w8
+; CHECK-i32-SD-NEXT: mov v0.s[1], w9
+; CHECK-i32-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-i32-SD-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v2f64:
; CHECK-i64: // %bb.0:
; CHECK-i64-NEXT: frintx v0.2d, v0.2d
; CHECK-i64-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-i64-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v2f64:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: frintx v0.2d, v0.2d
+; CHECK-i32-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i32-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-i32-GI-NEXT: ret
%a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f64(<2 x double> %x)
ret <2 x iXLen> %a
}
declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f64(<2 x double>)
define <4 x iXLen> @lrint_v4f64(<4 x double> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v4f64:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: frintx v0.2d, v0.2d
-; CHECK-i32-NEXT: frintx v1.2d, v1.2d
-; CHECK-i32-NEXT: mov d2, v0.d[1]
-; CHECK-i32-NEXT: fcvtzs w8, d0
-; CHECK-i32-NEXT: fcvtzs w9, d2
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: fcvtzs w8, d1
-; CHECK-i32-NEXT: mov d1, v1.d[1]
-; CHECK-i32-NEXT: mov v0.s[1], w9
-; CHECK-i32-NEXT: mov v0.s[2], w8
-; CHECK-i32-NEXT: fcvtzs w8, d1
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v4f64:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: frintx v0.2d, v0.2d
+; CHECK-i32-SD-NEXT: frintx v1.2d, v1.2d
+; CHECK-i32-SD-NEXT: mov d2, v0.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w8, d0
+; CHECK-i32-SD-NEXT: fcvtzs w9, d2
+; CHECK-i32-SD-NEXT: fmov s0, w8
+; CHECK-i32-SD-NEXT: fcvtzs w8, d1
+; CHECK-i32-SD-NEXT: mov d1, v1.d[1]
+; CHECK-i32-SD-NEXT: mov v0.s[1], w9
+; CHECK-i32-SD-NEXT: mov v0.s[2], w8
+; CHECK-i32-SD-NEXT: fcvtzs w8, d1
+; CHECK-i32-SD-NEXT: mov v0.s[3], w8
+; CHECK-i32-SD-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v4f64:
; CHECK-i64: // %bb.0:
@@ -1069,39 +1384,48 @@ define <4 x iXLen> @lrint_v4f64(<4 x double> %x) nounwind {
; CHECK-i64-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-i64-NEXT: fcvtzs v1.2d, v1.2d
; CHECK-i64-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v4f64:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: frintx v0.2d, v0.2d
+; CHECK-i32-GI-NEXT: frintx v1.2d, v1.2d
+; CHECK-i32-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i32-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i32-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-i32-GI-NEXT: ret
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f64(<4 x double> %x)
ret <4 x iXLen> %a
}
declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f64(<4 x double>)
define <8 x iXLen> @lrint_v8f64(<8 x double> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v8f64:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: frintx v2.2d, v2.2d
-; CHECK-i32-NEXT: frintx v0.2d, v0.2d
-; CHECK-i32-NEXT: frintx v3.2d, v3.2d
-; CHECK-i32-NEXT: mov d4, v0.d[1]
-; CHECK-i32-NEXT: mov d5, v2.d[1]
-; CHECK-i32-NEXT: fcvtzs w8, d0
-; CHECK-i32-NEXT: fcvtzs w9, d2
-; CHECK-i32-NEXT: frintx v2.2d, v1.2d
-; CHECK-i32-NEXT: fcvtzs w10, d4
-; CHECK-i32-NEXT: fcvtzs w11, d5
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: fmov s1, w9
-; CHECK-i32-NEXT: fcvtzs w8, d2
-; CHECK-i32-NEXT: mov d2, v2.d[1]
-; CHECK-i32-NEXT: fcvtzs w9, d3
-; CHECK-i32-NEXT: mov d3, v3.d[1]
-; CHECK-i32-NEXT: mov v0.s[1], w10
-; CHECK-i32-NEXT: mov v1.s[1], w11
-; CHECK-i32-NEXT: mov v0.s[2], w8
-; CHECK-i32-NEXT: fcvtzs w8, d2
-; CHECK-i32-NEXT: mov v1.s[2], w9
-; CHECK-i32-NEXT: fcvtzs w9, d3
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: mov v1.s[3], w9
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v8f64:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: frintx v2.2d, v2.2d
+; CHECK-i32-SD-NEXT: frintx v0.2d, v0.2d
+; CHECK-i32-SD-NEXT: frintx v3.2d, v3.2d
+; CHECK-i32-SD-NEXT: mov d4, v0.d[1]
+; CHECK-i32-SD-NEXT: mov d5, v2.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w8, d0
+; CHECK-i32-SD-NEXT: fcvtzs w9, d2
+; CHECK-i32-SD-NEXT: frintx v2.2d, v1.2d
+; CHECK-i32-SD-NEXT: fcvtzs w10, d4
+; CHECK-i32-SD-NEXT: fcvtzs w11, d5
+; CHECK-i32-SD-NEXT: fmov s0, w8
+; CHECK-i32-SD-NEXT: fmov s1, w9
+; CHECK-i32-SD-NEXT: fcvtzs w8, d2
+; CHECK-i32-SD-NEXT: mov d2, v2.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w9, d3
+; CHECK-i32-SD-NEXT: mov d3, v3.d[1]
+; CHECK-i32-SD-NEXT: mov v0.s[1], w10
+; CHECK-i32-SD-NEXT: mov v1.s[1], w11
+; CHECK-i32-SD-NEXT: mov v0.s[2], w8
+; CHECK-i32-SD-NEXT: fcvtzs w8, d2
+; CHECK-i32-SD-NEXT: mov v1.s[2], w9
+; CHECK-i32-SD-NEXT: fcvtzs w9, d3
+; CHECK-i32-SD-NEXT: mov v0.s[3], w8
+; CHECK-i32-SD-NEXT: mov v1.s[3], w9
+; CHECK-i32-SD-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v8f64:
; CHECK-i64: // %bb.0:
@@ -1114,63 +1438,77 @@ define <8 x iXLen> @lrint_v8f64(<8 x double> %x) nounwind {
; CHECK-i64-NEXT: fcvtzs v2.2d, v2.2d
; CHECK-i64-NEXT: fcvtzs v3.2d, v3.2d
; CHECK-i64-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v8f64:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: frintx v0.2d, v0.2d
+; CHECK-i32-GI-NEXT: frintx v1.2d, v1.2d
+; CHECK-i32-GI-NEXT: frintx v2.2d, v2.2d
+; CHECK-i32-GI-NEXT: frintx v3.2d, v3.2d
+; CHECK-i32-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i32-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i32-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-i32-GI-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-i32-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-i32-GI-NEXT: uzp1 v1.4s, v2.4s, v3.4s
+; CHECK-i32-GI-NEXT: ret
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double> %x)
ret <8 x iXLen> %a
}
declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double>)
define <16 x iXLen> @lrint_v16f64(<16 x double> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v16f64:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: frintx v0.2d, v0.2d
-; CHECK-i32-NEXT: frintx v2.2d, v2.2d
-; CHECK-i32-NEXT: frintx v4.2d, v4.2d
-; CHECK-i32-NEXT: frintx v6.2d, v6.2d
-; CHECK-i32-NEXT: frintx v17.2d, v1.2d
-; CHECK-i32-NEXT: frintx v5.2d, v5.2d
-; CHECK-i32-NEXT: fcvtzs w8, d0
-; CHECK-i32-NEXT: mov d16, v0.d[1]
-; CHECK-i32-NEXT: fcvtzs w9, d2
-; CHECK-i32-NEXT: mov d2, v2.d[1]
-; CHECK-i32-NEXT: fcvtzs w10, d4
-; CHECK-i32-NEXT: mov d4, v4.d[1]
-; CHECK-i32-NEXT: fcvtzs w11, d6
-; CHECK-i32-NEXT: mov d6, v6.d[1]
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: fcvtzs w8, d16
-; CHECK-i32-NEXT: frintx v16.2d, v3.2d
-; CHECK-i32-NEXT: fmov s1, w9
-; CHECK-i32-NEXT: fcvtzs w9, d2
-; CHECK-i32-NEXT: fmov s2, w10
-; CHECK-i32-NEXT: fcvtzs w10, d4
-; CHECK-i32-NEXT: frintx v4.2d, v7.2d
-; CHECK-i32-NEXT: fmov s3, w11
-; CHECK-i32-NEXT: fcvtzs w11, d6
-; CHECK-i32-NEXT: mov d6, v17.d[1]
-; CHECK-i32-NEXT: mov v0.s[1], w8
-; CHECK-i32-NEXT: fcvtzs w8, d17
-; CHECK-i32-NEXT: mov d7, v16.d[1]
-; CHECK-i32-NEXT: mov v1.s[1], w9
-; CHECK-i32-NEXT: fcvtzs w9, d16
-; CHECK-i32-NEXT: mov v2.s[1], w10
-; CHECK-i32-NEXT: fcvtzs w10, d5
-; CHECK-i32-NEXT: mov d5, v5.d[1]
-; CHECK-i32-NEXT: mov v3.s[1], w11
-; CHECK-i32-NEXT: fcvtzs w11, d4
-; CHECK-i32-NEXT: mov d4, v4.d[1]
-; CHECK-i32-NEXT: mov v0.s[2], w8
-; CHECK-i32-NEXT: fcvtzs w8, d6
-; CHECK-i32-NEXT: mov v1.s[2], w9
-; CHECK-i32-NEXT: fcvtzs w9, d7
-; CHECK-i32-NEXT: mov v2.s[2], w10
-; CHECK-i32-NEXT: fcvtzs w10, d5
-; CHECK-i32-NEXT: mov v3.s[2], w11
-; CHECK-i32-NEXT: fcvtzs w11, d4
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: mov v1.s[3], w9
-; CHECK-i32-NEXT: mov v2.s[3], w10
-; CHECK-i32-NEXT: mov v3.s[3], w11
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v16f64:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: frintx v0.2d, v0.2d
+; CHECK-i32-SD-NEXT: frintx v2.2d, v2.2d
+; CHECK-i32-SD-NEXT: frintx v4.2d, v4.2d
+; CHECK-i32-SD-NEXT: frintx v6.2d, v6.2d
+; CHECK-i32-SD-NEXT: frintx v17.2d, v1.2d
+; CHECK-i32-SD-NEXT: frintx v5.2d, v5.2d
+; CHECK-i32-SD-NEXT: fcvtzs w8, d0
+; CHECK-i32-SD-NEXT: mov d16, v0.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w9, d2
+; CHECK-i32-SD-NEXT: mov d2, v2.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w10, d4
+; CHECK-i32-SD-NEXT: mov d4, v4.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w11, d6
+; CHECK-i32-SD-NEXT: mov d6, v6.d[1]
+; CHECK-i32-SD-NEXT: fmov s0, w8
+; CHECK-i32-SD-NEXT: fcvtzs w8, d16
+; CHECK-i32-SD-NEXT: frintx v16.2d, v3.2d
+; CHECK-i32-SD-NEXT: fmov s1, w9
+; CHECK-i32-SD-NEXT: fcvtzs w9, d2
+; CHECK-i32-SD-NEXT: fmov s2, w10
+; CHECK-i32-SD-NEXT: fcvtzs w10, d4
+; CHECK-i32-SD-NEXT: frintx v4.2d, v7.2d
+; CHECK-i32-SD-NEXT: fmov s3, w11
+; CHECK-i32-SD-NEXT: fcvtzs w11, d6
+; CHECK-i32-SD-NEXT: mov d6, v17.d[1]
+; CHECK-i32-SD-NEXT: mov v0.s[1], w8
+; CHECK-i32-SD-NEXT: fcvtzs w8, d17
+; CHECK-i32-SD-NEXT: mov d7, v16.d[1]
+; CHECK-i32-SD-NEXT: mov v1.s[1], w9
+; CHECK-i32-SD-NEXT: fcvtzs w9, d16
+; CHECK-i32-SD-NEXT: mov v2.s[1], w10
+; CHECK-i32-SD-NEXT: fcvtzs w10, d5
+; CHECK-i32-SD-NEXT: mov d5, v5.d[1]
+; CHECK-i32-SD-NEXT: mov v3.s[1], w11
+; CHECK-i32-SD-NEXT: fcvtzs w11, d4
+; CHECK-i32-SD-NEXT: mov d4, v4.d[1]
+; CHECK-i32-SD-NEXT: mov v0.s[2], w8
+; CHECK-i32-SD-NEXT: fcvtzs w8, d6
+; CHECK-i32-SD-NEXT: mov v1.s[2], w9
+; CHECK-i32-SD-NEXT: fcvtzs w9, d7
+; CHECK-i32-SD-NEXT: mov v2.s[2], w10
+; CHECK-i32-SD-NEXT: fcvtzs w10, d5
+; CHECK-i32-SD-NEXT: mov v3.s[2], w11
+; CHECK-i32-SD-NEXT: fcvtzs w11, d4
+; CHECK-i32-SD-NEXT: mov v0.s[3], w8
+; CHECK-i32-SD-NEXT: mov v1.s[3], w9
+; CHECK-i32-SD-NEXT: mov v2.s[3], w10
+; CHECK-i32-SD-NEXT: mov v3.s[3], w11
+; CHECK-i32-SD-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v16f64:
; CHECK-i64: // %bb.0:
@@ -1191,176 +1529,296 @@ define <16 x iXLen> @lrint_v16f64(<16 x double> %x) nounwind {
; CHECK-i64-NEXT: fcvtzs v6.2d, v6.2d
; CHECK-i64-NEXT: fcvtzs v7.2d, v7.2d
; CHECK-i64-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v16f64:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: frintx v0.2d, v0.2d
+; CHECK-i32-GI-NEXT: frintx v1.2d, v1.2d
+; CHECK-i32-GI-NEXT: frintx v2.2d, v2.2d
+; CHECK-i32-GI-NEXT: frintx v3.2d, v3.2d
+; CHECK-i32-GI-NEXT: frintx v4.2d, v4.2d
+; CHECK-i32-GI-NEXT: frintx v5.2d, v5.2d
+; CHECK-i32-GI-NEXT: frintx v6.2d, v6.2d
+; CHECK-i32-GI-NEXT: frintx v7.2d, v7.2d
+; CHECK-i32-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i32-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i32-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-i32-GI-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-i32-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-i32-GI-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-i32-GI-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-i32-GI-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-i32-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-i32-GI-NEXT: uzp1 v1.4s, v2.4s, v3.4s
+; CHECK-i32-GI-NEXT: uzp1 v2.4s, v4.4s, v5.4s
+; CHECK-i32-GI-NEXT: uzp1 v3.4s, v6.4s, v7.4s
+; CHECK-i32-GI-NEXT: ret
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f64(<16 x double> %x)
ret <16 x iXLen> %a
}
declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f64(<16 x double>)
define <32 x iXLen> @lrint_v32f64(<32 x double> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v32f64:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: frintx v17.2d, v0.2d
-; CHECK-i32-NEXT: frintx v19.2d, v2.2d
-; CHECK-i32-NEXT: frintx v0.2d, v1.2d
-; CHECK-i32-NEXT: frintx v1.2d, v4.2d
-; CHECK-i32-NEXT: frintx v2.2d, v3.2d
-; CHECK-i32-NEXT: frintx v3.2d, v5.2d
-; CHECK-i32-NEXT: ldp q16, q5, [sp]
-; CHECK-i32-NEXT: frintx v18.2d, v6.2d
-; CHECK-i32-NEXT: frintx v4.2d, v7.2d
-; CHECK-i32-NEXT: ldp q22, q6, [sp, #64]
-; CHECK-i32-NEXT: mov d20, v17.d[1]
-; CHECK-i32-NEXT: mov d21, v19.d[1]
-; CHECK-i32-NEXT: fcvtzs w8, d17
-; CHECK-i32-NEXT: fcvtzs w9, d19
-; CHECK-i32-NEXT: ldp q17, q7, [sp, #32]
-; CHECK-i32-NEXT: fcvtzs w12, d0
-; CHECK-i32-NEXT: mov d19, v1.d[1]
-; CHECK-i32-NEXT: fcvtzs w13, d1
-; CHECK-i32-NEXT: frintx v16.2d, v16.2d
-; CHECK-i32-NEXT: mov d23, v18.d[1]
-; CHECK-i32-NEXT: fcvtzs w15, d18
-; CHECK-i32-NEXT: fcvtzs w10, d20
-; CHECK-i32-NEXT: fcvtzs w11, d21
-; CHECK-i32-NEXT: mov d21, v0.d[1]
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: fmov s1, w9
-; CHECK-i32-NEXT: frintx v17.2d, v17.2d
-; CHECK-i32-NEXT: frintx v20.2d, v22.2d
-; CHECK-i32-NEXT: mov d22, v2.d[1]
-; CHECK-i32-NEXT: fcvtzs w14, d19
-; CHECK-i32-NEXT: mov d18, v16.d[1]
-; CHECK-i32-NEXT: frintx v7.2d, v7.2d
-; CHECK-i32-NEXT: mov v0.s[1], w10
-; CHECK-i32-NEXT: fcvtzs w10, d2
-; CHECK-i32-NEXT: mov v1.s[1], w11
-; CHECK-i32-NEXT: fcvtzs w8, d21
-; CHECK-i32-NEXT: ldp q21, q19, [sp, #96]
-; CHECK-i32-NEXT: fmov s2, w13
-; CHECK-i32-NEXT: fcvtzs w11, d23
-; CHECK-i32-NEXT: mov d23, v3.d[1]
-; CHECK-i32-NEXT: fcvtzs w9, d22
-; CHECK-i32-NEXT: mov d22, v17.d[1]
-; CHECK-i32-NEXT: fcvtzs w13, d18
-; CHECK-i32-NEXT: mov v0.s[2], w12
-; CHECK-i32-NEXT: fcvtzs w12, d16
-; CHECK-i32-NEXT: mov v1.s[2], w10
-; CHECK-i32-NEXT: fcvtzs w10, d3
-; CHECK-i32-NEXT: fmov s3, w15
-; CHECK-i32-NEXT: frintx v21.2d, v21.2d
-; CHECK-i32-NEXT: mov v2.s[1], w14
-; CHECK-i32-NEXT: mov d16, v20.d[1]
-; CHECK-i32-NEXT: fcvtzs w14, d17
-; CHECK-i32-NEXT: mov d17, v4.d[1]
-; CHECK-i32-NEXT: fcvtzs w15, d22
-; CHECK-i32-NEXT: frintx v22.2d, v5.2d
-; CHECK-i32-NEXT: mov v3.s[1], w11
-; CHECK-i32-NEXT: fcvtzs w11, d4
-; CHECK-i32-NEXT: fmov s4, w12
-; CHECK-i32-NEXT: fcvtzs w12, d20
-; CHECK-i32-NEXT: mov d18, v21.d[1]
-; CHECK-i32-NEXT: mov d20, v7.d[1]
-; CHECK-i32-NEXT: fmov s5, w14
-; CHECK-i32-NEXT: fcvtzs w14, d21
-; CHECK-i32-NEXT: mov v2.s[2], w10
-; CHECK-i32-NEXT: mov v4.s[1], w13
-; CHECK-i32-NEXT: fcvtzs w13, d16
-; CHECK-i32-NEXT: frintx v16.2d, v6.2d
-; CHECK-i32-NEXT: fcvtzs w10, d23
-; CHECK-i32-NEXT: mov v3.s[2], w11
-; CHECK-i32-NEXT: fcvtzs w11, d17
-; CHECK-i32-NEXT: fmov s6, w12
-; CHECK-i32-NEXT: mov v5.s[1], w15
-; CHECK-i32-NEXT: fcvtzs w15, d18
-; CHECK-i32-NEXT: frintx v18.2d, v19.2d
-; CHECK-i32-NEXT: fcvtzs w12, d22
-; CHECK-i32-NEXT: mov d19, v22.d[1]
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: mov v1.s[3], w9
-; CHECK-i32-NEXT: mov v6.s[1], w13
-; CHECK-i32-NEXT: fcvtzs w13, d7
-; CHECK-i32-NEXT: fmov s7, w14
-; CHECK-i32-NEXT: fcvtzs w14, d16
-; CHECK-i32-NEXT: mov d16, v16.d[1]
-; CHECK-i32-NEXT: mov v2.s[3], w10
-; CHECK-i32-NEXT: mov v4.s[2], w12
-; CHECK-i32-NEXT: fcvtzs w12, d19
-; CHECK-i32-NEXT: mov v3.s[3], w11
-; CHECK-i32-NEXT: mov v7.s[1], w15
-; CHECK-i32-NEXT: fcvtzs w15, d18
-; CHECK-i32-NEXT: mov d18, v18.d[1]
-; CHECK-i32-NEXT: mov v5.s[2], w13
-; CHECK-i32-NEXT: fcvtzs w13, d20
-; CHECK-i32-NEXT: mov v6.s[2], w14
-; CHECK-i32-NEXT: fcvtzs w14, d16
-; CHECK-i32-NEXT: mov v4.s[3], w12
-; CHECK-i32-NEXT: mov v7.s[2], w15
-; CHECK-i32-NEXT: fcvtzs w15, d18
-; CHECK-i32-NEXT: mov v5.s[3], w13
-; CHECK-i32-NEXT: mov v6.s[3], w14
-; CHECK-i32-NEXT: mov v7.s[3], w15
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v32f64:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: frintx v17.2d, v0.2d
+; CHECK-i32-SD-NEXT: frintx v19.2d, v2.2d
+; CHECK-i32-SD-NEXT: frintx v0.2d, v1.2d
+; CHECK-i32-SD-NEXT: frintx v1.2d, v4.2d
+; CHECK-i32-SD-NEXT: frintx v2.2d, v3.2d
+; CHECK-i32-SD-NEXT: frintx v3.2d, v5.2d
+; CHECK-i32-SD-NEXT: ldp q16, q5, [sp]
+; CHECK-i32-SD-NEXT: frintx v18.2d, v6.2d
+; CHECK-i32-SD-NEXT: frintx v4.2d, v7.2d
+; CHECK-i32-SD-NEXT: ldp q22, q6, [sp, #64]
+; CHECK-i32-SD-NEXT: mov d20, v17.d[1]
+; CHECK-i32-SD-NEXT: mov d21, v19.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w8, d17
+; CHECK-i32-SD-NEXT: fcvtzs w9, d19
+; CHECK-i32-SD-NEXT: ldp q17, q7, [sp, #32]
+; CHECK-i32-SD-NEXT: fcvtzs w12, d0
+; CHECK-i32-SD-NEXT: mov d19, v1.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w13, d1
+; CHECK-i32-SD-NEXT: frintx v16.2d, v16.2d
+; CHECK-i32-SD-NEXT: mov d23, v18.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w15, d18
+; CHECK-i32-SD-NEXT: fcvtzs w10, d20
+; CHECK-i32-SD-NEXT: fcvtzs w11, d21
+; CHECK-i32-SD-NEXT: mov d21, v0.d[1]
+; CHECK-i32-SD-NEXT: fmov s0, w8
+; CHECK-i32-SD-NEXT: fmov s1, w9
+; CHECK-i32-SD-NEXT: frintx v17.2d, v17.2d
+; CHECK-i32-SD-NEXT: frintx v20.2d, v22.2d
+; CHECK-i32-SD-NEXT: mov d22, v2.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w14, d19
+; CHECK-i32-SD-NEXT: mov d18, v16.d[1]
+; CHECK-i32-SD-NEXT: frintx v7.2d, v7.2d
+; CHECK-i32-SD-NEXT: mov v0.s[1], w10
+; CHECK-i32-SD-NEXT: fcvtzs w10, d2
+; CHECK-i32-SD-NEXT: mov v1.s[1], w11
+; CHECK-i32-SD-NEXT: fcvtzs w8, d21
+; CHECK-i32-SD-NEXT: ldp q21, q19, [sp, #96]
+; CHECK-i32-SD-NEXT: fmov s2, w13
+; CHECK-i32-SD-NEXT: fcvtzs w11, d23
+; CHECK-i32-SD-NEXT: mov d23, v3.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w9, d22
+; CHECK-i32-SD-NEXT: mov d22, v17.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w13, d18
+; CHECK-i32-SD-NEXT: mov v0.s[2], w12
+; CHECK-i32-SD-NEXT: fcvtzs w12, d16
+; CHECK-i32-SD-NEXT: mov v1.s[2], w10
+; CHECK-i32-SD-NEXT: fcvtzs w10, d3
+; CHECK-i32-SD-NEXT: fmov s3, w15
+; CHECK-i32-SD-NEXT: frintx v21.2d, v21.2d
+; CHECK-i32-SD-NEXT: mov v2.s[1], w14
+; CHECK-i32-SD-NEXT: mov d16, v20.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w14, d17
+; CHECK-i32-SD-NEXT: mov d17, v4.d[1]
+; CHECK-i32-SD-NEXT: fcvtzs w15, d22
+; CHECK-i32-SD-NEXT: frintx v22.2d, v5.2d
+; CHECK-i32-SD-NEXT: mov v3.s[1], w11
+; CHECK-i32-SD-NEXT: fcvtzs w11, d4
+; CHECK-i32-SD-NEXT: fmov s4, w12
+; CHECK-i32-SD-NEXT: fcvtzs w12, d20
+; CHECK-i32-SD-NEXT: mov d18, v21.d[1]
+; CHECK-i32-SD-NEXT: mov d20, v7.d[1]
+; CHECK-i32-SD-NEXT: fmov s5, w14
+; CHECK-i32-SD-NEXT: fcvtzs w14, d21
+; CHECK-i32-SD-NEXT: mov v2.s[2], w10
+; CHECK-i32-SD-NEXT: mov v4.s[1], w13
+; CHECK-i32-SD-NEXT: fcvtzs w13, d16
+; CHECK-i32-SD-NEXT: frintx v16.2d, v6.2d
+; CHECK-i32-SD-NEXT: fcvtzs w10, d23
+; CHECK-i32-SD-NEXT: mov v3.s[2], w11
+; CHECK-i32-SD-NEXT: fcvtzs w11, d17
+; CHECK-i32-SD-NEXT: fmov s6, w12
+; CHECK-i32-SD-NEXT: mov v5.s[1], w15
+; CHECK-i32-SD-NEXT: fcvtzs w15, d18
+; CHECK-i32-SD-NEXT: frintx v18.2d, v19.2d
+; CHECK-i32-SD-NEXT: fcvtzs w12, d22
+; CHECK-i32-SD-NEXT: mov d19, v22.d[1]
+; CHECK-i32-SD-NEXT: mov v0.s[3], w8
+; CHECK-i32-SD-NEXT: mov v1.s[3], w9
+; CHECK-i32-SD-NEXT: mov v6.s[1], w13
+; CHECK-i32-SD-NEXT: fcvtzs w13, d7
+; CHECK-i32-SD-NEXT: fmov s7, w14
+; CHECK-i32-SD-NEXT: fcvtzs w14, d16
+; CHECK-i32-SD-NEXT: mov d16, v16.d[1]
+; CHECK-i32-SD-NEXT: mov v2.s[3], w10
+; CHECK-i32-SD-NEXT: mov v4.s[2], w12
+; CHECK-i32-SD-NEXT: fcvtzs w12, d19
+; CHECK-i32-SD-NEXT: mov v3.s[3], w11
+; CHECK-i32-SD-NEXT: mov v7.s[1], w15
+; CHECK-i32-SD-NEXT: fcvtzs w15, d18
+; CHECK-i32-SD-NEXT: mov d18, v18.d[1]
+; CHECK-i32-SD-NEXT: mov v5.s[2], w13
+; CHECK-i32-SD-NEXT: fcvtzs w13, d20
+; CHECK-i32-SD-NEXT: mov v6.s[2], w14
+; CHECK-i32-SD-NEXT: fcvtzs w14, d16
+; CHECK-i32-SD-NEXT: mov v4.s[3], w12
+; CHECK-i32-SD-NEXT: mov v7.s[2], w15
+; CHECK-i32-SD-NEXT: fcvtzs w15, d18
+; CHECK-i32-SD-NEXT: mov v5.s[3], w13
+; CHECK-i32-SD-NEXT: mov v6.s[3], w14
+; CHECK-i32-SD-NEXT: mov v7.s[3], w15
+; CHECK-i32-SD-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v32f64:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: ldp q17, q16, [sp, #96]
-; CHECK-i64-NEXT: frintx v7.2d, v7.2d
-; CHECK-i64-NEXT: ldp q19, q18, [sp, #64]
-; CHECK-i64-NEXT: frintx v6.2d, v6.2d
-; CHECK-i64-NEXT: ldp q21, q20, [sp, #32]
-; CHECK-i64-NEXT: frintx v5.2d, v5.2d
-; CHECK-i64-NEXT: frintx v16.2d, v16.2d
-; CHECK-i64-NEXT: frintx v17.2d, v17.2d
-; CHECK-i64-NEXT: frintx v4.2d, v4.2d
-; CHECK-i64-NEXT: frintx v18.2d, v18.2d
-; CHECK-i64-NEXT: frintx v19.2d, v19.2d
-; CHECK-i64-NEXT: frintx v3.2d, v3.2d
-; CHECK-i64-NEXT: ldp q23, q22, [sp]
-; CHECK-i64-NEXT: frintx v20.2d, v20.2d
-; CHECK-i64-NEXT: frintx v21.2d, v21.2d
-; CHECK-i64-NEXT: frintx v2.2d, v2.2d
-; CHECK-i64-NEXT: frintx v1.2d, v1.2d
-; CHECK-i64-NEXT: fcvtzs v16.2d, v16.2d
-; CHECK-i64-NEXT: fcvtzs v17.2d, v17.2d
-; CHECK-i64-NEXT: frintx v0.2d, v0.2d
-; CHECK-i64-NEXT: frintx v22.2d, v22.2d
-; CHECK-i64-NEXT: fcvtzs v18.2d, v18.2d
-; CHECK-i64-NEXT: frintx v23.2d, v23.2d
-; CHECK-i64-NEXT: fcvtzs v19.2d, v19.2d
-; CHECK-i64-NEXT: fcvtzs v20.2d, v20.2d
-; CHECK-i64-NEXT: fcvtzs v7.2d, v7.2d
-; CHECK-i64-NEXT: fcvtzs v6.2d, v6.2d
-; CHECK-i64-NEXT: fcvtzs v5.2d, v5.2d
-; CHECK-i64-NEXT: fcvtzs v4.2d, v4.2d
-; CHECK-i64-NEXT: stp q17, q16, [x8, #224]
-; CHECK-i64-NEXT: fcvtzs v16.2d, v21.2d
-; CHECK-i64-NEXT: fcvtzs v3.2d, v3.2d
-; CHECK-i64-NEXT: fcvtzs v17.2d, v22.2d
-; CHECK-i64-NEXT: fcvtzs v2.2d, v2.2d
-; CHECK-i64-NEXT: fcvtzs v1.2d, v1.2d
-; CHECK-i64-NEXT: stp q19, q18, [x8, #192]
-; CHECK-i64-NEXT: fcvtzs v18.2d, v23.2d
-; CHECK-i64-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-i64-NEXT: stp q4, q5, [x8, #64]
-; CHECK-i64-NEXT: stp q6, q7, [x8, #96]
-; CHECK-i64-NEXT: stp q2, q3, [x8, #32]
-; CHECK-i64-NEXT: stp q0, q1, [x8]
-; CHECK-i64-NEXT: stp q18, q17, [x8, #128]
-; CHECK-i64-NEXT: stp q16, q20, [x8, #160]
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v32f64:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: ldp q17, q16, [sp, #96]
+; CHECK-i64-SD-NEXT: frintx v7.2d, v7.2d
+; CHECK-i64-SD-NEXT: ldp q19, q18, [sp, #64]
+; CHECK-i64-SD-NEXT: frintx v6.2d, v6.2d
+; CHECK-i64-SD-NEXT: ldp q21, q20, [sp, #32]
+; CHECK-i64-SD-NEXT: frintx v5.2d, v5.2d
+; CHECK-i64-SD-NEXT: frintx v16.2d, v16.2d
+; CHECK-i64-SD-NEXT: frintx v17.2d, v17.2d
+; CHECK-i64-SD-NEXT: frintx v4.2d, v4.2d
+; CHECK-i64-SD-NEXT: frintx v18.2d, v18.2d
+; CHECK-i64-SD-NEXT: frintx v19.2d, v19.2d
+; CHECK-i64-SD-NEXT: frintx v3.2d, v3.2d
+; CHECK-i64-SD-NEXT: ldp q23, q22, [sp]
+; CHECK-i64-SD-NEXT: frintx v20.2d, v20.2d
+; CHECK-i64-SD-NEXT: frintx v21.2d, v21.2d
+; CHECK-i64-SD-NEXT: frintx v2.2d, v2.2d
+; CHECK-i64-SD-NEXT: frintx v1.2d, v1.2d
+; CHECK-i64-SD-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-i64-SD-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-i64-SD-NEXT: frintx v0.2d, v0.2d
+; CHECK-i64-SD-NEXT: frintx v22.2d, v22.2d
+; CHECK-i64-SD-NEXT: fcvtzs v18.2d, v18.2d
+; CHECK-i64-SD-NEXT: frintx v23.2d, v23.2d
+; CHECK-i64-SD-NEXT: fcvtzs v19.2d, v19.2d
+; CHECK-i64-SD-NEXT: fcvtzs v20.2d, v20.2d
+; CHECK-i64-SD-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-i64-SD-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-i64-SD-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-i64-SD-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-i64-SD-NEXT: stp q17, q16, [x8, #224]
+; CHECK-i64-SD-NEXT: fcvtzs v16.2d, v21.2d
+; CHECK-i64-SD-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-i64-SD-NEXT: fcvtzs v17.2d, v22.2d
+; CHECK-i64-SD-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-i64-SD-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i64-SD-NEXT: stp q19, q18, [x8, #192]
+; CHECK-i64-SD-NEXT: fcvtzs v18.2d, v23.2d
+; CHECK-i64-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-SD-NEXT: stp q4, q5, [x8, #64]
+; CHECK-i64-SD-NEXT: stp q6, q7, [x8, #96]
+; CHECK-i64-SD-NEXT: stp q2, q3, [x8, #32]
+; CHECK-i64-SD-NEXT: stp q0, q1, [x8]
+; CHECK-i64-SD-NEXT: stp q18, q17, [x8, #128]
+; CHECK-i64-SD-NEXT: stp q16, q20, [x8, #160]
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v32f64:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: ldp q16, q17, [sp]
+; CHECK-i32-GI-NEXT: frintx v0.2d, v0.2d
+; CHECK-i32-GI-NEXT: ldp q18, q19, [sp, #32]
+; CHECK-i32-GI-NEXT: frintx v1.2d, v1.2d
+; CHECK-i32-GI-NEXT: ldp q20, q21, [sp, #64]
+; CHECK-i32-GI-NEXT: frintx v2.2d, v2.2d
+; CHECK-i32-GI-NEXT: ldp q22, q23, [sp, #96]
+; CHECK-i32-GI-NEXT: frintx v3.2d, v3.2d
+; CHECK-i32-GI-NEXT: frintx v4.2d, v4.2d
+; CHECK-i32-GI-NEXT: frintx v5.2d, v5.2d
+; CHECK-i32-GI-NEXT: frintx v6.2d, v6.2d
+; CHECK-i32-GI-NEXT: frintx v7.2d, v7.2d
+; CHECK-i32-GI-NEXT: frintx v16.2d, v16.2d
+; CHECK-i32-GI-NEXT: frintx v17.2d, v17.2d
+; CHECK-i32-GI-NEXT: frintx v18.2d, v18.2d
+; CHECK-i32-GI-NEXT: frintx v19.2d, v19.2d
+; CHECK-i32-GI-NEXT: frintx v20.2d, v20.2d
+; CHECK-i32-GI-NEXT: frintx v21.2d, v21.2d
+; CHECK-i32-GI-NEXT: frintx v22.2d, v22.2d
+; CHECK-i32-GI-NEXT: frintx v23.2d, v23.2d
+; CHECK-i32-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i32-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i32-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-i32-GI-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-i32-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-i32-GI-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-i32-GI-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-i32-GI-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-i32-GI-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-i32-GI-NEXT: fcvtzs v17.2d, v17.2d
+; CHECK-i32-GI-NEXT: fcvtzs v18.2d, v18.2d
+; CHECK-i32-GI-NEXT: fcvtzs v19.2d, v19.2d
+; CHECK-i32-GI-NEXT: fcvtzs v20.2d, v20.2d
+; CHECK-i32-GI-NEXT: fcvtzs v21.2d, v21.2d
+; CHECK-i32-GI-NEXT: fcvtzs v22.2d, v22.2d
+; CHECK-i32-GI-NEXT: fcvtzs v23.2d, v23.2d
+; CHECK-i32-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-i32-GI-NEXT: uzp1 v1.4s, v2.4s, v3.4s
+; CHECK-i32-GI-NEXT: uzp1 v2.4s, v4.4s, v5.4s
+; CHECK-i32-GI-NEXT: uzp1 v3.4s, v6.4s, v7.4s
+; CHECK-i32-GI-NEXT: uzp1 v4.4s, v16.4s, v17.4s
+; CHECK-i32-GI-NEXT: uzp1 v5.4s, v18.4s, v19.4s
+; CHECK-i32-GI-NEXT: uzp1 v6.4s, v20.4s, v21.4s
+; CHECK-i32-GI-NEXT: uzp1 v7.4s, v22.4s, v23.4s
+; CHECK-i32-GI-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v32f64:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: frintx v0.2d, v0.2d
+; CHECK-i64-GI-NEXT: frintx v1.2d, v1.2d
+; CHECK-i64-GI-NEXT: frintx v2.2d, v2.2d
+; CHECK-i64-GI-NEXT: frintx v3.2d, v3.2d
+; CHECK-i64-GI-NEXT: ldp q16, q17, [sp]
+; CHECK-i64-GI-NEXT: frintx v4.2d, v4.2d
+; CHECK-i64-GI-NEXT: frintx v5.2d, v5.2d
+; CHECK-i64-GI-NEXT: frintx v6.2d, v6.2d
+; CHECK-i64-GI-NEXT: frintx v7.2d, v7.2d
+; CHECK-i64-GI-NEXT: ldp q18, q19, [sp, #32]
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i64-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-i64-GI-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-i64-GI-NEXT: ldp q20, q21, [sp, #64]
+; CHECK-i64-GI-NEXT: frintx v16.2d, v16.2d
+; CHECK-i64-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-i64-GI-NEXT: fcvtzs v5.2d, v5.2d
+; CHECK-i64-GI-NEXT: fcvtzs v6.2d, v6.2d
+; CHECK-i64-GI-NEXT: ldp q22, q23, [sp, #96]
+; CHECK-i64-GI-NEXT: stp q0, q1, [x8]
+; CHECK-i64-GI-NEXT: frintx v0.2d, v17.2d
+; CHECK-i64-GI-NEXT: frintx v1.2d, v18.2d
+; CHECK-i64-GI-NEXT: stp q2, q3, [x8, #32]
+; CHECK-i64-GI-NEXT: frintx v2.2d, v19.2d
+; CHECK-i64-GI-NEXT: fcvtzs v7.2d, v7.2d
+; CHECK-i64-GI-NEXT: frintx v3.2d, v20.2d
+; CHECK-i64-GI-NEXT: fcvtzs v16.2d, v16.2d
+; CHECK-i64-GI-NEXT: stp q4, q5, [x8, #64]
+; CHECK-i64-GI-NEXT: frintx v4.2d, v21.2d
+; CHECK-i64-GI-NEXT: frintx v5.2d, v22.2d
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-i64-GI-NEXT: stp q6, q7, [x8, #96]
+; CHECK-i64-GI-NEXT: frintx v6.2d, v23.2d
+; CHECK-i64-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-i64-GI-NEXT: fcvtzs v3.2d, v3.2d
+; CHECK-i64-GI-NEXT: fcvtzs v4.2d, v4.2d
+; CHECK-i64-GI-NEXT: stp q16, q0, [x8, #128]
+; CHECK-i64-GI-NEXT: fcvtzs v0.2d, v5.2d
+; CHECK-i64-GI-NEXT: stp q1, q2, [x8, #160]
+; CHECK-i64-GI-NEXT: fcvtzs v1.2d, v6.2d
+; CHECK-i64-GI-NEXT: stp q3, q4, [x8, #192]
+; CHECK-i64-GI-NEXT: stp q0, q1, [x8, #224]
+; CHECK-i64-GI-NEXT: ret
%a = call <32 x iXLen> @llvm.lrint.v32iXLen.v16f64(<32 x double> %x)
ret <32 x iXLen> %a
}
declare <32 x iXLen> @llvm.lrint.v32iXLen.v32f64(<32 x double>)
define <1 x iXLen> @lrint_v1fp128(<1 x fp128> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v1fp128:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: fmov s0, w0
-; CHECK-i32-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v1fp128:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: fmov s0, w0
+; CHECK-i32-SD-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-i32-SD-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v1fp128:
; CHECK-i64: // %bb.0:
@@ -1369,430 +1827,1001 @@ define <1 x iXLen> @lrint_v1fp128(<1 x fp128> %x) nounwind {
; CHECK-i64-NEXT: fmov d0, x0
; CHECK-i64-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-i64-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v1fp128:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: fmov s0, w0
+; CHECK-i32-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-i32-GI-NEXT: ret
%a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1fp128(<1 x fp128> %x)
ret <1 x iXLen> %a
}
declare <1 x iXLen> @llvm.lrint.v1iXLen.v1fp128(<1 x fp128>)
define <2 x iXLen> @lrint_v2fp128(<2 x fp128> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v2fp128:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: sub sp, sp, #48
-; CHECK-i32-NEXT: str x30, [sp, #32] // 8-byte Spill
-; CHECK-i32-NEXT: str q1, [sp, #16] // 16-byte Spill
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: fmov s0, w0
-; CHECK-i32-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-i32-NEXT: ldr x30, [sp, #32] // 8-byte Reload
-; CHECK-i32-NEXT: mov v0.s[1], w0
-; CHECK-i32-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-i32-NEXT: add sp, sp, #48
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v2fp128:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: sub sp, sp, #48
+; CHECK-i32-SD-NEXT: str x30, [sp, #32] // 8-byte Spill
+; CHECK-i32-SD-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: fmov s0, w0
+; CHECK-i32-SD-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i32-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[1], w0
+; CHECK-i32-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-i32-SD-NEXT: add sp, sp, #48
+; CHECK-i32-SD-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v2fp128:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: sub sp, sp, #48
-; CHECK-i64-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-i64-NEXT: mov v0.16b, v1.16b
-; CHECK-i64-NEXT: str x30, [sp, #32] // 8-byte Spill
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-i64-NEXT: ldr x30, [sp, #32] // 8-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: add sp, sp, #48
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v2fp128:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: sub sp, sp, #48
+; CHECK-i64-SD-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-i64-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-i64-SD-NEXT: str x30, [sp, #32] // 8-byte Spill
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-i64-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: add sp, sp, #48
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v2fp128:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: sub sp, sp, #48
+; CHECK-i32-GI-NEXT: stp x30, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w19, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: fmov s0, w19
+; CHECK-i32-GI-NEXT: ldp x30, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: mov v0.s[1], w0
+; CHECK-i32-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-i32-GI-NEXT: add sp, sp, #48
+; CHECK-i32-GI-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v2fp128:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: sub sp, sp, #48
+; CHECK-i64-GI-NEXT: stp x30, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: str q1, [sp, #16] // 16-byte Spill
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x19, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: fmov d0, x19
+; CHECK-i64-GI-NEXT: ldp x30, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: mov v0.d[1], x0
+; CHECK-i64-GI-NEXT: add sp, sp, #48
+; CHECK-i64-GI-NEXT: ret
%a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2fp128(<2 x fp128> %x)
ret <2 x iXLen> %a
}
declare <2 x iXLen> @llvm.lrint.v2iXLen.v2fp128(<2 x fp128>)
define <4 x iXLen> @lrint_v4fp128(<4 x fp128> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v4fp128:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: sub sp, sp, #80
-; CHECK-i32-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-i32-NEXT: stp q2, q3, [sp, #16] // 32-byte Folded Spill
-; CHECK-i32-NEXT: str q1, [sp] // 16-byte Spill
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: fmov s0, w0
-; CHECK-i32-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[1], w0
-; CHECK-i32-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[2], w0
-; CHECK-i32-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-i32-NEXT: ldr x30, [sp, #64] // 8-byte Reload
-; CHECK-i32-NEXT: mov v0.s[3], w0
-; CHECK-i32-NEXT: add sp, sp, #80
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v4fp128:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: sub sp, sp, #80
+; CHECK-i32-SD-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-i32-SD-NEXT: stp q2, q3, [sp, #16] // 32-byte Folded Spill
+; CHECK-i32-SD-NEXT: str q1, [sp] // 16-byte Spill
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: fmov s0, w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[1], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[2], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-SD-NEXT: ldr x30, [sp, #64] // 8-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[3], w0
+; CHECK-i32-SD-NEXT: add sp, sp, #80
+; CHECK-i32-SD-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v4fp128:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: sub sp, sp, #80
-; CHECK-i64-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-i64-NEXT: mov v0.16b, v1.16b
-; CHECK-i64-NEXT: str x30, [sp, #64] // 8-byte Spill
-; CHECK-i64-NEXT: stp q3, q2, [sp, #32] // 32-byte Folded Spill
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d1, x0
-; CHECK-i64-NEXT: ldp q0, q4, [sp, #16] // 32-byte Folded Reload
-; CHECK-i64-NEXT: ldr x30, [sp, #64] // 8-byte Reload
-; CHECK-i64-NEXT: mov v1.d[1], v4.d[0]
-; CHECK-i64-NEXT: add sp, sp, #80
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v4fp128:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: sub sp, sp, #80
+; CHECK-i64-SD-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-i64-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-i64-SD-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-i64-SD-NEXT: stp q3, q2, [sp, #32] // 32-byte Folded Spill
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d1, x0
+; CHECK-i64-SD-NEXT: ldp q0, q4, [sp, #16] // 32-byte Folded Reload
+; CHECK-i64-SD-NEXT: ldr x30, [sp, #64] // 8-byte Reload
+; CHECK-i64-SD-NEXT: mov v1.d[1], v4.d[0]
+; CHECK-i64-SD-NEXT: add sp, sp, #80
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v4fp128:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: sub sp, sp, #96
+; CHECK-i32-GI-NEXT: stp x30, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp q2, q1, [sp] // 32-byte Folded Spill
+; CHECK-i32-GI-NEXT: str q3, [sp, #48] // 16-byte Spill
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w19, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w20, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w21, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: fmov s0, w19
+; CHECK-i32-GI-NEXT: mov v0.s[1], w20
+; CHECK-i32-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: mov v0.s[2], w21
+; CHECK-i32-GI-NEXT: ldp x30, x21, [sp, #64] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: mov v0.s[3], w0
+; CHECK-i32-GI-NEXT: add sp, sp, #96
+; CHECK-i32-GI-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v4fp128:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: sub sp, sp, #96
+; CHECK-i64-GI-NEXT: stp x30, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp q2, q1, [sp] // 32-byte Folded Spill
+; CHECK-i64-GI-NEXT: str q3, [sp, #48] // 16-byte Spill
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x19, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x20, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x21, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: fmov d0, x19
+; CHECK-i64-GI-NEXT: fmov d1, x21
+; CHECK-i64-GI-NEXT: ldp x30, x21, [sp, #64] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: mov v0.d[1], x20
+; CHECK-i64-GI-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: mov v1.d[1], x0
+; CHECK-i64-GI-NEXT: add sp, sp, #96
+; CHECK-i64-GI-NEXT: ret
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4fp128(<4 x fp128> %x)
ret <4 x iXLen> %a
}
declare <4 x iXLen> @llvm.lrint.v4iXLen.v4fp128(<4 x fp128>)
define <8 x iXLen> @lrint_v8fp128(<8 x fp128> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v8fp128:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: sub sp, sp, #144
-; CHECK-i32-NEXT: str x30, [sp, #128] // 8-byte Spill
-; CHECK-i32-NEXT: str q4, [sp, #96] // 16-byte Spill
-; CHECK-i32-NEXT: stp q1, q2, [sp] // 32-byte Folded Spill
-; CHECK-i32-NEXT: stp q3, q5, [sp, #32] // 32-byte Folded Spill
-; CHECK-i32-NEXT: stp q6, q7, [sp, #64] // 32-byte Folded Spill
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: fmov s0, w0
-; CHECK-i32-NEXT: str q0, [sp, #112] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #112] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[1], w0
-; CHECK-i32-NEXT: str q0, [sp, #112] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #112] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[2], w0
-; CHECK-i32-NEXT: str q0, [sp, #112] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #112] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[3], w0
-; CHECK-i32-NEXT: str q0, [sp, #112] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: fmov s0, w0
-; CHECK-i32-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[1], w0
-; CHECK-i32-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[2], w0
-; CHECK-i32-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #80] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldp q1, q0, [sp, #96] // 32-byte Folded Reload
-; CHECK-i32-NEXT: ldr x30, [sp, #128] // 8-byte Reload
-; CHECK-i32-NEXT: mov v1.s[3], w0
-; CHECK-i32-NEXT: add sp, sp, #144
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v8fp128:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: sub sp, sp, #144
+; CHECK-i32-SD-NEXT: str x30, [sp, #128] // 8-byte Spill
+; CHECK-i32-SD-NEXT: str q4, [sp, #96] // 16-byte Spill
+; CHECK-i32-SD-NEXT: stp q1, q2, [sp] // 32-byte Folded Spill
+; CHECK-i32-SD-NEXT: stp q3, q5, [sp, #32] // 32-byte Folded Spill
+; CHECK-i32-SD-NEXT: stp q6, q7, [sp, #64] // 32-byte Folded Spill
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: fmov s0, w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[1], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[2], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[3], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: fmov s0, w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[1], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[2], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldp q1, q0, [sp, #96] // 32-byte Folded Reload
+; CHECK-i32-SD-NEXT: ldr x30, [sp, #128] // 8-byte Reload
+; CHECK-i32-SD-NEXT: mov v1.s[3], w0
+; CHECK-i32-SD-NEXT: add sp, sp, #144
+; CHECK-i32-SD-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v8fp128:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: sub sp, sp, #144
-; CHECK-i64-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-i64-NEXT: mov v0.16b, v1.16b
-; CHECK-i64-NEXT: str x30, [sp, #128] // 8-byte Spill
-; CHECK-i64-NEXT: stp q3, q2, [sp, #16] // 32-byte Folded Spill
-; CHECK-i64-NEXT: stp q5, q4, [sp, #48] // 32-byte Folded Spill
-; CHECK-i64-NEXT: stp q7, q6, [sp, #96] // 32-byte Folded Spill
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #80] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #80] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #80] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #64] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #112] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d3, x0
-; CHECK-i64-NEXT: ldp q0, q1, [sp, #80] // 32-byte Folded Reload
-; CHECK-i64-NEXT: ldr q2, [sp, #64] // 16-byte Reload
-; CHECK-i64-NEXT: ldr x30, [sp, #128] // 8-byte Reload
-; CHECK-i64-NEXT: mov v3.d[1], v1.d[0]
-; CHECK-i64-NEXT: ldr q1, [sp, #32] // 16-byte Reload
-; CHECK-i64-NEXT: add sp, sp, #144
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v8fp128:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: sub sp, sp, #144
+; CHECK-i64-SD-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-i64-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-i64-SD-NEXT: str x30, [sp, #128] // 8-byte Spill
+; CHECK-i64-SD-NEXT: stp q3, q2, [sp, #16] // 32-byte Folded Spill
+; CHECK-i64-SD-NEXT: stp q5, q4, [sp, #48] // 32-byte Folded Spill
+; CHECK-i64-SD-NEXT: stp q7, q6, [sp, #96] // 32-byte Folded Spill
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #80] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d3, x0
+; CHECK-i64-SD-NEXT: ldp q0, q1, [sp, #80] // 32-byte Folded Reload
+; CHECK-i64-SD-NEXT: ldr q2, [sp, #64] // 16-byte Reload
+; CHECK-i64-SD-NEXT: ldr x30, [sp, #128] // 8-byte Reload
+; CHECK-i64-SD-NEXT: mov v3.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-i64-SD-NEXT: add sp, sp, #144
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v8fp128:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: sub sp, sp, #192
+; CHECK-i32-GI-NEXT: stp x30, x25, [sp, #128] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp x24, x23, [sp, #144] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp x22, x21, [sp, #160] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp q6, q5, [sp] // 32-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp q4, q3, [sp, #32] // 32-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp q2, q1, [sp, #64] // 32-byte Folded Spill
+; CHECK-i32-GI-NEXT: str q7, [sp, #112] // 16-byte Spill
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w19, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w20, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w21, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w22, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w23, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w24, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w25, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: fmov s0, w19
+; CHECK-i32-GI-NEXT: fmov s1, w23
+; CHECK-i32-GI-NEXT: mov v0.s[1], w20
+; CHECK-i32-GI-NEXT: mov v1.s[1], w24
+; CHECK-i32-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: ldp x24, x23, [sp, #144] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: mov v0.s[2], w21
+; CHECK-i32-GI-NEXT: mov v1.s[2], w25
+; CHECK-i32-GI-NEXT: ldp x30, x25, [sp, #128] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: mov v0.s[3], w22
+; CHECK-i32-GI-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: mov v1.s[3], w0
+; CHECK-i32-GI-NEXT: add sp, sp, #192
+; CHECK-i32-GI-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v8fp128:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: sub sp, sp, #192
+; CHECK-i64-GI-NEXT: stp x30, x25, [sp, #128] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp x24, x23, [sp, #144] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp x22, x21, [sp, #160] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp q6, q5, [sp] // 32-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp q4, q3, [sp, #32] // 32-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp q2, q1, [sp, #64] // 32-byte Folded Spill
+; CHECK-i64-GI-NEXT: str q7, [sp, #112] // 16-byte Spill
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x19, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x20, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x21, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x22, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x23, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x24, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x25, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: fmov d0, x19
+; CHECK-i64-GI-NEXT: fmov d1, x21
+; CHECK-i64-GI-NEXT: fmov d2, x23
+; CHECK-i64-GI-NEXT: fmov d3, x25
+; CHECK-i64-GI-NEXT: ldp x30, x25, [sp, #128] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: mov v0.d[1], x20
+; CHECK-i64-GI-NEXT: mov v1.d[1], x22
+; CHECK-i64-GI-NEXT: mov v2.d[1], x24
+; CHECK-i64-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: mov v3.d[1], x0
+; CHECK-i64-GI-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: ldp x24, x23, [sp, #144] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: add sp, sp, #192
+; CHECK-i64-GI-NEXT: ret
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8fp128(<8 x fp128> %x)
ret <8 x iXLen> %a
}
declare <8 x iXLen> @llvm.lrint.v8iXLen.v8fp128(<8 x fp128>)
define <16 x iXLen> @lrint_v16fp128(<16 x fp128> %x) nounwind {
-; CHECK-i32-LABEL: lrint_v16fp128:
-; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: sub sp, sp, #272
-; CHECK-i32-NEXT: stp q1, q2, [sp] // 32-byte Folded Spill
-; CHECK-i32-NEXT: ldr q1, [sp, #384]
-; CHECK-i32-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
-; CHECK-i32-NEXT: str q1, [sp, #176] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q1, [sp, #368]
-; CHECK-i32-NEXT: stp q3, q5, [sp, #32] // 32-byte Folded Spill
-; CHECK-i32-NEXT: str q1, [sp, #160] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q1, [sp, #352]
-; CHECK-i32-NEXT: stp q7, q4, [sp, #208] // 32-byte Folded Spill
-; CHECK-i32-NEXT: str q1, [sp, #144] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q1, [sp, #336]
-; CHECK-i32-NEXT: str q1, [sp, #192] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q1, [sp, #320]
-; CHECK-i32-NEXT: str q1, [sp, #128] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q1, [sp, #304]
-; CHECK-i32-NEXT: str q1, [sp, #112] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q1, [sp, #288]
-; CHECK-i32-NEXT: stp q6, q1, [sp, #80] // 32-byte Folded Spill
-; CHECK-i32-NEXT: ldr q1, [sp, #272]
-; CHECK-i32-NEXT: str q1, [sp, #64] // 16-byte Spill
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: fmov s0, w0
-; CHECK-i32-NEXT: str q0, [sp, #240] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #240] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[1], w0
-; CHECK-i32-NEXT: str q0, [sp, #240] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #240] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[2], w0
-; CHECK-i32-NEXT: str q0, [sp, #240] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #240] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[3], w0
-; CHECK-i32-NEXT: str q0, [sp, #240] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #224] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: fmov s0, w0
-; CHECK-i32-NEXT: str q0, [sp, #224] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #224] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[1], w0
-; CHECK-i32-NEXT: str q0, [sp, #224] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #80] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #224] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[2], w0
-; CHECK-i32-NEXT: str q0, [sp, #224] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #208] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #224] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[3], w0
-; CHECK-i32-NEXT: str q0, [sp, #224] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: fmov s0, w0
-; CHECK-i32-NEXT: str q0, [sp, #208] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #208] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[1], w0
-; CHECK-i32-NEXT: str q0, [sp, #208] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #112] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #208] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[2], w0
-; CHECK-i32-NEXT: str q0, [sp, #208] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #128] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #208] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[3], w0
-; CHECK-i32-NEXT: str q0, [sp, #208] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #192] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: fmov s0, w0
-; CHECK-i32-NEXT: str q0, [sp, #192] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #144] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #192] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[1], w0
-; CHECK-i32-NEXT: str q0, [sp, #192] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #160] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldr q0, [sp, #192] // 16-byte Reload
-; CHECK-i32-NEXT: mov v0.s[2], w0
-; CHECK-i32-NEXT: str q0, [sp, #192] // 16-byte Spill
-; CHECK-i32-NEXT: ldr q0, [sp, #176] // 16-byte Reload
-; CHECK-i32-NEXT: bl lrintl
-; CHECK-i32-NEXT: ldp q3, q2, [sp, #192] // 32-byte Folded Reload
-; CHECK-i32-NEXT: ldp q1, q0, [sp, #224] // 32-byte Folded Reload
-; CHECK-i32-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
-; CHECK-i32-NEXT: mov v3.s[3], w0
-; CHECK-i32-NEXT: add sp, sp, #272
-; CHECK-i32-NEXT: ret
+; CHECK-i32-SD-LABEL: lrint_v16fp128:
+; CHECK-i32-SD: // %bb.0:
+; CHECK-i32-SD-NEXT: sub sp, sp, #272
+; CHECK-i32-SD-NEXT: stp q1, q2, [sp] // 32-byte Folded Spill
+; CHECK-i32-SD-NEXT: ldr q1, [sp, #384]
+; CHECK-i32-SD-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
+; CHECK-i32-SD-NEXT: str q1, [sp, #176] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q1, [sp, #368]
+; CHECK-i32-SD-NEXT: stp q3, q5, [sp, #32] // 32-byte Folded Spill
+; CHECK-i32-SD-NEXT: str q1, [sp, #160] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q1, [sp, #352]
+; CHECK-i32-SD-NEXT: stp q7, q4, [sp, #208] // 32-byte Folded Spill
+; CHECK-i32-SD-NEXT: str q1, [sp, #144] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q1, [sp, #336]
+; CHECK-i32-SD-NEXT: str q1, [sp, #192] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q1, [sp, #320]
+; CHECK-i32-SD-NEXT: str q1, [sp, #128] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q1, [sp, #304]
+; CHECK-i32-SD-NEXT: str q1, [sp, #112] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q1, [sp, #288]
+; CHECK-i32-SD-NEXT: stp q6, q1, [sp, #80] // 32-byte Folded Spill
+; CHECK-i32-SD-NEXT: ldr q1, [sp, #272]
+; CHECK-i32-SD-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: fmov s0, w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #240] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[1], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #240] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[2], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #240] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[3], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #240] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: fmov s0, w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #224] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[1], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #224] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[2], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #224] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #208] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[3], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #224] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: fmov s0, w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #208] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[1], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #208] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[2], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #128] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #208] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[3], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: fmov s0, w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #192] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #144] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[1], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #192] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #160] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-i32-SD-NEXT: mov v0.s[2], w0
+; CHECK-i32-SD-NEXT: str q0, [sp, #192] // 16-byte Spill
+; CHECK-i32-SD-NEXT: ldr q0, [sp, #176] // 16-byte Reload
+; CHECK-i32-SD-NEXT: bl lrintl
+; CHECK-i32-SD-NEXT: ldp q3, q2, [sp, #192] // 32-byte Folded Reload
+; CHECK-i32-SD-NEXT: ldp q1, q0, [sp, #224] // 32-byte Folded Reload
+; CHECK-i32-SD-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
+; CHECK-i32-SD-NEXT: mov v3.s[3], w0
+; CHECK-i32-SD-NEXT: add sp, sp, #272
+; CHECK-i32-SD-NEXT: ret
;
-; CHECK-i64-LABEL: lrint_v16fp128:
-; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: sub sp, sp, #272
-; CHECK-i64-NEXT: str q2, [sp, #160] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q2, [sp, #368]
-; CHECK-i64-NEXT: stp q0, q3, [sp] // 32-byte Folded Spill
-; CHECK-i64-NEXT: mov v0.16b, v1.16b
-; CHECK-i64-NEXT: str q2, [sp, #240] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q2, [sp, #384]
-; CHECK-i64-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
-; CHECK-i64-NEXT: str q2, [sp, #224] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q2, [sp, #336]
-; CHECK-i64-NEXT: stp q5, q7, [sp, #32] // 32-byte Folded Spill
-; CHECK-i64-NEXT: str q2, [sp, #192] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q2, [sp, #352]
-; CHECK-i64-NEXT: str q2, [sp, #176] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q2, [sp, #304]
-; CHECK-i64-NEXT: str q2, [sp, #144] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q2, [sp, #320]
-; CHECK-i64-NEXT: stp q4, q2, [sp, #112] // 32-byte Folded Spill
-; CHECK-i64-NEXT: ldr q2, [sp, #272]
-; CHECK-i64-NEXT: stp q6, q2, [sp, #80] // 32-byte Folded Spill
-; CHECK-i64-NEXT: ldr q2, [sp, #288]
-; CHECK-i64-NEXT: str q2, [sp, #64] // 16-byte Spill
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #208] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #208] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #208] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #16] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #16] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #160] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #16] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #160] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #32] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #112] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #32] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #112] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #48] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #80] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #48] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #80] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #64] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #64] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #96] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #64] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #96] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #128] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #128] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #144] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #128] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #144] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #176] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #176] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #192] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: ldr q1, [sp, #176] // 16-byte Reload
-; CHECK-i64-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-i64-NEXT: str q0, [sp, #192] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #224] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d0, x0
-; CHECK-i64-NEXT: str q0, [sp, #224] // 16-byte Spill
-; CHECK-i64-NEXT: ldr q0, [sp, #240] // 16-byte Reload
-; CHECK-i64-NEXT: bl lrintl
-; CHECK-i64-NEXT: fmov d7, x0
-; CHECK-i64-NEXT: ldp q0, q1, [sp, #208] // 32-byte Folded Reload
-; CHECK-i64-NEXT: ldp q4, q2, [sp, #96] // 32-byte Folded Reload
-; CHECK-i64-NEXT: ldr q3, [sp, #80] // 16-byte Reload
-; CHECK-i64-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
-; CHECK-i64-NEXT: ldr q6, [sp, #192] // 16-byte Reload
-; CHECK-i64-NEXT: mov v7.d[1], v1.d[0]
-; CHECK-i64-NEXT: ldp q5, q1, [sp, #144] // 32-byte Folded Reload
-; CHECK-i64-NEXT: add sp, sp, #272
-; CHECK-i64-NEXT: ret
+; CHECK-i64-SD-LABEL: lrint_v16fp128:
+; CHECK-i64-SD: // %bb.0:
+; CHECK-i64-SD-NEXT: sub sp, sp, #272
+; CHECK-i64-SD-NEXT: str q2, [sp, #160] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q2, [sp, #368]
+; CHECK-i64-SD-NEXT: stp q0, q3, [sp] // 32-byte Folded Spill
+; CHECK-i64-SD-NEXT: mov v0.16b, v1.16b
+; CHECK-i64-SD-NEXT: str q2, [sp, #240] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q2, [sp, #384]
+; CHECK-i64-SD-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
+; CHECK-i64-SD-NEXT: str q2, [sp, #224] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q2, [sp, #336]
+; CHECK-i64-SD-NEXT: stp q5, q7, [sp, #32] // 32-byte Folded Spill
+; CHECK-i64-SD-NEXT: str q2, [sp, #192] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q2, [sp, #352]
+; CHECK-i64-SD-NEXT: str q2, [sp, #176] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q2, [sp, #304]
+; CHECK-i64-SD-NEXT: str q2, [sp, #144] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q2, [sp, #320]
+; CHECK-i64-SD-NEXT: stp q4, q2, [sp, #112] // 32-byte Folded Spill
+; CHECK-i64-SD-NEXT: ldr q2, [sp, #272]
+; CHECK-i64-SD-NEXT: stp q6, q2, [sp, #80] // 32-byte Folded Spill
+; CHECK-i64-SD-NEXT: ldr q2, [sp, #288]
+; CHECK-i64-SD-NEXT: str q2, [sp, #64] // 16-byte Spill
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #208] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #160] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #160] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #32] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #48] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #64] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #128] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #128] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #144] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #128] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #144] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #176] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #176] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: ldr q1, [sp, #176] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: str q0, [sp, #192] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d0, x0
+; CHECK-i64-SD-NEXT: str q0, [sp, #224] // 16-byte Spill
+; CHECK-i64-SD-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-i64-SD-NEXT: bl lrintl
+; CHECK-i64-SD-NEXT: fmov d7, x0
+; CHECK-i64-SD-NEXT: ldp q0, q1, [sp, #208] // 32-byte Folded Reload
+; CHECK-i64-SD-NEXT: ldp q4, q2, [sp, #96] // 32-byte Folded Reload
+; CHECK-i64-SD-NEXT: ldr q3, [sp, #80] // 16-byte Reload
+; CHECK-i64-SD-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
+; CHECK-i64-SD-NEXT: ldr q6, [sp, #192] // 16-byte Reload
+; CHECK-i64-SD-NEXT: mov v7.d[1], v1.d[0]
+; CHECK-i64-SD-NEXT: ldp q5, q1, [sp, #144] // 32-byte Folded Reload
+; CHECK-i64-SD-NEXT: add sp, sp, #272
+; CHECK-i64-SD-NEXT: ret
+;
+; CHECK-i32-GI-LABEL: lrint_v16fp128:
+; CHECK-i32-GI: // %bb.0:
+; CHECK-i32-GI-NEXT: sub sp, sp, #384
+; CHECK-i32-GI-NEXT: stp q6, q5, [sp, #160] // 32-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp q4, q3, [sp, #192] // 32-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp q2, q1, [sp, #224] // 32-byte Folded Spill
+; CHECK-i32-GI-NEXT: ldr q1, [sp, #384]
+; CHECK-i32-GI-NEXT: stp x29, x30, [sp, #288] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: stp q1, q7, [sp, #128] // 32-byte Folded Spill
+; CHECK-i32-GI-NEXT: ldr q1, [sp, #400]
+; CHECK-i32-GI-NEXT: stp x28, x27, [sp, #304] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: str q1, [sp, #112] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q1, [sp, #416]
+; CHECK-i32-GI-NEXT: stp x26, x25, [sp, #320] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: str q1, [sp, #96] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q1, [sp, #432]
+; CHECK-i32-GI-NEXT: stp x24, x23, [sp, #336] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q1, [sp, #448]
+; CHECK-i32-GI-NEXT: stp x22, x21, [sp, #352] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q1, [sp, #464]
+; CHECK-i32-GI-NEXT: stp x20, x19, [sp, #368] // 16-byte Folded Spill
+; CHECK-i32-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q1, [sp, #480]
+; CHECK-i32-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q1, [sp, #496]
+; CHECK-i32-GI-NEXT: str q1, [sp, #272] // 16-byte Spill
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #256] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #240] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #224] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #208] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #192] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #176] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #176] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #160] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #160] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #144] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #144] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #128] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #128] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #272] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl rintl
+; CHECK-i32-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #256] // 16-byte Reload
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-i32-GI-NEXT: str w0, [sp, #12] // 4-byte Spill
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-i32-GI-NEXT: str w0, [sp, #272] // 4-byte Spill
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #208] // 16-byte Reload
+; CHECK-i32-GI-NEXT: str w0, [sp, #256] // 4-byte Spill
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-i32-GI-NEXT: str w0, [sp, #240] // 4-byte Spill
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #176] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w26, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #160] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w23, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #144] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w24, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #128] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w25, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w27, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w28, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w29, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w19, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w20, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w21, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i32-GI-NEXT: mov w22, w0
+; CHECK-i32-GI-NEXT: bl __fixtfsi
+; CHECK-i32-GI-NEXT: fmov s1, w26
+; CHECK-i32-GI-NEXT: fmov s2, w27
+; CHECK-i32-GI-NEXT: ldr s0, [sp, #12] // 4-byte Reload
+; CHECK-i32-GI-NEXT: fmov s3, w20
+; CHECK-i32-GI-NEXT: ldr w8, [sp, #272] // 4-byte Reload
+; CHECK-i32-GI-NEXT: mov v1.s[1], w23
+; CHECK-i32-GI-NEXT: mov v2.s[1], w28
+; CHECK-i32-GI-NEXT: mov v0.s[1], w8
+; CHECK-i32-GI-NEXT: mov v3.s[1], w21
+; CHECK-i32-GI-NEXT: ldr w8, [sp, #256] // 4-byte Reload
+; CHECK-i32-GI-NEXT: ldp x28, x27, [sp, #304] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: mov v1.s[2], w24
+; CHECK-i32-GI-NEXT: mov v2.s[2], w29
+; CHECK-i32-GI-NEXT: mov v0.s[2], w8
+; CHECK-i32-GI-NEXT: mov v3.s[2], w22
+; CHECK-i32-GI-NEXT: ldr w8, [sp, #240] // 4-byte Reload
+; CHECK-i32-GI-NEXT: ldp x22, x21, [sp, #352] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: ldp x24, x23, [sp, #336] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: mov v1.s[3], w25
+; CHECK-i32-GI-NEXT: mov v2.s[3], w19
+; CHECK-i32-GI-NEXT: mov v0.s[3], w8
+; CHECK-i32-GI-NEXT: ldp x20, x19, [sp, #368] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: mov v3.s[3], w0
+; CHECK-i32-GI-NEXT: ldp x26, x25, [sp, #320] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload
+; CHECK-i32-GI-NEXT: add sp, sp, #384
+; CHECK-i32-GI-NEXT: ret
+;
+; CHECK-i64-GI-LABEL: lrint_v16fp128:
+; CHECK-i64-GI: // %bb.0:
+; CHECK-i64-GI-NEXT: sub sp, sp, #384
+; CHECK-i64-GI-NEXT: stp q6, q5, [sp, #160] // 32-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp q4, q3, [sp, #192] // 32-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp q2, q1, [sp, #224] // 32-byte Folded Spill
+; CHECK-i64-GI-NEXT: ldr q1, [sp, #384]
+; CHECK-i64-GI-NEXT: stp x29, x30, [sp, #288] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: stp q1, q7, [sp, #128] // 32-byte Folded Spill
+; CHECK-i64-GI-NEXT: ldr q1, [sp, #400]
+; CHECK-i64-GI-NEXT: stp x28, x27, [sp, #304] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: str q1, [sp, #112] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q1, [sp, #416]
+; CHECK-i64-GI-NEXT: stp x26, x25, [sp, #320] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: str q1, [sp, #96] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q1, [sp, #432]
+; CHECK-i64-GI-NEXT: stp x24, x23, [sp, #336] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: str q1, [sp, #80] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q1, [sp, #448]
+; CHECK-i64-GI-NEXT: stp x22, x21, [sp, #352] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: str q1, [sp, #64] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q1, [sp, #464]
+; CHECK-i64-GI-NEXT: stp x20, x19, [sp, #368] // 16-byte Folded Spill
+; CHECK-i64-GI-NEXT: str q1, [sp, #48] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q1, [sp, #480]
+; CHECK-i64-GI-NEXT: str q1, [sp, #32] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q1, [sp, #496]
+; CHECK-i64-GI-NEXT: str q1, [sp, #272] // 16-byte Spill
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #256] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #240] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #224] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #208] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #208] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #192] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #176] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #176] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #160] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #160] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #144] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #144] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #128] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #128] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #112] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #80] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #64] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #48] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #32] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #272] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl rintl
+; CHECK-i64-GI-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #256] // 16-byte Reload
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #240] // 16-byte Reload
+; CHECK-i64-GI-NEXT: str x0, [sp, #256] // 8-byte Spill
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #224] // 16-byte Reload
+; CHECK-i64-GI-NEXT: str x0, [sp, #272] // 8-byte Spill
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #208] // 16-byte Reload
+; CHECK-i64-GI-NEXT: str x0, [sp, #240] // 8-byte Spill
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #192] // 16-byte Reload
+; CHECK-i64-GI-NEXT: str x0, [sp, #224] // 8-byte Spill
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #176] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x24, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #160] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x23, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #144] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x25, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #128] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x26, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #112] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x27, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #96] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x28, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #80] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x29, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #64] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x19, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x20, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #32] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x21, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-i64-GI-NEXT: mov x22, x0
+; CHECK-i64-GI-NEXT: bl __fixtfdi
+; CHECK-i64-GI-NEXT: fmov d2, x24
+; CHECK-i64-GI-NEXT: fmov d3, x25
+; CHECK-i64-GI-NEXT: ldr d0, [sp, #256] // 8-byte Reload
+; CHECK-i64-GI-NEXT: fmov d4, x27
+; CHECK-i64-GI-NEXT: fmov d5, x29
+; CHECK-i64-GI-NEXT: ldr x8, [sp, #272] // 8-byte Reload
+; CHECK-i64-GI-NEXT: fmov d6, x20
+; CHECK-i64-GI-NEXT: fmov d7, x22
+; CHECK-i64-GI-NEXT: ldr d1, [sp, #240] // 8-byte Reload
+; CHECK-i64-GI-NEXT: mov v0.d[1], x8
+; CHECK-i64-GI-NEXT: ldr x8, [sp, #224] // 8-byte Reload
+; CHECK-i64-GI-NEXT: mov v2.d[1], x23
+; CHECK-i64-GI-NEXT: mov v3.d[1], x26
+; CHECK-i64-GI-NEXT: mov v4.d[1], x28
+; CHECK-i64-GI-NEXT: mov v5.d[1], x19
+; CHECK-i64-GI-NEXT: mov v6.d[1], x21
+; CHECK-i64-GI-NEXT: ldp x20, x19, [sp, #368] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: ldp x22, x21, [sp, #352] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: mov v1.d[1], x8
+; CHECK-i64-GI-NEXT: ldp x24, x23, [sp, #336] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: mov v7.d[1], x0
+; CHECK-i64-GI-NEXT: ldp x26, x25, [sp, #320] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: ldp x28, x27, [sp, #304] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload
+; CHECK-i64-GI-NEXT: add sp, sp, #384
+; CHECK-i64-GI-NEXT: ret
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16fp128(<16 x fp128> %x)
ret <16 x iXLen> %a
}
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