[llvm] [AArch64] Eliminate redundant setcc on vector comparison results (PR #171431)

[Valeriy Savchenko via llvm-commits]

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@@ -4746,6 +4746,19 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
     }
   }
 
+  // setcc X, 0, setlt --> X  (when X is all sign bits)
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SavchenkoValeriy wrote:

Do you mean this: https://github.com/llvm/llvm-project/blob/f3c16454b4f78f286e9b95a65b3c6be92465b948/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp#L4995-L5014
It seems not to be a perfect match IMO, just for the reason that I don't see how I can merge these two cases without making the logic awfully complicated. 

https://github.com/llvm/llvm-project/pull/171431