[llvm] [AArch64] Eliminate redundant setcc on vector comparison results (PR #171431)

[Matt Arsenault via llvm-commits]

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@@ -4746,6 +4746,19 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
     }
   }
 
+  // setcc X, 0, setlt --> X  (when X is all sign bits)
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arsenm wrote:

Isn't there already a similar check special cased for zero or one boolean content? Can these be merged? 

https://github.com/llvm/llvm-project/pull/171431