[llvm] [AMDGPU] Schedule independent instructions between s_barrier_signal and s_barrier_wait (PR #172057)

[Matt Arsenault via llvm-commits]

================
@@ -41,38 +51,58 @@ class BarrierLatency : public ScheduleDAGMutation {
   void apply(ScheduleDAGInstrs *DAG) override;
 };
 
+void addLatencyToEdge(SDep &PredDep, SUnit &SU, unsigned Latency) {
+  SUnit *PredSU = PredDep.getSUnit();
+  SDep ForwardD = PredDep;
+  ForwardD.setSUnit(&SU);
+  for (SDep &SuccDep : PredSU->Succs) {
+    if (SuccDep == ForwardD) {
+      SuccDep.setLatency(SuccDep.getLatency() + Latency);
+      break;
+    }
+  }
+  PredDep.setLatency(PredDep.getLatency() + Latency);
+  PredSU->setDepthDirty();
+  SU.setDepthDirty();
+}
+
 void BarrierLatency::apply(ScheduleDAGInstrs *DAG) {
-  constexpr unsigned SyntheticLatency = 2000;
+  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(DAG->TII);
+  constexpr unsigned FenceLatency = 2000;
----------------
arsenm wrote:

Should this come from the sched model for the barrier? I don't think this number agrees with what's there 

https://github.com/llvm/llvm-project/pull/172057