[llvm] [AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPTRUNC (PR #171723)

[Petar Avramovic via llvm-commits]

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@@ -260,6 +260,34 @@ bool AMDGPURegBankLegalizeCombiner::tryEliminateReadAnyLane(
     RALDst = SrcMI.getOperand(1).getReg();
 
   Register RALSrc = getReadAnyLaneSrc(RALDst);
+
+  // Sgpr0 = G_AMDGPU_READANYLANE Vgpr0
+  // Sgpr1 = G_AMDGPU_READANYLANE Vgpr1
+  // Sgpr2 = G_AMDGPU_READANYLANE Vgpr2
+  // ...
+  // Src = G_BUILD_VECTOR Sgpr0, Sgpr1, Sgpr2, ...
+  // Dst = COPY Src
+  // ->
+  // Dst = G_BUILD_VECTOR Vgpr0, Vgpr1, Vgpr2, ...
+  if (!RALSrc) {
+    if (auto *BV = getOpcodeDef<GBuildVector>(RALDst, MRI)) {
+      unsigned NumElts = BV->getNumSources();
+      SmallVector<Register, 4> VgprSrcs;
+      for (unsigned i = 0; i < NumElts; ++i) {
+        auto [RAL, VgprSrc] =
+            tryMatch(BV->getSourceReg(i), AMDGPU::G_AMDGPU_READANYLANE);
+        if (!RAL)
+          break;
+        VgprSrcs.push_back(VgprSrc);
+      }
+      if (VgprSrcs.size() == NumElts) {
+        B.setInstr(Copy);
+        LLT MergeTy = MRI.getType(BV->getReg(0));
+        RALSrc = B.buildBuildVector({VgprRB, MergeTy}, VgprSrcs).getReg(0);
+      }
+    }
+  }
+
   if (!RALSrc)
     return false;
----------------
petar-avramovic wrote:

Another suggestion, there is this combine in
  // LoVgpr, HiVgpr = G_UNMERGE_VALUES UnmergeSrc
  // LoSgpr = G_AMDGPU_READANYLANE LoVgpr
  // HiSgpr = G_AMDGPU_READANYLANE HiVgpr
  // Src G_MERGE_VALUES LoSgpr, HiSgpr
getReadAnyLaneSrc
same as what you are tying to do but there was no LoVgpr, HiVgpr = G_UNMERGE_VALUES UnmergeSrc
think you could rewrite them both to share most of the code (until you pick up all read any lane sources and store them in vector)
then you either find G_UNMERGE_VALUES or make new build vector. (Might need to buildMergeLikeInstr instead, since there is a possibility to have other types?)

https://github.com/llvm/llvm-project/pull/171723