[llvm] [AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPTRUNC (PR #171723)

[Petar Avramovic via llvm-commits]

================
@@ -260,6 +260,34 @@ bool AMDGPURegBankLegalizeCombiner::tryEliminateReadAnyLane(
     RALDst = SrcMI.getOperand(1).getReg();
 
   Register RALSrc = getReadAnyLaneSrc(RALDst);
+
+  // Sgpr0 = G_AMDGPU_READANYLANE Vgpr0
+  // Sgpr1 = G_AMDGPU_READANYLANE Vgpr1
+  // Sgpr2 = G_AMDGPU_READANYLANE Vgpr2
+  // ...
+  // Src = G_BUILD_VECTOR Sgpr0, Sgpr1, Sgpr2, ...
+  // Dst = COPY Src
+  // ->
+  // Dst = G_BUILD_VECTOR Vgpr0, Vgpr1, Vgpr2, ...
+  if (!RALSrc) {
+    if (auto *BV = getOpcodeDef<GBuildVector>(RALDst, MRI)) {
+      unsigned NumElts = BV->getNumSources();
+      SmallVector<Register, 4> VgprSrcs;
+      for (unsigned i = 0; i < NumElts; ++i) {
+        auto [RAL, VgprSrc] =
+            tryMatch(BV->getSourceReg(i), AMDGPU::G_AMDGPU_READANYLANE);
+        if (!RAL)
+          break;
+        VgprSrcs.push_back(VgprSrc);
+      }
+      if (VgprSrcs.size() == NumElts) {
+        B.setInstr(Copy);
+        LLT MergeTy = MRI.getType(BV->getReg(0));
+        RALSrc = B.buildBuildVector({VgprRB, MergeTy}, VgprSrcs).getReg(0);
+      }
+    }
+  }
+
   if (!RALSrc)
     return false;
----------------
petar-avramovic wrote:

Is there a reason to name new instruction RALSrc and use G_BITCAST check below? Maybe
```suggestion
        auto VgprBV = B.buildBuildVector({VgprRB, MergeTy}, VgprSrcs);
        replaceRegWithOrBuildCopy(Dst, VgprBV.getReg(0));
        eraseInstr(Copy, MRI);
        return true;
      }
    }
    return false;
  }
```
but think it would be better to extract this section to helper function and have indicated in the name that it makes new buildvector

https://github.com/llvm/llvm-project/pull/171723