[llvm] [AMDGPU] Add register pressure guard on LLVM-IR level to prevent harmful optimizations (PR #171267)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm requested changes to this pull request.

I don't think this is a reasonable strategy to pursue. This is heavy handed hack. Letting optimizations proceed, and rolling them back is not the way to approach this.

The IR can't have that great of a notion of the register pressure to start with. I'd rather have the effort put into improving codegen sinking. I do think many of our late sinking problems can be solved by running machine optimizations on gMIR in global isel 

https://github.com/llvm/llvm-project/pull/171267