[llvm] [RISCV] Combine (addi (addi)) and add post riscv-opt-w-instrs machine-combiner (PR #171165)

[Piotr Fusik via llvm-commits]

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@@ -1071,19 +1071,33 @@ define double @test_fmax_f64(double %a0, double %a1, double %a2, double %a3) {
 }
 
 define double @test_fmadd_strategy(double %a0, double %a1, double %a2, double %a3, i64 %flag) {
-; CHECK-LABEL: test_fmadd_strategy:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    fsub.d fa5, fa0, fa1
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    beqz a0, .LBB76_2
-; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    fmul.d fa4, fa0, fa1
-; CHECK-NEXT:    fmadd.d fa5, fa5, fa2, fa4
-; CHECK-NEXT:    fsub.d fa0, fa5, fa4
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB76_2:
-; CHECK-NEXT:    fmul.d fa0, fa5, fa2
-; CHECK-NEXT:    ret
+; CHECK_LOCAL-LABEL: test_fmadd_strategy:
+; CHECK_LOCAL:       # %bb.0: # %entry
+; CHECK_LOCAL-NEXT:    fsub.d fa4, fa0, fa1
+; CHECK_LOCAL-NEXT:    andi a0, a0, 1
+; CHECK_LOCAL-NEXT:    fmv.d fa5, fa0
+; CHECK_LOCAL-NEXT:    fmul.d fa0, fa4, fa2
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pfusik wrote:

These two `fmul.d`s in a row look like it might be worse.

https://github.com/llvm/llvm-project/pull/171165