[llvm] [RISCV] Combine (addi (addi)) and add post riscv-opt-w-instrs machine-combiner (PR #171165)
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llvm-commits at lists.llvm.org
Mon Dec 8 09:50:53 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Piotr Fusik (pfusik)
<details>
<summary>Changes</summary>
The inner ADDI can be ADDIW until riscv-opt-w-instrs.
Likewise, riscv-opt-w-instrs enables some SHXADD combines.
---
Patch is 62.16 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/171165.diff
16 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+43)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+1)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+1)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/O3-pipeline.ll (+3)
- (modified) llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll (+26-26)
- (modified) llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll (+98-98)
- (modified) llvm/test/CodeGen/RISCV/mul-expand.ll (+92-92)
- (modified) llvm/test/CodeGen/RISCV/rv64xtheadbb.ll (+53-53)
- (modified) llvm/test/CodeGen/RISCV/rv64zba.ll (+31-2)
- (modified) llvm/test/CodeGen/RISCV/rv64zbb.ll (+53-53)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll (+211-108)
- (modified) llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll (+13-13)
- (modified) llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll (+58-58)
- (modified) llvm/test/CodeGen/RISCV/zicond-opts.ll (+55)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index a3bacfbfe5214..37dec648b6b53 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2654,6 +2654,22 @@ static bool getSHXADDPatterns(const MachineInstr &Root,
return Found;
}
+// Check (addi (addi X, C1), C2) -> (addi X, C1+C2) pattern.
+static bool getADDIADDIPatterns(const MachineInstr &Root,
+ SmallVectorImpl<unsigned> &Patterns) {
+ if (Root.getOpcode() != RISCV::ADDI)
+ return false;
+ const MachineBasicBlock &MBB = *Root.getParent();
+ const MachineInstr *Inner = canCombine(MBB, Root.getOperand(1), RISCV::ADDI);
+ if (!Inner || !Inner->getOperand(1).isReg())
+ return false;
+ int64_t Sum = Inner->getOperand(2).getImm() + Root.getOperand(2).getImm();
+ if (!isInt<12>(Sum))
+ return false;
+ Patterns.push_back(RISCVMachineCombinerPattern::ADDI_ADDI);
+ return true;
+}
+
CombinerObjective RISCVInstrInfo::getCombinerObjective(unsigned Pattern) const {
switch (Pattern) {
case RISCVMachineCombinerPattern::FMADD_AX:
@@ -2676,6 +2692,9 @@ bool RISCVInstrInfo::getMachineCombinerPatterns(
if (getSHXADDPatterns(Root, Patterns))
return true;
+ if (getADDIADDIPatterns(Root, Patterns))
+ return true;
+
return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns,
DoRegPressureReduce);
}
@@ -2819,6 +2838,27 @@ genShXAddAddShift(MachineInstr &Root, unsigned AddOpIdx,
DelInstrs.push_back(&Root);
}
+// Fold (addi (addi X, C1), C2) -> (addi X, C1+C2)
+static void combineADDIADDI(MachineInstr &Root,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ SmallVectorImpl<MachineInstr *> &DelInstrs) {
+ MachineFunction *MF = Root.getMF();
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+ const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
+
+ MachineInstr *Inner = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
+ const MachineOperand &X = Inner->getOperand(1);
+ int64_t Sum = Inner->getOperand(2).getImm() + Root.getOperand(2).getImm();
+
+ auto MIB = BuildMI(*MF, MIMetadata(Root), TII->get(RISCV::ADDI),
+ Root.getOperand(0).getReg())
+ .addReg(X.getReg(), getKillRegState(X.isKill()))
+ .addImm(Sum);
+ InsInstrs.push_back(MIB);
+ DelInstrs.push_back(Inner);
+ DelInstrs.push_back(&Root);
+}
+
void RISCVInstrInfo::genAlternativeCodeSequence(
MachineInstr &Root, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
@@ -2848,6 +2888,9 @@ void RISCVInstrInfo::genAlternativeCodeSequence(
case RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP2:
genShXAddAddShift(Root, 2, InsInstrs, DelInstrs, InstrIdxForVirtReg);
return;
+ case RISCVMachineCombinerPattern::ADDI_ADDI:
+ combineADDIADDI(Root, InsInstrs, DelInstrs);
+ return;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 0ffe015b9fac8..2f91dd4698a84 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -76,6 +76,7 @@ enum RISCVMachineCombinerPattern : unsigned {
FNMSUB,
SHXADD_ADD_SLLI_OP1,
SHXADD_ADD_SLLI_OP2,
+ ADDI_ADDI,
};
class RISCVInstrInfo : public RISCVGenInstrInfo {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 52dc38564059c..e461cc3fab8b4 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -597,6 +597,7 @@ void RISCVPassConfig::addMachineSSAOptimization() {
if (TM->getTargetTriple().isRISCV64()) {
addPass(createRISCVOptWInstrsPass());
+ addILPOpts();
}
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
index 01d9ceb0a0860..5351061273676 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
@@ -1235,12 +1235,12 @@ define i1 @fpclass(float %x) {
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: seqz a6, a6
-; RV64I-NEXT: sltu a4, a5, a4
-; RV64I-NEXT: and a3, a3, a0
-; RV64I-NEXT: or a2, a2, a6
; RV64I-NEXT: or a1, a2, a1
+; RV64I-NEXT: sltu a2, a5, a4
+; RV64I-NEXT: and a3, a3, a0
+; RV64I-NEXT: or a1, a1, a6
; RV64I-NEXT: or a1, a1, a3
-; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: and a0, a2, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
%cmp = call i1 @llvm.is.fpclass.f32(float %x, i32 639)
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 85027a56a1348..325d69f91b2c4 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -124,6 +124,9 @@
; CHECK-NEXT: Peephole Optimizations
; CHECK-NEXT: Remove dead machine instructions
; RV64-NEXT: RISC-V Optimize W Instructions
+; RV64-NEXT: Machine Trace Metrics
+; RV64-NEXT: Lazy Machine Block Frequency Analysis
+; RV64-NEXT: Machine InstCombiner
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
; CHECK-NEXT: RISC-V Merge Base Offset
; CHECK-NEXT: MachineDominator Tree Construction
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
index a63dc0ef3a3a7..066379501e3c2 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
@@ -53,12 +53,12 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f,
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: slli a1, a1, 48
; RV64I-NEXT: xor a3, a3, a7
+; RV64I-NEXT: add a5, a5, a6
; RV64I-NEXT: srli a1, a1, 48
; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: add a0, a0, a5
; RV64I-NEXT: xor a1, a4, t1
-; RV64I-NEXT: add a0, a0, a6
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: seqz a1, a1
; RV64I-NEXT: add a0, a0, t0
diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
index 976c57e422761..1e2bfccdb0a14 100644
--- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
@@ -255,23 +255,23 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI2_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI2_0)
; RV64I-NEXT: add a0, a1, a0
@@ -736,23 +736,23 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
; RV64I-NEXT: add a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll b/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
index e92ff1a1b1b40..660bc5e7a9354 100644
--- a/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
+++ b/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
@@ -166,23 +166,23 @@ define i64 @ctz_dereferencing_pointer_zext(ptr %b) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI1_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI1_0)
; RV64I-NEXT: add a1, a2, a1
@@ -248,23 +248,23 @@ define signext i32 @ctz1(i32 signext %x) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI2_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI2_0)
; RV64I-NEXT: add a1, a2, a1
@@ -328,23 +328,23 @@ define signext i32 @ctz1_flipped(i32 signext %x) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI3_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI3_0)
; RV64I-NEXT: add a1, a2, a1
@@ -406,23 +406,23 @@ define signext i32 @ctz2(i32 signext %x) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI4_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI4_0)
; RV64I-NEXT: add a0, a1, a0
@@ -481,23 +481,23 @@ define signext i32 @ctz3(i32 signext %x) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI5_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI5_0)
; RV64I-NEXT: add a0, a1, a0
@@ -806,23 +806,23 @@ define signext i32 @ctz5(i32 signext %x) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI8_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI8_0)
; RV64I-NEXT: add a1, a2, a1
@@ -886,23 +886,23 @@ define signext i32 @ctz6(i32 signext %x) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI9_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI9_0)
; RV64I-NEXT: add a1, a2, a1
@@ -973,23 +973,23 @@ define signext i32 @globalVar() nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI10_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI10_0)
; RV64I-NEXT: add a1, a2, a1
diff --git a/llvm/test/CodeGen/RISCV/mul-expand.ll b/llvm/test/CodeGen/RISCV/mul-expand.ll
index a75a7355fa407..9e02af9581c83 100644
--- a/llvm/test/CodeGen/RISCV/mul-expand.ll
+++ b/llvm/test/CodeGen/RISCV/mul-expand.ll
@@ -107,31 +107,31 @@ define i32 @muli32_0x33333333(i32 %a) nounwind {
; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: slli a4, a0, 10
; RV64I-NEXT: slli a5, a0, 14
+; RV64I-NEXT: slli a6, a0, 16
+; RV64I-NEXT: slli a7, a0, 18
; RV64I-NEXT: sub a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
+; RV64I-NEXT: slli a2, a0, 20
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 22
-; RV64I-NEXT: sub a5, a5, a2
-; RV64I-NEXT: slli a2, a0, 24
-; RV64I-NEXT: sub a4, a4, a2
-; RV64I-NEXT: slli a2, a0, 2
-; RV64I-NEXT: sub a2, a2, a0
-; RV64I-NEXT: sub a2, a2, a1
-; RV64I-NEXT: slli a1, a0, 12
-; RV64I-NEXT: add a1, a3, a1
-; RV64...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/171165
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