[llvm] [RISCV] Combine (addi (addi)) and add post riscv-opt-w-instrs machine-combiner (PR #171165)
Piotr Fusik via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 8 09:50:18 PST 2025
https://github.com/pfusik created https://github.com/llvm/llvm-project/pull/171165
The inner ADDI can be ADDIW until riscv-opt-w-instrs.
Likewise, riscv-opt-w-instrs enables some SHXADD combines.
>From 10731b2d496b7499c1af1e30c96b124d702d2870 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Mon, 8 Dec 2025 18:07:00 +0100
Subject: [PATCH 1/4] [RISCV][test] Add tests for (addi (addi X, C1), C2) ->
(addi X, C1+C2) combines
---
llvm/test/CodeGen/RISCV/zicond-opts.ll | 58 ++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/zicond-opts.ll b/llvm/test/CodeGen/RISCV/zicond-opts.ll
index c6d72981eff32..fdf631e5faac8 100644
--- a/llvm/test/CodeGen/RISCV/zicond-opts.ll
+++ b/llvm/test/CodeGen/RISCV/zicond-opts.ll
@@ -401,3 +401,61 @@ entry:
%clzg = select i1 %iszero, i32 -9, i32 %cast
ret i32 %clzg
}
+
+define i32 @addi_addi(i1 %a, i16 %b) {
+; RV32ZICOND-LABEL: addi_addi:
+; RV32ZICOND: # %bb.0:
+; RV32ZICOND-NEXT: andi a0, a0, 1
+; RV32ZICOND-NEXT: bset a1, zero, a1
+; RV32ZICOND-NEXT: addi a1, a1, -1
+; RV32ZICOND-NEXT: addi a1, a1, -1
+; RV32ZICOND-NEXT: czero.nez a0, a1, a0
+; RV32ZICOND-NEXT: addi a0, a0, 1
+; RV32ZICOND-NEXT: ret
+;
+; RV64ZICOND-LABEL: addi_addi:
+; RV64ZICOND: # %bb.0:
+; RV64ZICOND-NEXT: andi a0, a0, 1
+; RV64ZICOND-NEXT: bset a1, zero, a1
+; RV64ZICOND-NEXT: addi a1, a1, -1
+; RV64ZICOND-NEXT: addi a1, a1, -1
+; RV64ZICOND-NEXT: czero.nez a0, a1, a0
+; RV64ZICOND-NEXT: addi a0, a0, 1
+; RV64ZICOND-NEXT: ret
+ %zext = zext nneg i16 %b to i32
+ %shl = shl nsw i32 -1, %zext
+ %xor = xor i32 %shl, -1
+ %select = select i1 %a, i32 1, i32 %xor
+ ret i32 %select
+}
+
+define i64 @addiw_addi(i32 %x) {
+; RV32ZICOND-LABEL: addiw_addi:
+; RV32ZICOND: # %bb.0:
+; RV32ZICOND-NEXT: addi a1, a0, -64
+; RV32ZICOND-NEXT: czero.eqz a0, a1, a0
+; RV32ZICOND-NEXT: addi a1, a0, 63
+; RV32ZICOND-NEXT: addi a0, a0, 31
+; RV32ZICOND-NEXT: srli a2, a0, 31
+; RV32ZICOND-NEXT: bset a1, zero, a1
+; RV32ZICOND-NEXT: bset a3, zero, a0
+; RV32ZICOND-NEXT: czero.eqz a0, a1, a2
+; RV32ZICOND-NEXT: czero.nez a1, a3, a2
+; RV32ZICOND-NEXT: ret
+;
+; RV64ZICOND-LABEL: addiw_addi:
+; RV64ZICOND: # %bb.0:
+; RV64ZICOND-NEXT: sext.w a1, a0
+; RV64ZICOND-NEXT: addi a0, a0, -1
+; RV64ZICOND-NEXT: addi a0, a0, -63
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a1
+; RV64ZICOND-NEXT: addi a0, a0, 63
+; RV64ZICOND-NEXT: bset a0, zero, a0
+; RV64ZICOND-NEXT: ret
+ %add = add i32 %x, -1
+ %icmp = icmp eq i32 %x, 0
+ %select = select i1 %icmp, i32 63, i32 %add
+ %zext= zext nneg i32 %select to i64
+ %shl = shl nuw i64 1, %zext
+ ret i64 %shl
+}
>From 94430e2ee057a9e7110042713f980d4c4215c68a Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Mon, 8 Dec 2025 18:09:28 +0100
Subject: [PATCH 2/4] [RISCV][test] Add a test for post opt-w-instrs
MachineCombiner
---
llvm/test/CodeGen/RISCV/rv64zba.ll | 31 ++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index fb26b8b16a290..4af605472220a 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -5087,3 +5087,34 @@ define i64 @exactashr1mul36(i64 %a) {
%d = mul i64 %c, 36
ret i64 %d
}
+
+define i32 @shl_add_shl_add(i32 %a, i32 %b, i32 %c) {
+; RV64I-LABEL: shl_add_shl_add:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a2, a2, 5
+; RV64I-NEXT: add a1, a1, a2
+; RV64I-NEXT: slli a0, a0, 3
+; RV64I-NEXT: addw a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: shl_add_shl_add:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a2, a2, 5
+; RV64ZBA-NEXT: add a1, a1, a2
+; RV64ZBA-NEXT: sh3add a0, a0, a1
+; RV64ZBA-NEXT: sext.w a0, a0
+; RV64ZBA-NEXT: ret
+;
+; RV64XANDESPERF-LABEL: shl_add_shl_add:
+; RV64XANDESPERF: # %bb.0:
+; RV64XANDESPERF-NEXT: slli a2, a2, 5
+; RV64XANDESPERF-NEXT: add a1, a1, a2
+; RV64XANDESPERF-NEXT: nds.lea.d a0, a1, a0
+; RV64XANDESPERF-NEXT: sext.w a0, a0
+; RV64XANDESPERF-NEXT: ret
+ %shl = shl nsw i32 %c, 5
+ %add = add i32 %b, %shl
+ %shl2 = shl nuw nsw i32 %a, 3
+ %add2= add i32 %shl2, %add
+ ret i32 %add2
+}
>From ea5d1fefe8dd8d960a3b2a78b8af9201d1de5f4c Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Mon, 8 Dec 2025 18:10:56 +0100
Subject: [PATCH 3/4] [RISCV] Combine (addi (addi X, C1), C2) -> (addi X,
C1+C2)
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 43 ++++++++++++++++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 1 +
llvm/test/CodeGen/RISCV/rv64zba.ll | 3 +-
llvm/test/CodeGen/RISCV/zicond-opts.ll | 6 ++--
4 files changed, 47 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index a3bacfbfe5214..37dec648b6b53 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2654,6 +2654,22 @@ static bool getSHXADDPatterns(const MachineInstr &Root,
return Found;
}
+// Check (addi (addi X, C1), C2) -> (addi X, C1+C2) pattern.
+static bool getADDIADDIPatterns(const MachineInstr &Root,
+ SmallVectorImpl<unsigned> &Patterns) {
+ if (Root.getOpcode() != RISCV::ADDI)
+ return false;
+ const MachineBasicBlock &MBB = *Root.getParent();
+ const MachineInstr *Inner = canCombine(MBB, Root.getOperand(1), RISCV::ADDI);
+ if (!Inner || !Inner->getOperand(1).isReg())
+ return false;
+ int64_t Sum = Inner->getOperand(2).getImm() + Root.getOperand(2).getImm();
+ if (!isInt<12>(Sum))
+ return false;
+ Patterns.push_back(RISCVMachineCombinerPattern::ADDI_ADDI);
+ return true;
+}
+
CombinerObjective RISCVInstrInfo::getCombinerObjective(unsigned Pattern) const {
switch (Pattern) {
case RISCVMachineCombinerPattern::FMADD_AX:
@@ -2676,6 +2692,9 @@ bool RISCVInstrInfo::getMachineCombinerPatterns(
if (getSHXADDPatterns(Root, Patterns))
return true;
+ if (getADDIADDIPatterns(Root, Patterns))
+ return true;
+
return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns,
DoRegPressureReduce);
}
@@ -2819,6 +2838,27 @@ genShXAddAddShift(MachineInstr &Root, unsigned AddOpIdx,
DelInstrs.push_back(&Root);
}
+// Fold (addi (addi X, C1), C2) -> (addi X, C1+C2)
+static void combineADDIADDI(MachineInstr &Root,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ SmallVectorImpl<MachineInstr *> &DelInstrs) {
+ MachineFunction *MF = Root.getMF();
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+ const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
+
+ MachineInstr *Inner = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
+ const MachineOperand &X = Inner->getOperand(1);
+ int64_t Sum = Inner->getOperand(2).getImm() + Root.getOperand(2).getImm();
+
+ auto MIB = BuildMI(*MF, MIMetadata(Root), TII->get(RISCV::ADDI),
+ Root.getOperand(0).getReg())
+ .addReg(X.getReg(), getKillRegState(X.isKill()))
+ .addImm(Sum);
+ InsInstrs.push_back(MIB);
+ DelInstrs.push_back(Inner);
+ DelInstrs.push_back(&Root);
+}
+
void RISCVInstrInfo::genAlternativeCodeSequence(
MachineInstr &Root, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
@@ -2848,6 +2888,9 @@ void RISCVInstrInfo::genAlternativeCodeSequence(
case RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP2:
genShXAddAddShift(Root, 2, InsInstrs, DelInstrs, InstrIdxForVirtReg);
return;
+ case RISCVMachineCombinerPattern::ADDI_ADDI:
+ combineADDIADDI(Root, InsInstrs, DelInstrs);
+ return;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 0ffe015b9fac8..2f91dd4698a84 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -76,6 +76,7 @@ enum RISCVMachineCombinerPattern : unsigned {
FNMSUB,
SHXADD_ADD_SLLI_OP1,
SHXADD_ADD_SLLI_OP2,
+ ADDI_ADDI,
};
class RISCVInstrInfo : public RISCVGenInstrInfo {
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index 4af605472220a..0afd6f5727934 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -4609,8 +4609,7 @@ define i64 @add_u32simm32_zextw(i64 %x) nounwind {
; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a1
; RV64XANDESPERF-NEXT: li a1, 1
; RV64XANDESPERF-NEXT: slli a1, a1, 32
-; RV64XANDESPERF-NEXT: addi a1, a1, -2
-; RV64XANDESPERF-NEXT: addi a1, a1, 1
+; RV64XANDESPERF-NEXT: addi a1, a1, -1
; RV64XANDESPERF-NEXT: and a0, a0, a1
; RV64XANDESPERF-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/zicond-opts.ll b/llvm/test/CodeGen/RISCV/zicond-opts.ll
index fdf631e5faac8..47ff6edb0499d 100644
--- a/llvm/test/CodeGen/RISCV/zicond-opts.ll
+++ b/llvm/test/CodeGen/RISCV/zicond-opts.ll
@@ -407,8 +407,7 @@ define i32 @addi_addi(i1 %a, i16 %b) {
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: andi a0, a0, 1
; RV32ZICOND-NEXT: bset a1, zero, a1
-; RV32ZICOND-NEXT: addi a1, a1, -1
-; RV32ZICOND-NEXT: addi a1, a1, -1
+; RV32ZICOND-NEXT: addi a1, a1, -2
; RV32ZICOND-NEXT: czero.nez a0, a1, a0
; RV32ZICOND-NEXT: addi a0, a0, 1
; RV32ZICOND-NEXT: ret
@@ -417,8 +416,7 @@ define i32 @addi_addi(i1 %a, i16 %b) {
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: andi a0, a0, 1
; RV64ZICOND-NEXT: bset a1, zero, a1
-; RV64ZICOND-NEXT: addi a1, a1, -1
-; RV64ZICOND-NEXT: addi a1, a1, -1
+; RV64ZICOND-NEXT: addi a1, a1, -2
; RV64ZICOND-NEXT: czero.nez a0, a1, a0
; RV64ZICOND-NEXT: addi a0, a0, 1
; RV64ZICOND-NEXT: ret
>From dbb75f0c6c6408fb2a2b02171a69de25dd4c2aa5 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Mon, 8 Dec 2025 18:12:44 +0100
Subject: [PATCH 4/4] [RISCV] Add post opt-w-instrs MachineCombiner
---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 1 +
.../RISCV/GlobalISel/float-intrinsics.ll | 8 +-
llvm/test/CodeGen/RISCV/O3-pipeline.ll | 3 +
.../calling-conv-lp64-lp64f-lp64d-common.ll | 2 +-
llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll | 52 +--
.../CodeGen/RISCV/ctz_zero_return_test.ll | 196 +++++------
llvm/test/CodeGen/RISCV/mul-expand.ll | 184 +++++-----
llvm/test/CodeGen/RISCV/rv64xtheadbb.ll | 106 +++---
llvm/test/CodeGen/RISCV/rv64zba.ll | 3 +-
llvm/test/CodeGen/RISCV/rv64zbb.ll | 106 +++---
.../rvv/fixed-vectors-int-explodevector.ll | 319 ++++++++++++------
.../CodeGen/RISCV/rvv/known-never-zero.ll | 26 +-
.../CodeGen/RISCV/srem-seteq-illegal-types.ll | 116 +++----
llvm/test/CodeGen/RISCV/zicond-opts.ll | 3 +-
14 files changed, 615 insertions(+), 510 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 52dc38564059c..e461cc3fab8b4 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -597,6 +597,7 @@ void RISCVPassConfig::addMachineSSAOptimization() {
if (TM->getTargetTriple().isRISCV64()) {
addPass(createRISCVOptWInstrsPass());
+ addILPOpts();
}
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
index 01d9ceb0a0860..5351061273676 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
@@ -1235,12 +1235,12 @@ define i1 @fpclass(float %x) {
; RV64I-NEXT: seqz a2, a2
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: seqz a6, a6
-; RV64I-NEXT: sltu a4, a5, a4
-; RV64I-NEXT: and a3, a3, a0
-; RV64I-NEXT: or a2, a2, a6
; RV64I-NEXT: or a1, a2, a1
+; RV64I-NEXT: sltu a2, a5, a4
+; RV64I-NEXT: and a3, a3, a0
+; RV64I-NEXT: or a1, a1, a6
; RV64I-NEXT: or a1, a1, a3
-; RV64I-NEXT: and a0, a4, a0
+; RV64I-NEXT: and a0, a2, a0
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
%cmp = call i1 @llvm.is.fpclass.f32(float %x, i32 639)
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 85027a56a1348..325d69f91b2c4 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -124,6 +124,9 @@
; CHECK-NEXT: Peephole Optimizations
; CHECK-NEXT: Remove dead machine instructions
; RV64-NEXT: RISC-V Optimize W Instructions
+; RV64-NEXT: Machine Trace Metrics
+; RV64-NEXT: Lazy Machine Block Frequency Analysis
+; RV64-NEXT: Machine InstCombiner
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
; CHECK-NEXT: RISC-V Merge Base Offset
; CHECK-NEXT: MachineDominator Tree Construction
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
index a63dc0ef3a3a7..066379501e3c2 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
@@ -53,12 +53,12 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f,
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: slli a1, a1, 48
; RV64I-NEXT: xor a3, a3, a7
+; RV64I-NEXT: add a5, a5, a6
; RV64I-NEXT: srli a1, a1, 48
; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: add a0, a0, a5
; RV64I-NEXT: xor a1, a4, t1
-; RV64I-NEXT: add a0, a0, a6
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: seqz a1, a1
; RV64I-NEXT: add a0, a0, t0
diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
index 976c57e422761..1e2bfccdb0a14 100644
--- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
@@ -255,23 +255,23 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI2_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI2_0)
; RV64I-NEXT: add a0, a1, a0
@@ -736,23 +736,23 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
; RV64I-NEXT: add a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll b/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
index e92ff1a1b1b40..660bc5e7a9354 100644
--- a/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
+++ b/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
@@ -166,23 +166,23 @@ define i64 @ctz_dereferencing_pointer_zext(ptr %b) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI1_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI1_0)
; RV64I-NEXT: add a1, a2, a1
@@ -248,23 +248,23 @@ define signext i32 @ctz1(i32 signext %x) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI2_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI2_0)
; RV64I-NEXT: add a1, a2, a1
@@ -328,23 +328,23 @@ define signext i32 @ctz1_flipped(i32 signext %x) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI3_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI3_0)
; RV64I-NEXT: add a1, a2, a1
@@ -406,23 +406,23 @@ define signext i32 @ctz2(i32 signext %x) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI4_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI4_0)
; RV64I-NEXT: add a0, a1, a0
@@ -481,23 +481,23 @@ define signext i32 @ctz3(i32 signext %x) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI5_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI5_0)
; RV64I-NEXT: add a0, a1, a0
@@ -806,23 +806,23 @@ define signext i32 @ctz5(i32 signext %x) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI8_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI8_0)
; RV64I-NEXT: add a1, a2, a1
@@ -886,23 +886,23 @@ define signext i32 @ctz6(i32 signext %x) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI9_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI9_0)
; RV64I-NEXT: add a1, a2, a1
@@ -973,23 +973,23 @@ define signext i32 @globalVar() nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI10_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI10_0)
; RV64I-NEXT: add a1, a2, a1
diff --git a/llvm/test/CodeGen/RISCV/mul-expand.ll b/llvm/test/CodeGen/RISCV/mul-expand.ll
index a75a7355fa407..9e02af9581c83 100644
--- a/llvm/test/CodeGen/RISCV/mul-expand.ll
+++ b/llvm/test/CodeGen/RISCV/mul-expand.ll
@@ -107,31 +107,31 @@ define i32 @muli32_0x33333333(i32 %a) nounwind {
; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: slli a4, a0, 10
; RV64I-NEXT: slli a5, a0, 14
+; RV64I-NEXT: slli a6, a0, 16
+; RV64I-NEXT: slli a7, a0, 18
; RV64I-NEXT: sub a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
+; RV64I-NEXT: slli a2, a0, 20
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 22
-; RV64I-NEXT: sub a5, a5, a2
-; RV64I-NEXT: slli a2, a0, 24
-; RV64I-NEXT: sub a4, a4, a2
-; RV64I-NEXT: slli a2, a0, 2
-; RV64I-NEXT: sub a2, a2, a0
-; RV64I-NEXT: sub a2, a2, a1
-; RV64I-NEXT: slli a1, a0, 12
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: slli a3, a0, 18
-; RV64I-NEXT: add a3, a5, a3
-; RV64I-NEXT: slli a5, a0, 26
-; RV64I-NEXT: add a4, a4, a5
-; RV64I-NEXT: sub a2, a2, a1
-; RV64I-NEXT: slli a1, a0, 20
-; RV64I-NEXT: sub a3, a3, a1
-; RV64I-NEXT: slli a1, a0, 28
-; RV64I-NEXT: sub a4, a4, a1
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a0, 24
+; RV64I-NEXT: sub a2, a7, a2
+; RV64I-NEXT: slli a7, a0, 26
+; RV64I-NEXT: sub a4, a4, a6
+; RV64I-NEXT: slli a6, a0, 28
+; RV64I-NEXT: sub a6, a7, a6
+; RV64I-NEXT: slli a7, a0, 2
+; RV64I-NEXT: sub a7, a7, a0
+; RV64I-NEXT: sub a1, a7, a1
+; RV64I-NEXT: slli a7, a0, 12
+; RV64I-NEXT: add a3, a3, a7
+; RV64I-NEXT: add a2, a5, a2
+; RV64I-NEXT: add a4, a4, a6
; RV64I-NEXT: slli a0, a0, 30
-; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: sub a1, a1, a3
+; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: add a0, a4, a0
-; RV64I-NEXT: add a0, a2, a0
+; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
%a1 = mul i32 %a, 858993459
ret i32 %a1
@@ -157,31 +157,31 @@ define i64 @muli64_0x33333333(i64 %a) nounwind {
; RV64I-NEXT: slli a3, a0, 8
; RV64I-NEXT: slli a4, a0, 10
; RV64I-NEXT: slli a5, a0, 14
+; RV64I-NEXT: slli a6, a0, 16
+; RV64I-NEXT: slli a7, a0, 18
; RV64I-NEXT: sub a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
+; RV64I-NEXT: slli a2, a0, 20
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 22
-; RV64I-NEXT: sub a5, a5, a2
-; RV64I-NEXT: slli a2, a0, 24
-; RV64I-NEXT: sub a4, a4, a2
-; RV64I-NEXT: slli a2, a0, 2
-; RV64I-NEXT: sub a2, a2, a0
-; RV64I-NEXT: sub a2, a2, a1
-; RV64I-NEXT: slli a1, a0, 12
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: slli a3, a0, 18
-; RV64I-NEXT: add a3, a5, a3
-; RV64I-NEXT: slli a5, a0, 26
-; RV64I-NEXT: add a4, a4, a5
-; RV64I-NEXT: sub a2, a2, a1
-; RV64I-NEXT: slli a1, a0, 20
-; RV64I-NEXT: sub a3, a3, a1
-; RV64I-NEXT: slli a1, a0, 28
-; RV64I-NEXT: sub a4, a4, a1
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a0, 24
+; RV64I-NEXT: sub a2, a7, a2
+; RV64I-NEXT: slli a7, a0, 26
+; RV64I-NEXT: sub a4, a4, a6
+; RV64I-NEXT: slli a6, a0, 28
+; RV64I-NEXT: sub a6, a7, a6
+; RV64I-NEXT: slli a7, a0, 2
+; RV64I-NEXT: sub a7, a7, a0
+; RV64I-NEXT: sub a1, a7, a1
+; RV64I-NEXT: slli a7, a0, 12
+; RV64I-NEXT: add a3, a3, a7
+; RV64I-NEXT: add a2, a5, a2
+; RV64I-NEXT: add a4, a4, a6
; RV64I-NEXT: slli a0, a0, 30
-; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: sub a1, a1, a3
+; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: add a0, a4, a0
-; RV64I-NEXT: add a0, a2, a0
+; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
%a1 = mul i64 %a, 858993459
ret i64 %a1
@@ -231,30 +231,30 @@ define i32 @muli32_0xaaaaaaaa(i32 %a) nounwind {
; RV64I-NEXT: slli a4, a0, 7
; RV64I-NEXT: slli a5, a0, 9
; RV64I-NEXT: slli a6, a0, 11
+; RV64I-NEXT: slli a7, a0, 15
+; RV64I-NEXT: slli t0, a0, 17
; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: slli a2, a0, 15
+; RV64I-NEXT: slli a2, a0, 19
; RV64I-NEXT: add a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 17
+; RV64I-NEXT: slli a4, a0, 21
; RV64I-NEXT: add a5, a5, a6
; RV64I-NEXT: slli a6, a0, 23
+; RV64I-NEXT: add a7, a7, t0
+; RV64I-NEXT: slli t0, a0, 25
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 25
-; RV64I-NEXT: add a4, a6, a4
+; RV64I-NEXT: slli a4, a0, 27
+; RV64I-NEXT: add a6, a6, t0
+; RV64I-NEXT: slli t0, a0, 29
+; RV64I-NEXT: add a4, a4, t0
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: slli a3, a0, 13
; RV64I-NEXT: add a3, a5, a3
-; RV64I-NEXT: slli a5, a0, 19
-; RV64I-NEXT: add a2, a2, a5
-; RV64I-NEXT: slli a5, a0, 27
-; RV64I-NEXT: add a4, a4, a5
-; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: slli a3, a0, 21
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a0, 29
-; RV64I-NEXT: add a3, a4, a3
+; RV64I-NEXT: add a2, a7, a2
+; RV64I-NEXT: add a4, a6, a4
; RV64I-NEXT: slli a0, a0, 31
+; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: sub a0, a3, a0
+; RV64I-NEXT: sub a0, a4, a0
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
%a1 = mul i32 %a, -1431655766
@@ -282,30 +282,30 @@ define i64 @muli64_0xaaaaaaaa(i64 %a) nounwind {
; RV64I-NEXT: slli a4, a0, 7
; RV64I-NEXT: slli a5, a0, 9
; RV64I-NEXT: slli a6, a0, 11
+; RV64I-NEXT: slli a7, a0, 15
+; RV64I-NEXT: slli t0, a0, 17
; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: slli a2, a0, 15
+; RV64I-NEXT: slli a2, a0, 19
; RV64I-NEXT: add a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 17
+; RV64I-NEXT: slli a4, a0, 21
; RV64I-NEXT: add a5, a5, a6
; RV64I-NEXT: slli a6, a0, 23
+; RV64I-NEXT: add a7, a7, t0
+; RV64I-NEXT: slli t0, a0, 25
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 25
-; RV64I-NEXT: add a4, a6, a4
+; RV64I-NEXT: slli a4, a0, 27
+; RV64I-NEXT: add a6, a6, t0
+; RV64I-NEXT: slli t0, a0, 29
+; RV64I-NEXT: add a4, a4, t0
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: slli a3, a0, 13
; RV64I-NEXT: add a3, a5, a3
-; RV64I-NEXT: slli a5, a0, 19
-; RV64I-NEXT: add a2, a2, a5
-; RV64I-NEXT: slli a5, a0, 27
-; RV64I-NEXT: add a4, a4, a5
-; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: slli a3, a0, 21
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a0, 29
-; RV64I-NEXT: add a3, a4, a3
+; RV64I-NEXT: add a2, a7, a2
+; RV64I-NEXT: add a4, a6, a4
; RV64I-NEXT: slli a0, a0, 31
+; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: add a0, a3, a0
+; RV64I-NEXT: add a0, a4, a0
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
%a1 = mul i64 %a, 2863311530
@@ -745,22 +745,22 @@ define i32 @muli32_0x12345678(i32 %a) nounwind {
; RV64I-NEXT: slli a3, a0, 9
; RV64I-NEXT: slli a4, a0, 11
; RV64I-NEXT: slli a5, a0, 13
+; RV64I-NEXT: slli a6, a0, 15
; RV64I-NEXT: sub a2, a2, a1
-; RV64I-NEXT: slli a1, a0, 15
+; RV64I-NEXT: slli a1, a0, 20
; RV64I-NEXT: add a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 20
-; RV64I-NEXT: sub a5, a5, a1
-; RV64I-NEXT: slli a1, a0, 22
-; RV64I-NEXT: sub a4, a4, a1
+; RV64I-NEXT: slli a4, a0, 22
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a0, 25
+; RV64I-NEXT: sub a1, a1, a4
+; RV64I-NEXT: slli a4, a0, 28
+; RV64I-NEXT: add a4, a6, a4
; RV64I-NEXT: sub a2, a2, a3
-; RV64I-NEXT: slli a1, a0, 18
-; RV64I-NEXT: sub a5, a5, a1
-; RV64I-NEXT: slli a1, a0, 25
-; RV64I-NEXT: sub a4, a4, a1
-; RV64I-NEXT: slli a0, a0, 28
+; RV64I-NEXT: slli a0, a0, 18
+; RV64I-NEXT: sub a5, a5, a0
; RV64I-NEXT: sub a2, a2, a5
-; RV64I-NEXT: sub a4, a4, a0
-; RV64I-NEXT: sub a0, a2, a4
+; RV64I-NEXT: sub a1, a1, a4
+; RV64I-NEXT: sub a0, a2, a1
; RV64I-NEXT: ret
%a1 = mul i32 %a, 305419896
ret i32 %a1
@@ -786,22 +786,22 @@ define i64 @muli64_0x12345678(i64 %a) nounwind {
; RV64I-NEXT: slli a3, a0, 9
; RV64I-NEXT: slli a4, a0, 11
; RV64I-NEXT: slli a5, a0, 13
+; RV64I-NEXT: slli a6, a0, 15
; RV64I-NEXT: sub a2, a2, a1
-; RV64I-NEXT: slli a1, a0, 15
+; RV64I-NEXT: slli a1, a0, 20
; RV64I-NEXT: add a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 20
-; RV64I-NEXT: sub a5, a5, a1
-; RV64I-NEXT: slli a1, a0, 22
-; RV64I-NEXT: sub a4, a4, a1
+; RV64I-NEXT: slli a4, a0, 22
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a0, 25
+; RV64I-NEXT: sub a1, a1, a4
+; RV64I-NEXT: slli a4, a0, 28
+; RV64I-NEXT: add a4, a6, a4
; RV64I-NEXT: sub a2, a2, a3
-; RV64I-NEXT: slli a1, a0, 18
-; RV64I-NEXT: sub a5, a5, a1
-; RV64I-NEXT: slli a1, a0, 25
-; RV64I-NEXT: sub a4, a4, a1
-; RV64I-NEXT: slli a0, a0, 28
+; RV64I-NEXT: slli a0, a0, 18
+; RV64I-NEXT: sub a5, a5, a0
; RV64I-NEXT: sub a2, a2, a5
-; RV64I-NEXT: sub a4, a4, a0
-; RV64I-NEXT: sub a0, a2, a4
+; RV64I-NEXT: sub a1, a1, a4
+; RV64I-NEXT: sub a0, a2, a1
; RV64I-NEXT: ret
%a1 = mul i64 %a, 305419896
ret i64 %a1
diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
index c62fb0ae63555..cbccfcb37dc3a 100644
--- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
@@ -395,23 +395,23 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
; RV64I-NEXT: add a0, a1, a0
@@ -453,23 +453,23 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI7_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0)
; RV64I-NEXT: add a0, a1, a0
@@ -503,23 +503,23 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI8_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI8_0)
; RV64I-NEXT: add a1, a2, a1
@@ -564,26 +564,26 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
+; RV64I-NEXT: lui a1, %hi(.LCPI9_0)
+; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0)
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: lui a4, %hi(.LCPI9_0)
-; RV64I-NEXT: addi a4, a4, %lo(.LCPI9_0)
-; RV64I-NEXT: slli a1, a1, 27
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
-; RV64I-NEXT: add a1, a4, a1
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a2, a2, 27
+; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: lbu a1, 0(a1)
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addi a1, a1, 1
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index 0afd6f5727934..5f1cb3ff41665 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -5098,8 +5098,7 @@ define i32 @shl_add_shl_add(i32 %a, i32 %b, i32 %c) {
;
; RV64ZBA-LABEL: shl_add_shl_add:
; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: slli a2, a2, 5
-; RV64ZBA-NEXT: add a1, a1, a2
+; RV64ZBA-NEXT: sh2add a0, a2, a0
; RV64ZBA-NEXT: sh3add a0, a0, a1
; RV64ZBA-NEXT: sext.w a0, a0
; RV64ZBA-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index b3581459c2622..f47aaefb06ca5 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -347,23 +347,23 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
; RV64I-NEXT: add a0, a1, a0
@@ -390,23 +390,23 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a2, a0, 8
; RV64I-NEXT: slli a3, a0, 10
; RV64I-NEXT: slli a4, a0, 12
+; RV64I-NEXT: slli a5, a0, 16
; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a0, 16
-; RV64I-NEXT: sub a3, a3, a4
-; RV64I-NEXT: slli a4, a0, 18
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a4, a0, 4
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: add a1, a4, a1
-; RV64I-NEXT: slli a4, a0, 14
+; RV64I-NEXT: slli a2, a0, 18
; RV64I-NEXT: sub a3, a3, a4
; RV64I-NEXT: slli a4, a0, 23
-; RV64I-NEXT: sub a2, a2, a4
-; RV64I-NEXT: slli a0, a0, 27
+; RV64I-NEXT: sub a5, a5, a2
+; RV64I-NEXT: slli a2, a0, 27
+; RV64I-NEXT: sub a4, a4, a2
+; RV64I-NEXT: slli a2, a0, 4
+; RV64I-NEXT: sub a2, a0, a2
+; RV64I-NEXT: add a1, a2, a1
+; RV64I-NEXT: slli a0, a0, 14
+; RV64I-NEXT: sub a3, a3, a0
+; RV64I-NEXT: sub a5, a5, a4
; RV64I-NEXT: add a1, a1, a3
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srliw a0, a0, 27
+; RV64I-NEXT: add a1, a1, a5
+; RV64I-NEXT: srliw a0, a1, 27
; RV64I-NEXT: lui a1, %hi(.LCPI7_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0)
; RV64I-NEXT: add a0, a1, a0
@@ -430,23 +430,23 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a1, a1, 27
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a1, a2, 27
; RV64I-NEXT: lui a2, %hi(.LCPI8_0)
; RV64I-NEXT: addi a2, a2, %lo(.LCPI8_0)
; RV64I-NEXT: add a1, a2, a1
@@ -478,26 +478,26 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a3, a1, 8
; RV64I-NEXT: slli a4, a1, 10
; RV64I-NEXT: slli a5, a1, 12
+; RV64I-NEXT: slli a6, a1, 16
; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: slli a3, a1, 16
-; RV64I-NEXT: sub a4, a4, a5
-; RV64I-NEXT: slli a5, a1, 18
-; RV64I-NEXT: sub a3, a3, a5
-; RV64I-NEXT: slli a5, a1, 4
-; RV64I-NEXT: sub a5, a1, a5
-; RV64I-NEXT: add a2, a5, a2
-; RV64I-NEXT: slli a5, a1, 14
+; RV64I-NEXT: slli a3, a1, 18
; RV64I-NEXT: sub a4, a4, a5
; RV64I-NEXT: slli a5, a1, 23
+; RV64I-NEXT: sub a3, a6, a3
+; RV64I-NEXT: slli a6, a1, 27
+; RV64I-NEXT: sub a5, a5, a6
+; RV64I-NEXT: slli a6, a1, 4
+; RV64I-NEXT: sub a6, a1, a6
+; RV64I-NEXT: add a2, a6, a2
+; RV64I-NEXT: slli a1, a1, 14
+; RV64I-NEXT: sub a4, a4, a1
; RV64I-NEXT: sub a3, a3, a5
+; RV64I-NEXT: lui a1, %hi(.LCPI9_0)
+; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0)
; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: lui a4, %hi(.LCPI9_0)
-; RV64I-NEXT: addi a4, a4, %lo(.LCPI9_0)
-; RV64I-NEXT: slli a1, a1, 27
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: add a1, a2, a1
-; RV64I-NEXT: srliw a1, a1, 27
-; RV64I-NEXT: add a1, a4, a1
+; RV64I-NEXT: add a2, a2, a3
+; RV64I-NEXT: srliw a2, a2, 27
+; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: lbu a1, 0(a1)
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addi a1, a1, 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
index 719659823ed91..7cb4fd7bb2e65 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
@@ -88,56 +88,107 @@ define i8 @explode_8xi8(<8 x i8> %v) {
}
define i8 @explode_16xi8(<16 x i8> %v) {
-; CHECK-LABEL: explode_16xi8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 3
-; CHECK-NEXT: vmv.x.s a1, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 4
-; CHECK-NEXT: vmv.x.s a2, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 5
-; CHECK-NEXT: vmv.x.s a3, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 6
-; CHECK-NEXT: vmv.x.s a4, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 7
-; CHECK-NEXT: vmv.x.s a5, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 8
-; CHECK-NEXT: vmv.x.s a6, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 9
-; CHECK-NEXT: vmv.x.s a7, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 10
-; CHECK-NEXT: vmv.x.s t0, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 11
-; CHECK-NEXT: vmv.x.s t1, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 12
-; CHECK-NEXT: vmv.x.s t2, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 13
-; CHECK-NEXT: vmv.x.s t3, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 14
-; CHECK-NEXT: vmv.x.s t4, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 15
-; CHECK-NEXT: vmv.x.s t5, v9
-; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v8, v9
-; CHECK-NEXT: vmv.x.s t6, v8
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: add a2, a2, a3
-; CHECK-NEXT: add a5, a5, a6
-; CHECK-NEXT: add t1, t1, t2
-; CHECK-NEXT: add a0, t6, a0
-; CHECK-NEXT: add a2, a2, a4
-; CHECK-NEXT: add a5, a5, a7
-; CHECK-NEXT: add t1, t1, t3
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: add a5, a5, t0
-; CHECK-NEXT: add t1, t1, t4
-; CHECK-NEXT: add a0, a0, a5
-; CHECK-NEXT: add t1, t1, t5
-; CHECK-NEXT: add a0, a0, t1
-; CHECK-NEXT: ret
+; RV32-LABEL: explode_16xi8:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v9, v8, 2
+; RV32-NEXT: vmv.x.s a0, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 3
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 4
+; RV32-NEXT: vmv.x.s a2, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 5
+; RV32-NEXT: vmv.x.s a3, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 6
+; RV32-NEXT: vmv.x.s a4, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 7
+; RV32-NEXT: vmv.x.s a5, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 8
+; RV32-NEXT: vmv.x.s a6, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 9
+; RV32-NEXT: vmv.x.s a7, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 10
+; RV32-NEXT: vmv.x.s t0, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 11
+; RV32-NEXT: vmv.x.s t1, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 12
+; RV32-NEXT: vmv.x.s t2, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 13
+; RV32-NEXT: vmv.x.s t3, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 14
+; RV32-NEXT: vmv.x.s t4, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 15
+; RV32-NEXT: vmv.x.s t5, v9
+; RV32-NEXT: vmv.s.x v9, zero
+; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; RV32-NEXT: vredxor.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s t6, v8
+; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: add a2, a2, a3
+; RV32-NEXT: add a5, a5, a6
+; RV32-NEXT: add t1, t1, t2
+; RV32-NEXT: add a0, t6, a0
+; RV32-NEXT: add a2, a2, a4
+; RV32-NEXT: add a5, a5, a7
+; RV32-NEXT: add t1, t1, t3
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: add a5, a5, t0
+; RV32-NEXT: add t1, t1, t4
+; RV32-NEXT: add a0, a0, a5
+; RV32-NEXT: add t1, t1, t5
+; RV32-NEXT: add a0, a0, t1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: explode_16xi8:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64-NEXT: vslidedown.vi v9, v8, 2
+; RV64-NEXT: vmv.x.s a0, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 3
+; RV64-NEXT: vmv.x.s a1, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 4
+; RV64-NEXT: vmv.x.s a2, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 5
+; RV64-NEXT: vmv.x.s a3, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 6
+; RV64-NEXT: vmv.x.s a4, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 7
+; RV64-NEXT: vmv.x.s a5, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 8
+; RV64-NEXT: vmv.x.s a6, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 9
+; RV64-NEXT: vmv.x.s a7, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 10
+; RV64-NEXT: vmv.x.s t0, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 11
+; RV64-NEXT: vmv.x.s t1, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 12
+; RV64-NEXT: vmv.x.s t2, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 13
+; RV64-NEXT: vmv.x.s t3, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 14
+; RV64-NEXT: vmv.x.s t4, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 15
+; RV64-NEXT: vmv.x.s t5, v9
+; RV64-NEXT: vmv.s.x v9, zero
+; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; RV64-NEXT: vredxor.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s t6, v8
+; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: add a2, a2, a3
+; RV64-NEXT: add a5, a5, a6
+; RV64-NEXT: add a7, a7, t0
+; RV64-NEXT: add t1, t1, t2
+; RV64-NEXT: add t3, t3, t4
+; RV64-NEXT: add a0, t6, a0
+; RV64-NEXT: add a2, a2, a4
+; RV64-NEXT: add a5, a5, a7
+; RV64-NEXT: add t1, t1, t3
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: add a0, a0, a5
+; RV64-NEXT: add t1, t1, t5
+; RV64-NEXT: add a0, a0, t1
+; RV64-NEXT: ret
%e0 = extractelement <16 x i8> %v, i32 0
%e1 = extractelement <16 x i8> %v, i32 1
%e2 = extractelement <16 x i8> %v, i32 2
@@ -258,57 +309,109 @@ define i16 @explode_8xi16(<8 x i16> %v) {
}
define i16 @explode_16xi16(<16 x i16> %v) {
-; CHECK-LABEL: explode_16xi16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 8
-; CHECK-NEXT: vmv.x.s a0, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 9
-; CHECK-NEXT: vmv.x.s a1, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 10
-; CHECK-NEXT: vmv.x.s a2, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 11
-; CHECK-NEXT: vmv.x.s a3, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 12
-; CHECK-NEXT: vmv.x.s a4, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 13
-; CHECK-NEXT: vmv.x.s a5, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 14
-; CHECK-NEXT: vmv.x.s a6, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 15
-; CHECK-NEXT: vmv.x.s a7, v10
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 2
-; CHECK-NEXT: vslidedown.vi v10, v8, 3
-; CHECK-NEXT: vmv.x.s t0, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 4
-; CHECK-NEXT: vmv.x.s t1, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 5
-; CHECK-NEXT: vmv.x.s t2, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 6
-; CHECK-NEXT: vmv.x.s t3, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 7
-; CHECK-NEXT: vmv.x.s t4, v9
-; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vmv.x.s t5, v10
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vredxor.vs v8, v8, v9
-; CHECK-NEXT: vmv.x.s t6, v8
-; CHECK-NEXT: add t0, t0, t1
-; CHECK-NEXT: add t2, t2, t3
-; CHECK-NEXT: add a0, t5, a0
-; CHECK-NEXT: add a3, a3, a4
-; CHECK-NEXT: add t0, t6, t0
-; CHECK-NEXT: add t2, t2, t4
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: add a3, a3, a5
-; CHECK-NEXT: add t0, t0, t2
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: add a3, a3, a6
-; CHECK-NEXT: add a0, t0, a0
-; CHECK-NEXT: add a3, a3, a7
-; CHECK-NEXT: add a0, a0, a3
-; CHECK-NEXT: ret
+; RV32-LABEL: explode_16xi16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; RV32-NEXT: vslidedown.vi v10, v8, 8
+; RV32-NEXT: vmv.x.s a0, v10
+; RV32-NEXT: vslidedown.vi v10, v8, 9
+; RV32-NEXT: vmv.x.s a1, v10
+; RV32-NEXT: vslidedown.vi v10, v8, 10
+; RV32-NEXT: vmv.x.s a2, v10
+; RV32-NEXT: vslidedown.vi v10, v8, 11
+; RV32-NEXT: vmv.x.s a3, v10
+; RV32-NEXT: vslidedown.vi v10, v8, 12
+; RV32-NEXT: vmv.x.s a4, v10
+; RV32-NEXT: vslidedown.vi v10, v8, 13
+; RV32-NEXT: vmv.x.s a5, v10
+; RV32-NEXT: vslidedown.vi v10, v8, 14
+; RV32-NEXT: vmv.x.s a6, v10
+; RV32-NEXT: vslidedown.vi v10, v8, 15
+; RV32-NEXT: vmv.x.s a7, v10
+; RV32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v9, v8, 2
+; RV32-NEXT: vslidedown.vi v10, v8, 3
+; RV32-NEXT: vmv.x.s t0, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 4
+; RV32-NEXT: vmv.x.s t1, v10
+; RV32-NEXT: vslidedown.vi v10, v8, 5
+; RV32-NEXT: vmv.x.s t2, v9
+; RV32-NEXT: vslidedown.vi v9, v8, 6
+; RV32-NEXT: vmv.x.s t3, v10
+; RV32-NEXT: vslidedown.vi v10, v8, 7
+; RV32-NEXT: vmv.x.s t4, v9
+; RV32-NEXT: vmv.s.x v9, zero
+; RV32-NEXT: vmv.x.s t5, v10
+; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; RV32-NEXT: vredxor.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s t6, v8
+; RV32-NEXT: add t0, t0, t1
+; RV32-NEXT: add t2, t2, t3
+; RV32-NEXT: add a0, t5, a0
+; RV32-NEXT: add a3, a3, a4
+; RV32-NEXT: add t0, t6, t0
+; RV32-NEXT: add t2, t2, t4
+; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: add a3, a3, a5
+; RV32-NEXT: add t0, t0, t2
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: add a3, a3, a6
+; RV32-NEXT: add a0, t0, a0
+; RV32-NEXT: add a3, a3, a7
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: ret
+;
+; RV64-LABEL: explode_16xi16:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; RV64-NEXT: vslidedown.vi v10, v8, 8
+; RV64-NEXT: vmv.x.s a0, v10
+; RV64-NEXT: vslidedown.vi v10, v8, 9
+; RV64-NEXT: vmv.x.s a1, v10
+; RV64-NEXT: vslidedown.vi v10, v8, 10
+; RV64-NEXT: vmv.x.s a2, v10
+; RV64-NEXT: vslidedown.vi v10, v8, 11
+; RV64-NEXT: vmv.x.s a3, v10
+; RV64-NEXT: vslidedown.vi v10, v8, 12
+; RV64-NEXT: vmv.x.s a4, v10
+; RV64-NEXT: vslidedown.vi v10, v8, 13
+; RV64-NEXT: vmv.x.s a5, v10
+; RV64-NEXT: vslidedown.vi v10, v8, 14
+; RV64-NEXT: vmv.x.s a6, v10
+; RV64-NEXT: vslidedown.vi v10, v8, 15
+; RV64-NEXT: vmv.x.s a7, v10
+; RV64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64-NEXT: vslidedown.vi v9, v8, 2
+; RV64-NEXT: vslidedown.vi v10, v8, 3
+; RV64-NEXT: vmv.x.s t0, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 4
+; RV64-NEXT: vmv.x.s t1, v10
+; RV64-NEXT: vslidedown.vi v10, v8, 5
+; RV64-NEXT: vmv.x.s t2, v9
+; RV64-NEXT: vslidedown.vi v9, v8, 6
+; RV64-NEXT: vmv.x.s t3, v10
+; RV64-NEXT: vslidedown.vi v10, v8, 7
+; RV64-NEXT: vmv.x.s t4, v9
+; RV64-NEXT: vmv.s.x v9, zero
+; RV64-NEXT: vmv.x.s t5, v10
+; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; RV64-NEXT: vredxor.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s t6, v8
+; RV64-NEXT: add t0, t0, t1
+; RV64-NEXT: add t2, t2, t3
+; RV64-NEXT: add a0, t5, a0
+; RV64-NEXT: add a1, a1, a2
+; RV64-NEXT: add a3, a3, a4
+; RV64-NEXT: add a5, a5, a6
+; RV64-NEXT: add t0, t6, t0
+; RV64-NEXT: add t2, t2, t4
+; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: add a3, a3, a5
+; RV64-NEXT: add t0, t0, t2
+; RV64-NEXT: add a0, t0, a0
+; RV64-NEXT: add a3, a3, a7
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: ret
%e0 = extractelement <16 x i16> %v, i32 0
%e1 = extractelement <16 x i16> %v, i32 1
%e2 = extractelement <16 x i16> %v, i32 2
@@ -585,11 +688,11 @@ define i32 @explode_16xi32(<16 x i32> %v) {
; RV64-NEXT: add a3, a3, a4
; RV64-NEXT: add a7, a7, t0
; RV64-NEXT: add t2, t2, t3
+; RV64-NEXT: add t4, t4, t5
; RV64-NEXT: add a0, a0, a3
; RV64-NEXT: add a7, a7, t1
-; RV64-NEXT: add t2, t2, t4
; RV64-NEXT: add a0, a0, a7
-; RV64-NEXT: add t2, t2, t5
+; RV64-NEXT: add t2, t2, t4
; RV64-NEXT: addw a0, a0, t2
; RV64-NEXT: addi sp, s0, -128
; RV64-NEXT: .cfi_def_cfa sp, 128
@@ -1070,14 +1173,14 @@ define i64 @explode_16xi64(<16 x i64> %v) {
; RV64-NEXT: add a3, a3, a4
; RV64-NEXT: add a5, a5, a6
; RV64-NEXT: add t0, t0, t1
+; RV64-NEXT: add t2, t2, t3
+; RV64-NEXT: add t4, t4, t5
; RV64-NEXT: add a0, a0, a3
; RV64-NEXT: add a5, a5, a7
; RV64-NEXT: add t0, t0, t2
; RV64-NEXT: add a0, a0, a5
-; RV64-NEXT: add t0, t0, t3
+; RV64-NEXT: add t0, t0, t4
; RV64-NEXT: add a0, a0, t0
-; RV64-NEXT: add t4, t4, t5
-; RV64-NEXT: add a0, a0, t4
; RV64-NEXT: addi sp, s0, -256
; RV64-NEXT: .cfi_def_cfa sp, 256
; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
@@ -1205,14 +1308,14 @@ define i32 @explode_16xi32_exact_vlen(<16 x i32> %v) vscale_range(2, 2) {
; RV64-NEXT: add a0, a0, a2
; RV64-NEXT: add a1, a1, a3
; RV64-NEXT: add a5, a6, a5
+; RV64-NEXT: add a7, a7, t0
; RV64-NEXT: add t1, t2, t1
+; RV64-NEXT: add t3, t3, t4
; RV64-NEXT: add a0, t6, a0
; RV64-NEXT: add a1, a1, a4
; RV64-NEXT: add a5, a5, a7
; RV64-NEXT: add t1, t1, t3
; RV64-NEXT: add a0, a0, a1
-; RV64-NEXT: add a5, a5, t0
-; RV64-NEXT: add t1, t1, t4
; RV64-NEXT: add a0, a0, a5
; RV64-NEXT: add t1, t1, t5
; RV64-NEXT: addw a0, a0, t1
diff --git a/llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll b/llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
index 749b2041aa63d..41ead021b4dc9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
@@ -17,23 +17,23 @@ define i32 @vscale_known_nonzero() {
; CHECK-NEXT: slli a2, a0, 8
; CHECK-NEXT: slli a3, a0, 10
; CHECK-NEXT: slli a4, a0, 12
+; CHECK-NEXT: slli a5, a0, 16
; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: slli a2, a0, 16
-; CHECK-NEXT: sub a3, a3, a4
-; CHECK-NEXT: slli a4, a0, 18
-; CHECK-NEXT: sub a2, a2, a4
-; CHECK-NEXT: slli a4, a0, 4
-; CHECK-NEXT: sub a4, a0, a4
-; CHECK-NEXT: add a1, a4, a1
-; CHECK-NEXT: slli a4, a0, 14
+; CHECK-NEXT: slli a2, a0, 18
; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a0, 23
-; CHECK-NEXT: sub a2, a2, a4
-; CHECK-NEXT: slli a0, a0, 27
+; CHECK-NEXT: sub a5, a5, a2
+; CHECK-NEXT: slli a2, a0, 27
+; CHECK-NEXT: sub a4, a4, a2
+; CHECK-NEXT: slli a2, a0, 4
+; CHECK-NEXT: sub a2, a0, a2
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: slli a0, a0, 14
+; CHECK-NEXT: sub a3, a3, a0
+; CHECK-NEXT: sub a5, a5, a4
; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: add a0, a2, a0
-; CHECK-NEXT: add a0, a1, a0
-; CHECK-NEXT: srliw a0, a0, 27
+; CHECK-NEXT: add a1, a1, a5
+; CHECK-NEXT: srliw a0, a1, 27
; CHECK-NEXT: lui a1, %hi(.LCPI0_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI0_0)
; CHECK-NEXT: add a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
index 06bbe5209df35..14fcb95a83056 100644
--- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
@@ -431,77 +431,77 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV64-NEXT: slli a4, s4, 10
; RV64-NEXT: slli a5, s4, 14
; RV64-NEXT: slli a6, s4, 16
-; RV64-NEXT: slli a7, s4, 22
+; RV64-NEXT: slli a7, s4, 18
+; RV64-NEXT: slli t0, s4, 20
+; RV64-NEXT: slli t1, s4, 22
+; RV64-NEXT: slli t2, s4, 24
+; RV64-NEXT: slli t3, s4, 26
+; RV64-NEXT: slli t4, s4, 28
+; RV64-NEXT: slli t5, s3, 32
; RV64-NEXT: add a1, a1, a2
-; RV64-NEXT: slli a2, s4, 24
+; RV64-NEXT: slli a2, s3, 34
; RV64-NEXT: add a3, a3, a4
-; RV64-NEXT: slli a4, s3, 32
+; RV64-NEXT: slli a4, s3, 36
; RV64-NEXT: add a5, a5, a6
-; RV64-NEXT: slli a6, s3, 34
-; RV64-NEXT: add a2, a7, a2
-; RV64-NEXT: slli a7, s3, 48
+; RV64-NEXT: slli a6, s3, 38
+; RV64-NEXT: add a7, a7, t0
+; RV64-NEXT: slli t0, s3, 40
+; RV64-NEXT: add t1, t1, t2
+; RV64-NEXT: slli t2, s3, 42
+; RV64-NEXT: add t3, t3, t4
+; RV64-NEXT: slli t4, s3, 48
+; RV64-NEXT: add a2, t5, a2
+; RV64-NEXT: slli t5, s3, 50
; RV64-NEXT: add a4, a4, a6
-; RV64-NEXT: slli a6, s3, 50
-; RV64-NEXT: add a6, a7, a6
-; RV64-NEXT: slli a7, s4, 2
-; RV64-NEXT: add a7, s4, a7
-; RV64-NEXT: add a1, a7, a1
-; RV64-NEXT: slli a7, s4, 12
-; RV64-NEXT: add a3, a3, a7
-; RV64-NEXT: slli a7, s4, 18
+; RV64-NEXT: slli a6, s3, 52
+; RV64-NEXT: add t0, t0, t2
+; RV64-NEXT: slli t2, s3, 54
+; RV64-NEXT: add t4, t4, t5
+; RV64-NEXT: slli t5, s3, 56
+; RV64-NEXT: add a6, a6, t2
+; RV64-NEXT: slli t2, s3, 58
+; RV64-NEXT: add t2, t5, t2
+; RV64-NEXT: slli t5, s4, 2
+; RV64-NEXT: add t5, s4, t5
+; RV64-NEXT: add a1, t5, a1
+; RV64-NEXT: slli t5, s4, 12
+; RV64-NEXT: add a3, a3, t5
; RV64-NEXT: add a5, a5, a7
-; RV64-NEXT: slli a7, s4, 26
-; RV64-NEXT: add a2, a2, a7
-; RV64-NEXT: slli a7, s3, 36
-; RV64-NEXT: add a4, a4, a7
-; RV64-NEXT: slli a7, s3, 52
-; RV64-NEXT: add a6, a6, a7
-; RV64-NEXT: add a1, a1, a3
-; RV64-NEXT: slli a3, s4, 20
-; RV64-NEXT: add a3, a5, a3
-; RV64-NEXT: slli a5, s4, 28
-; RV64-NEXT: add a2, a2, a5
-; RV64-NEXT: slli a5, s3, 38
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: slli a5, s3, 54
-; RV64-NEXT: add a5, a6, a5
+; RV64-NEXT: add t1, t1, t3
+; RV64-NEXT: add a2, a2, a4
+; RV64-NEXT: slli a4, s3, 44
+; RV64-NEXT: add a4, t0, a4
+; RV64-NEXT: add a6, t4, a6
+; RV64-NEXT: slli a7, s3, 60
+; RV64-NEXT: add a7, t2, a7
; RV64-NEXT: add a1, a1, a3
; RV64-NEXT: slli s4, s4, 30
-; RV64-NEXT: add a2, a2, s4
-; RV64-NEXT: slli a3, s3, 40
-; RV64-NEXT: add a3, a4, a3
-; RV64-NEXT: slli a4, s3, 56
-; RV64-NEXT: add a4, a5, a4
-; RV64-NEXT: slli a5, s3, 42
-; RV64-NEXT: add a1, a1, a2
-; RV64-NEXT: slli a2, s3, 58
+; RV64-NEXT: add t1, t1, s4
+; RV64-NEXT: add a2, a2, a4
+; RV64-NEXT: add a6, a6, a7
+; RV64-NEXT: add a1, a1, a5
+; RV64-NEXT: slli a3, s3, 46
+; RV64-NEXT: slli s3, s3, 62
; RV64-NEXT: addi a0, a0, -2
; RV64-NEXT: addi s1, s1, -1
; RV64-NEXT: seqz a0, a0
-; RV64-NEXT: seqz a6, s1
-; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: seqz a4, s1
+; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: add a3, a3, a5
-; RV64-NEXT: slli a5, a0, 2
-; RV64-NEXT: add a2, a4, a2
-; RV64-NEXT: slli a4, a6, 31
-; RV64-NEXT: srli a4, a4, 62
-; RV64-NEXT: or a4, a4, a5
-; RV64-NEXT: slli a5, s3, 44
-; RV64-NEXT: add a3, a3, a5
-; RV64-NEXT: slli a5, s3, 60
-; RV64-NEXT: add a2, a2, a5
-; RV64-NEXT: slli a5, s3, 46
-; RV64-NEXT: add a3, a3, a5
-; RV64-NEXT: slli s3, s3, 62
-; RV64-NEXT: add a2, a2, s3
+; RV64-NEXT: add a2, a2, a3
+; RV64-NEXT: slli a3, a0, 2
+; RV64-NEXT: add a2, t1, a2
+; RV64-NEXT: slli a5, a4, 31
+; RV64-NEXT: srli a5, a5, 62
+; RV64-NEXT: or a3, a5, a3
; RV64-NEXT: lui a5, %hi(.LCPI3_0)
; RV64-NEXT: ld a5, %lo(.LCPI3_0)(a5)
; RV64-NEXT: slli a0, a0, 29
-; RV64-NEXT: slli a6, a6, 33
+; RV64-NEXT: slli a4, a4, 33
; RV64-NEXT: srli a0, a0, 61
-; RV64-NEXT: add a1, a1, a3
-; RV64-NEXT: sub a2, a5, a2
+; RV64-NEXT: sub a7, a5, s3
+; RV64-NEXT: add a1, a1, a2
+; RV64-NEXT: sub a2, a7, a6
; RV64-NEXT: sub a2, a2, a1
; RV64-NEXT: slli a1, a2, 63
; RV64-NEXT: srli a2, a2, 1
@@ -510,9 +510,9 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV64-NEXT: neg a1, a1
; RV64-NEXT: slli a1, a1, 31
; RV64-NEXT: srli a1, a1, 31
-; RV64-NEXT: or a1, a1, a6
+; RV64-NEXT: or a1, a1, a4
; RV64-NEXT: sd a1, 0(s0)
-; RV64-NEXT: sw a4, 8(s0)
+; RV64-NEXT: sw a3, 8(s0)
; RV64-NEXT: sb a0, 12(s0)
; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/zicond-opts.ll b/llvm/test/CodeGen/RISCV/zicond-opts.ll
index 47ff6edb0499d..4cbdbe754f4f1 100644
--- a/llvm/test/CodeGen/RISCV/zicond-opts.ll
+++ b/llvm/test/CodeGen/RISCV/zicond-opts.ll
@@ -444,8 +444,7 @@ define i64 @addiw_addi(i32 %x) {
; RV64ZICOND-LABEL: addiw_addi:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: sext.w a1, a0
-; RV64ZICOND-NEXT: addi a0, a0, -1
-; RV64ZICOND-NEXT: addi a0, a0, -63
+; RV64ZICOND-NEXT: addi a0, a0, -64
; RV64ZICOND-NEXT: czero.eqz a0, a0, a1
; RV64ZICOND-NEXT: addi a0, a0, 63
; RV64ZICOND-NEXT: bset a0, zero, a0
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