[llvm] HexagonGenWideningVecInstr.cpp - fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC. (PR #171095)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/171095

None

>From b70e3d71275c4fd0ed46a34053e525e487da4654 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Mon, 8 Dec 2025 09:13:01 +0000
Subject: [PATCH] HexagonGenWideningVecInstr.cpp - fix MSVC "esult of 32-bit
 shift implicitly converted to 64 bits" warning. NFC.

---
 llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp b/llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp
index 895de57561430..478eaf10b0710 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp
@@ -596,7 +596,7 @@ bool HexagonGenWideningVecInstr::replaceWithIntrinsic(Instruction *Inst,
   if (IsConstScalar && OPK == OP_Shl) {
     if (((NewOpEltSize == 8) && (SplatVal > 0) && (SplatVal < 8)) ||
         ((NewOpEltSize == 16) && (SplatVal > 0) && (SplatVal < 16))) {
-      SplatVal = 1 << SplatVal;
+      SplatVal = 1LL << SplatVal;
       OPK = OP_Mul;
     } else {
       return false;