[llvm] 9c60d70 - [RISCV] Re-generate rvp-ext-rv32.ll after #170399. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 7 23:23:07 PST 2025
Author: Craig Topper
Date: 2025-12-07T23:19:36-08:00
New Revision: 9c60d70df9212734d0cf332b4b687a4942cc7257
URL: https://github.com/llvm/llvm-project/commit/9c60d70df9212734d0cf332b4b687a4942cc7257
DIFF: https://github.com/llvm/llvm-project/commit/9c60d70df9212734d0cf332b4b687a4942cc7257.diff
LOG: [RISCV] Re-generate rvp-ext-rv32.ll after #170399. NFC
Some instructions got renamed by #170399, but new tests cases were
added after that PR was created.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index afca45a39f854..cd59aa03597e2 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -691,7 +691,7 @@ define void @test_psll_hs_vec_shamt(ptr %ret_ptr, ptr %a_ptr, ptr %shamt_ptr) {
; CHECK-RV64-NEXT: srli a2, a2, 16
; CHECK-RV64-NEXT: srli a1, a1, 16
; CHECK-RV64-NEXT: sll a1, a1, a2
-; CHECK-RV64-NEXT: ppack.w a1, a3, a1
+; CHECK-RV64-NEXT: ppaire.h a1, a3, a1
; CHECK-RV64-NEXT: sw a1, 0(a0)
; CHECK-RV64-NEXT: ret
%a = load <2 x i16>, ptr %a_ptr
@@ -716,7 +716,7 @@ define void @test_psll_bs_vec_shamt(ptr %ret_ptr, ptr %a_ptr, ptr %shamt_ptr) {
; CHECK-RV32-NEXT: srli a2, a2, 16
; CHECK-RV32-NEXT: srli a1, a1, 16
; CHECK-RV32-NEXT: sll a5, a1, a2
-; CHECK-RV32-NEXT: ppack.dh a2, a4, a6
+; CHECK-RV32-NEXT: ppaire.db a2, a4, a6
; CHECK-RV32-NEXT: pack a1, a2, a3
; CHECK-RV32-NEXT: sw a1, 0(a0)
; CHECK-RV32-NEXT: ret
@@ -735,9 +735,9 @@ define void @test_psll_bs_vec_shamt(ptr %ret_ptr, ptr %a_ptr, ptr %shamt_ptr) {
; CHECK-RV64-NEXT: srli a2, a2, 8
; CHECK-RV64-NEXT: srli a1, a1, 8
; CHECK-RV64-NEXT: sll a1, a1, a2
-; CHECK-RV64-NEXT: ppack.h a2, a4, a3
-; CHECK-RV64-NEXT: ppack.h a1, a5, a1
-; CHECK-RV64-NEXT: ppack.w a1, a1, a2
+; CHECK-RV64-NEXT: ppaire.b a2, a4, a3
+; CHECK-RV64-NEXT: ppaire.b a1, a5, a1
+; CHECK-RV64-NEXT: ppaire.h a1, a1, a2
; CHECK-RV64-NEXT: sw a1, 0(a0)
; CHECK-RV64-NEXT: ret
%a = load <4 x i8>, ptr %a_ptr
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