[llvm] [Hexagon] Fix HWBF16 PatLeaf type (PR #170560)

[Fateme Hosseini via llvm-commits]

https://github.com/fhossein-quic updated https://github.com/llvm/llvm-project/pull/170560

>From 15c27479248f5e01e688168e49cf3f52ecb98872 Mon Sep 17 00:00:00 2001
From: Muntasir Mallick <quic_mallick at quicinc.com>
Date: Mon, 5 May 2025 14:07:44 -0700
Subject: [PATCH] [Hexagon] Custom lower v128 bf16 vectors

Adds custom load/store and masked/vector-building lowering for
v128bf16, updates HVX patterns to use the proper VecPBF16 leaf.

Patch By: Fateme Hosseini

Co-authored-by: Muntasir Mallick <quic_mallick at quicinc.com>
---
 .../Target/Hexagon/HexagonISelLoweringHVX.cpp |  8 ++++++
 llvm/lib/Target/Hexagon/HexagonPatternsHVX.td |  6 ++++-
 llvm/test/CodeGen/Hexagon/bfloat_vec.ll       | 25 ++++++++-----------
 3 files changed, 23 insertions(+), 16 deletions(-)

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 4bc8e741c56bf..22597980c729f 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -184,11 +184,19 @@ HexagonTargetLowering::initializeHVXLowering() {
       setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64bf16, Custom);
       setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64bf16, Custom);
 
+      setOperationAction(ISD::LOAD, MVT::v128bf16, Custom);
+      setOperationAction(ISD::STORE, MVT::v128bf16, Custom);
+
       setOperationAction(ISD::MLOAD, MVT::v64bf16, Custom);
       setOperationAction(ISD::MSTORE, MVT::v64bf16, Custom);
       setOperationAction(ISD::BUILD_VECTOR, MVT::v64bf16, Custom);
       setOperationAction(ISD::CONCAT_VECTORS, MVT::v64bf16, Custom);
 
+      setOperationAction(ISD::MLOAD, MVT::v128bf16, Custom);
+      setOperationAction(ISD::MSTORE, MVT::v128bf16, Custom);
+      setOperationAction(ISD::BUILD_VECTOR, MVT::v128bf16, Custom);
+      setOperationAction(ISD::CONCAT_VECTORS, MVT::v128bf16, Custom);
+
       setOperationAction(ISD::SPLAT_VECTOR, MVT::bf16, Custom);
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::bf16, Custom);
       setOperationAction(ISD::BUILD_VECTOR, MVT::bf16, Custom);
diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
index 674d19176a88b..c0352f8e10fd2 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
@@ -22,7 +22,7 @@ def HWI16:  PatLeaf<(VecPI16 HvxWR:$R)>;
 def HWI32:  PatLeaf<(VecPI32 HvxWR:$R)>;
 def HWF16:  PatLeaf<(VecPF16 HvxWR:$R)>;
 def HWF32:  PatLeaf<(VecPF32 HvxWR:$R)>;
-def HWBF16: PatLeaf<(VecBF16 HvxWR:$R)>;
+def HWBF16: PatLeaf<(VecPBF16 HvxWR:$R)>;
 
 def SDTVecUnaryOp:
   SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
@@ -354,11 +354,15 @@ let Predicates = [UseHVX, UseHVXFloatingPoint] in {
 
   def: Pat<(VecPF16 (concat_vectors HVF16:$Vs, HVF16:$Vt)),
            (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
+  def: Pat<(VecPBF16 (concat_vectors HVBF16:$Vs, HVBF16:$Vt)),
+           (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
   def: Pat<(VecPF32 (concat_vectors HVF32:$Vs, HVF32:$Vt)),
            (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
 
   def: Pat<(HexagonVINSERTW0 HVF16:$Vu, I32:$Rt),
            (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
+  def: Pat<(HexagonVINSERTW0 HVBF16:$Vu, I32:$Rt),
+           (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
   def: Pat<(HexagonVINSERTW0 HVF32:$Vu, I32:$Rt),
            (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
 }
diff --git a/llvm/test/CodeGen/Hexagon/bfloat_vec.ll b/llvm/test/CodeGen/Hexagon/bfloat_vec.ll
index e9373d85e16d8..54a14cb05ac25 100644
--- a/llvm/test/CodeGen/Hexagon/bfloat_vec.ll
+++ b/llvm/test/CodeGen/Hexagon/bfloat_vec.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=hexagon --mattr=+hvx-length128b,+hvx-qfloat,+hvxv81,+v81 < %s | FileCheck %s
+; RUN: llc -mtriple=hexagon < %s | FileCheck %s
 
 ; Function Attrs: mustprogress nounwind
 
@@ -95,22 +95,17 @@ entry:
 
 define dso_local void @copy1d(ptr noundef readonly captures(none) %X, ptr noundef writeonly captures(none) %Y) local_unnamed_addr #0 {
 ; CHECK-LABEL: copy1d:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    {
-; CHECK-NEXT:     v0 = vmemu(r0+#1)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     v1 = vmemu(r0+#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     vmemu(r1+#1) = v0
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     jumpr r31
-; CHECK-NEXT:     vmemu(r1+#0) = v1
-; CHECK-NEXT:    }
+; CHECK: v[[X_HI:[0-9]+]] = vmemu(r0+#1)
+; CHECK: v[[X_LO:[0-9]+]] = vmemu(r0+#0)
+; CHECK: vmemu(r1+#1) = v[[X_HI]]
+; CHECK: jumpr [[RET:r[0-9]+]]
+; CHECK: vmemu(r1+#0) = v[[X_LO]]
 entry:
   %0 = load <128 x half>, ptr %X, align 2
   store <128 x half> %0, ptr %Y, align 2
   ret void
 }
+
+attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv81" "target-features"="+hvx-length128b,+hvx-qfloat,+hvxv81,+v81,-long-calls" }
+attributes #1 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv81" "target-features"="+hvx-length128b,+hvx-qfloat,+hvxv81,+v81,-long-calls" }
+attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }