[llvm] [SystemZ] Support fp16 vector ABI and basic codegen. (PR #171066)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp llvm/lib/Target/SystemZ/SystemZISelLowering.h --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index aaa6c22ea..ccd99eeb8 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -845,8 +845,9 @@ bool SystemZTargetLowering::useSoftFloat() const {
   return Subtarget.hasSoftFloat();
 }
 
-unsigned SystemZTargetLowering::getNumRegisters(LLVMContext &Context, EVT VT,
-                                          std::optional<MVT> RegisterVT) const {
+unsigned
+SystemZTargetLowering::getNumRegisters(LLVMContext &Context, EVT VT,
+                                       std::optional<MVT> RegisterVT) const {
   // i128 inline assembly operand.
   if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)
     return 1;
@@ -6391,13 +6392,12 @@ static SDValue mergeHighParts(SelectionDAG &DAG, const SDLoc &DL,
          "Handling full vectors only.");
   Op0 = DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0);
   Op1 = DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op1);
-  SDValue Op = DAG.getNode(SystemZISD::MERGE_HIGH,
-                           DL, IntVecVT, Op0, Op1);
+  SDValue Op = DAG.getNode(SystemZISD::MERGE_HIGH, DL, IntVecVT, Op0, Op1);
   return DAG.getNode(ISD::BITCAST, DL, VT, Op);
 }
 
-static SDValue buildFPVecFromScalars4(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
-                                      SmallVectorImpl<SDValue> &Elems,
+static SDValue buildFPVecFromScalars4(SelectionDAG &DAG, const SDLoc &DL,
+                                      EVT VT, SmallVectorImpl<SDValue> &Elems,
                                       unsigned Pos) {
   SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[Pos + 0], Elems[Pos + 1]);
   SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[Pos + 2], Elems[Pos + 3]);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index ca47b96ef..9ea7f3e55 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -68,7 +68,8 @@ public:
     // Expand (narrow) f16 vectors during type legalization to avoid
     // operations for all elements as with expansion after widening.
     if (VT.getScalarType() == MVT::f16)
-      return VT.getVectorElementCount().isScalar() ? TypeScalarizeVector : TypeSplitVector;
+      return VT.getVectorElementCount().isScalar() ? TypeScalarizeVector
+                                                   : TypeSplitVector;
     if (VT.getScalarSizeInBits() % 8 == 0)
       return TypeWidenVector;
     return TargetLoweringBase::getPreferredVectorAction(VT);

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https://github.com/llvm/llvm-project/pull/171066