[llvm] [DAG] Precommit test for PR #164946 - Update Tests SimplifyDemandedBits - ICMP_SLT(X,0) - only sign mask of X is required (PR #171030)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 7 03:16:32 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
@llvm/pr-subscribers-backend-aarch64
Author: Anikesh Parashar (an1k3sh)
<details>
<summary>Changes</summary>
Test case update for #<!-- -->164946
Resolves #<!-- -->164589
---
Patch is 45.79 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/171030.diff
14 Files Affected:
- (modified) llvm/test/CodeGen/AArch64/tbz-tbnz.ll (+5-24)
- (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll (+22-19)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll (+8-16)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll (+8-8)
- (modified) llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll (+4-6)
- (modified) llvm/test/CodeGen/RISCV/bittest.ll (+4-3)
- (modified) llvm/test/CodeGen/RISCV/float-intrinsics.ll (+8-6)
- (modified) llvm/test/CodeGen/SystemZ/tdc-05.ll (+72-29)
- (modified) llvm/test/CodeGen/X86/combine-smax.ll (+8-11)
- (modified) llvm/test/CodeGen/X86/combine-smin.ll (+8-11)
- (modified) llvm/test/CodeGen/X86/combine-umax.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/combine-umin.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/is_fpclass-fp80.ll (+35-31)
- (modified) llvm/test/CodeGen/X86/test-shrink.ll (+21-28)
``````````diff
diff --git a/llvm/test/CodeGen/AArch64/tbz-tbnz.ll b/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
index 72e3a2ef59677..a43db908dcadd 100644
--- a/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
+++ b/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
@@ -836,30 +836,11 @@ if.then28: ; preds = %if.end26
}
define i1 @avifSequenceHeaderParse() {
-; CHECK-SD-LABEL: avifSequenceHeaderParse:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: mov w8, #1 // =0x1
-; CHECK-SD-NEXT: cbz w8, .LBB24_2
-; CHECK-SD-NEXT: .LBB24_1: // %bb6
-; CHECK-SD-NEXT: mov w0, wzr
-; CHECK-SD-NEXT: ret
-; CHECK-SD-NEXT: .LBB24_2: // %bb1
-; CHECK-SD-NEXT: cbz w8, .LBB24_4
-; CHECK-SD-NEXT: // %bb.3:
-; CHECK-SD-NEXT: b .LBB24_1
-; CHECK-SD-NEXT: .LBB24_4: // %bb2
-; CHECK-SD-NEXT: mov w8, #1 // =0x1
-; CHECK-SD-NEXT: tbz x8, #63, .LBB24_1
-; CHECK-SD-NEXT: // %bb.5: // %bb4
-; CHECK-SD-NEXT: mov w8, #1 // =0x1
-; CHECK-SD-NEXT: mov w0, wzr
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: avifSequenceHeaderParse:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov w0, wzr
-; CHECK-GI-NEXT: mov w8, #1 // =0x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: avifSequenceHeaderParse:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: mov w8, #1 // =0x1
+; CHECK-NEXT: ret
entry:
%a = icmp slt i64 0, 0
br i1 %a, label %bb1, label %bb6
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
index 58adb220d7b2f..0299cc60bfc86 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
@@ -14,15 +14,15 @@ define amdgpu_kernel void @uniform_trunc_i16_to_i1(ptr addrspace(1) %out, i16 %x
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY2]], %subreg.sub0, killed [[COPY1]], %subreg.sub1, killed [[S_MOV_B32_1]], %subreg.sub2, killed [[S_MOV_B32_]], %subreg.sub3
- ; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[S_LOAD_DWORD_IMM]]
; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 16
- ; GCN-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[S_LOAD_DWORD_IMM]], killed [[S_MOV_B32_2]], implicit-def dead $scc
+ ; GCN-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_LOAD_DWORD_IMM]], [[S_MOV_B32_2]], implicit-def dead $scc
+ ; GCN-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[S_LOAD_DWORD_IMM]], [[S_MOV_B32_2]], implicit-def dead $scc
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY killed [[S_LSHR_B32_]]
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY3]], implicit-def dead $scc
; GCN-NEXT: S_CMP_EQ_U32 killed [[S_AND_B32_]], 1, implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $scc
; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GCN-NEXT: S_CMP_LT_I32 killed [[S_SEXT_I32_I16_]], killed [[S_MOV_B32_3]], implicit-def $scc
+ ; GCN-NEXT: S_CMP_LT_I32 killed [[S_LSHL_B32_]], killed [[S_MOV_B32_3]], implicit-def $scc
; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_64 = COPY $scc
; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[COPY5]], killed [[COPY4]], implicit-def dead $scc
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B64_]], implicit $exec
@@ -41,11 +41,12 @@ define i1 @divergent_trunc_i16_to_i1(ptr addrspace(1) %out, i16 %x, i1 %z) {
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
+ ; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 killed [[S_MOV_B32_]], [[COPY1]], implicit $exec
; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 1, [[COPY]], implicit $exec
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_AND_B32_e64_]], 1, implicit $exec
- ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY1]], 0, 16, implicit $exec
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GCN-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I32_e64 killed [[V_BFE_I32_e64_]], killed [[S_MOV_B32_]], implicit $exec
+ ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; GCN-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I32_e64 killed [[V_LSHLREV_B32_e64_]], killed [[S_MOV_B32_1]], implicit $exec
; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[V_CMP_LT_I32_e64_]], killed [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B64_]], implicit $exec
; GCN-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
@@ -124,16 +125,17 @@ define amdgpu_kernel void @uniform_trunc_i64_to_i1(ptr addrspace(1) %out, i64 %x
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY4]], %subreg.sub0, killed [[COPY3]], %subreg.sub1, killed [[S_MOV_B32_1]], %subreg.sub2, killed [[S_MOV_B32_]], %subreg.sub3
; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub3
- ; GCN-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX4_IMM]].sub2
- ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY5]], %subreg.sub1
- ; GCN-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY killed [[S_LOAD_DWORD_IMM]]
- ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY7]], implicit-def dead $scc
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[DEF]], %subreg.sub0, killed [[COPY5]], %subreg.sub1
+ ; GCN-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY killed [[S_LOAD_DWORD_IMM]]
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY6]], implicit-def dead $scc
; GCN-NEXT: S_CMP_EQ_U32 killed [[S_AND_B32_]], 1, implicit-def $scc
- ; GCN-NEXT: [[COPY8:%[0-9]+]]:sreg_64 = COPY $scc
+ ; GCN-NEXT: [[COPY7:%[0-9]+]]:sreg_64 = COPY $scc
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
- ; GCN-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY killed [[S_MOV_B64_]]
- ; GCN-NEXT: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I64_e64 killed [[REG_SEQUENCE2]], [[COPY9]], implicit $exec
- ; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[V_CMP_LT_I64_e64_]], killed [[COPY8]], implicit-def dead $scc
+ ; GCN-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY killed [[S_MOV_B64_]]
+ ; GCN-NEXT: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I64_e64 killed [[REG_SEQUENCE2]], [[COPY8]], implicit $exec
+ ; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[V_CMP_LT_I64_e64_]], killed [[COPY7]], implicit-def dead $scc
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B64_]], implicit $exec
; GCN-NEXT: BUFFER_STORE_BYTE_OFFSET killed [[V_CNDMASK_B32_e64_]], killed [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec :: (store (s8) into %ir.2, addrspace 1)
; GCN-NEXT: S_ENDPGM 0
@@ -146,17 +148,18 @@ define amdgpu_kernel void @uniform_trunc_i64_to_i1(ptr addrspace(1) %out, i64 %x
define i1 @divergent_trunc_i64_to_i1(ptr addrspace(1) %out, i64 %x, i1 %z) {
; GCN-LABEL: name: divergent_trunc_i64_to_i1
; GCN: bb.0 (%ir-block.0):
- ; GCN-NEXT: liveins: $vgpr2, $vgpr3, $vgpr4
+ ; GCN-NEXT: liveins: $vgpr3, $vgpr4
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
- ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[DEF]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 1, [[COPY]], implicit $exec
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_AND_B32_e64_]], 1, implicit $exec
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[S_MOV_B64_]]
- ; GCN-NEXT: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I64_e64 killed [[REG_SEQUENCE]], [[COPY3]], implicit $exec
+ ; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY killed [[S_MOV_B64_]]
+ ; GCN-NEXT: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I64_e64 killed [[REG_SEQUENCE]], [[COPY2]], implicit $exec
; GCN-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 killed [[V_CMP_LT_I64_e64_]], killed [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed [[S_OR_B64_]], implicit $exec
; GCN-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
index 956145fb24c4a..fc8628e9e7b14 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
@@ -391,12 +391,11 @@ define i1 @posnormal_bf16(bfloat %x) nounwind {
; GFX7CHECK: ; %bb.0:
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
+; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v0
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
; GFX7CHECK-NEXT: v_add_i32_e32 v0, vcc, 0xffffff80, v0
; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7CHECK-NEXT: s_movk_i32 s6, 0x7f00
-; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v1
; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
; GFX7CHECK-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -467,12 +466,11 @@ define i1 @negnormal_bf16(bfloat %x) nounwind {
; GFX7CHECK: ; %bb.0:
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
+; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
; GFX7CHECK-NEXT: v_add_i32_e32 v0, vcc, 0xffffff80, v0
; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7CHECK-NEXT: s_movk_i32 s6, 0x7f00
-; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v1
; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
; GFX7CHECK-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -601,11 +599,10 @@ define i1 @negsubnormal_bf16(bfloat %x) nounwind {
; GFX7CHECK: ; %bb.0:
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
+; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
; GFX7CHECK-NEXT: v_add_i32_e64 v0, s[4:5], -1, v0
; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f
-; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
; GFX7CHECK-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v0
; GFX7CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -826,10 +823,9 @@ define i1 @negfinite_bf16(bfloat %x) nounwind {
; GFX7CHECK: ; %bb.0:
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
+; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v0
; GFX7CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -1634,12 +1630,11 @@ define i1 @not_is_plus_normal_bf16(bfloat %x) {
; GFX7CHECK: ; %bb.0:
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
+; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
; GFX7CHECK-NEXT: v_add_i32_e32 v0, vcc, 0xffffff80, v0
; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7CHECK-NEXT: s_movk_i32 s6, 0x7eff
-; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v1
; GFX7CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
; GFX7CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -1710,12 +1705,11 @@ define i1 @not_is_neg_normal_bf16(bfloat %x) {
; GFX7CHECK: ; %bb.0:
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v1, 16, v0
+; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v0
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
; GFX7CHECK-NEXT: v_add_i32_e32 v0, vcc, 0xffffff80, v0
; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7CHECK-NEXT: s_movk_i32 s6, 0x7eff
-; GFX7CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v1
; GFX7CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
; GFX7CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
@@ -2068,10 +2062,9 @@ define i1 @not_ispositive_bf16(bfloat %x) {
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7CHECK-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v2, 16, v0
+; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
; GFX7CHECK-NEXT: s_movk_i32 s6, 0x7f80
-; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2
; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], s6, v0
; GFX7CHECK-NEXT: s_mov_b32 s7, 0xff80
; GFX7CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
@@ -2165,10 +2158,9 @@ define i1 @isnegative_bf16(bfloat %x) {
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7CHECK-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX7CHECK-NEXT: v_ashrrev_i32_e32 v2, 16, v0
+; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2
; GFX7CHECK-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v0
; GFX7CHECK-NEXT: s_mov_b32 s6, 0xff80
; GFX7CHECK-NEXT: s_and_b64 s[4:5], s[4:5], vcc
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
index dd19ba17bb292..dcb1fe03ef178 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
@@ -570,7 +570,7 @@ define i1 @posnormal_f16(half %x) nounwind {
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
-; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -657,7 +657,7 @@ define i1 @negnormal_f16(half %x) nounwind {
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
-; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -819,7 +819,7 @@ define i1 @negsubnormal_f16(half %x) nounwind {
; GFX7SELDAG: ; %bb.0:
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7SELDAG-NEXT: v_add_i32_e64 v0, s[4:5], -1, v0
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
@@ -1123,7 +1123,7 @@ define i1 @negfinite_f16(half %x) nounwind {
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
-; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v0
@@ -2421,7 +2421,7 @@ define i1 @not_is_plus_normal_f16(half %x) {
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x77ff
-; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -2517,7 +2517,7 @@ define i1 @not_is_neg_normal_f16(half %x) {
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x77ff
-; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -3018,7 +3018,7 @@ define i1 @not_ispositive_f16(half %x) {
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7c00
; GFX7SELDAG-NEXT: s_mov_b32 s7, 0xfc00
-; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v0
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s6, v2
@@ -3109,7 +3109,7 @@ define i1 @isnegative_f16(half %x) {
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
; GFX7SELDAG-NEXT: s_mov_b32 s6, 0xfc00
-; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v0
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v2
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll b/llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll
index 8bdeebef13dd2..2fff15d0b2e4e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll
@@ -702,11 +702,10 @@ entry:
define i32 @vmsk2_sge_allzeros_i8(<32 x i8> %a) {
; LA32-LABEL: vmsk2_sge_allzeros_i8:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: vrepli.b $vr2, 0
-; LA32-NEXT: vsle.b $vr0, $vr2, $vr0
+; LA32-NEXT: vxori.b $vr0, $vr0, 255
; LA32-NEXT: vmskltz.b $vr0, $vr0
; LA32-NEXT: vpickve2gr.hu $a0, $vr0, 0
-; LA32-NEXT: vsle.b $vr0, $vr2, $vr1
+; LA32-NEXT: vxori.b $vr0, $vr1, 255
; LA32-NEXT: vmskltz.b $vr0, $vr0
; LA32-NEXT: vpickve2gr.hu $a1, $vr0, 0
; LA32-NEXT: slli.w $a1, $a1, 16
@@ -715,11 +714,10 @@ define i32 @vmsk2_sge_allzeros_i8(<32 x i8> %a) {
;
; LA64-LABEL: vmsk2_sge_allzeros_i8:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: vrepli.b $vr2, 0
-; LA64-NEXT: vsle.b $vr0, $vr2, $vr0
+; LA64-NEXT: vxori.b $vr0, $vr0, 255
; LA64-NEXT: vmskltz.b $vr0, $vr0
; LA64-NEXT: vpickve2gr.hu $a0, $vr0, 0
-; LA64-NEXT: vsle.b $vr0, $vr2, $vr1
+; LA64-NEXT: vxori.b $vr0, $vr1, 255
; LA64-NEXT: vmskltz.b $vr0, $vr0
; LA64-NEXT: vpickve2gr.hu $a1, $vr0, 0
; LA64-NEXT:...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/171030
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