[clang] [llvm] [RISCV] Add Propeller support for RISC-V (PR #170992)

[via llvm-commits]

https://github.com/leidian977 created https://github.com/llvm/llvm-project/pull/170992

## Summary
This PR adds Propeller optimization framework support to the RISC-V backend.

## Motivation
Currently, LLVM's Propeller is only supported on x86. This limits profile-guided 
optimizations for RISC-V targets. This patch extends Propeller support to RISC-V.

>From c90691476842a90b414949724eacaea1ecc6f472 Mon Sep 17 00:00:00 2001
From: leidian977 <943677770 at qq.com>
Date: Sat, 6 Dec 2025 13:20:34 -0500
Subject: [PATCH] [RISCV] Add basic Propeller infrastructure

---
 clang/lib/Driver/ToolChains/Clang.cpp    | 7 +++++++
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 9 +++++++++
 llvm/lib/Target/RISCV/RISCVInstrInfo.h   | 3 +++
 3 files changed, 19 insertions(+)

diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 0380568412e62..d6b93777b8dd1 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -6128,6 +6128,13 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
             << A->getAsString(Args) << A->getValue();
       else
         A->render(Args, CmdArgs);
+    } else if (Triple.isRISCV() && Triple.isOSBinFormatELF()) {
+      // Add RISC-V support for basic block sections
+      if (Val != "labels" && Val != "none" && !Val.starts_with("list="))
+        D.Diag(diag::err_drv_invalid_value)
+            << A->getAsString(Args) << A->getValue();
+      else
+        A->render(Args, CmdArgs);
     } else if (Triple.isNVPTX()) {
       // Do not pass the option to the GPU compilation. We still want it enabled
       // for the host-side compilation, so seeing it here is not an error.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9fb7ac0573824..269a3ca539635 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -89,6 +89,15 @@ RISCVInstrInfo::RISCVInstrInfo(const RISCVSubtarget &STI)
 #define GET_INSTRINFO_HELPERS
 #include "RISCVGenInstrInfo.inc"
 
+void RISCVInstrInfo::insertNoop(MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator MI) const {
+  DebugLoc DL;
+  BuildMI(MBB, MI, DL, get(RISCV::ADDI))
+      .addReg(RISCV::X0)
+      .addReg(RISCV::X0)
+      .addImm(0);
+}
+
 MCInst RISCVInstrInfo::getNop() const {
   if (STI.hasStdExtZca())
     return MCInstBuilder(RISCV::C_NOP);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 0ffe015b9fac8..bf12c1900be25 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -86,6 +86,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   const RISCVRegisterInfo &getRegisterInfo() const { return RegInfo; }
 
+  void insertNoop(MachineBasicBlock &MBB,
+                  MachineBasicBlock::iterator MI) const override;
+
   MCInst getNop() const override;
 
   Register isLoadFromStackSlot(const MachineInstr &MI,