[llvm] e546d0f - [RISCV][TTI] Add cost model for ROTL/ROTR (#170824)
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Fri Dec 5 18:18:00 PST 2025
Author: Sudharsan Veeravalli
Date: 2025-12-06T07:47:56+05:30
New Revision: e546d0f5d4179ac95e464ea968f7759e61aea8a3
URL: https://github.com/llvm/llvm-project/commit/e546d0f5d4179ac95e464ea968f7759e61aea8a3
DIFF: https://github.com/llvm/llvm-project/commit/e546d0f5d4179ac95e464ea968f7759e61aea8a3.diff
LOG: [RISCV][TTI] Add cost model for ROTL/ROTR (#170824)
A funnel shift with the same first two operands is a rotate. When
`Zbb/Zbkb` is enabled we can use the `ROL(W)/ROR(I)(W)` instruction to
represent this. Add cost model support for this.
Similar to https://github.com/llvm/llvm-project/pull/169335 for AArch64.
Added:
llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll
Modified:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index aedd7f124cef5..afc2f2c9cd07b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1559,6 +1559,23 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
}
break;
}
+ case Intrinsic::fshl:
+ case Intrinsic::fshr: {
+ if (ICA.getArgs().empty())
+ break;
+
+ // Funnel-shifts are ROTL/ROTR when the first and second operand are equal.
+ // When Zbb/Zbkb is enabled we can use a single ROL(W)/ROR(I)(W)
+ // instruction.
+ if ((ST->hasStdExtZbb() || ST->hasStdExtZbkb()) && RetTy->isIntegerTy() &&
+ ICA.getArgs()[0] == ICA.getArgs()[1] &&
+ (RetTy->getIntegerBitWidth() == 32 ||
+ RetTy->getIntegerBitWidth() == 64) &&
+ RetTy->getIntegerBitWidth() <= ST->getXLen()) {
+ return 1;
+ }
+ break;
+ }
case Intrinsic::get_active_lane_mask: {
if (ST->hasVInstructions()) {
Type *ExpRetTy = VectorType::get(
diff --git a/llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll b/llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll
new file mode 100644
index 0000000000000..04e6745d137e4
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll
@@ -0,0 +1,181 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv32 < %s | FileCheck %s --check-prefix=RV32
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv64 < %s | FileCheck %s --check-prefix=RV64
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv32 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV32ZBB
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv64 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV64ZBB
+
+define i32 @rotl_i32_3rd_arg_const(i32 %a) {
+; RV32-LABEL: 'rotl_i32_3rd_arg_const'
+; RV32-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64-LABEL: 'rotl_i32_3rd_arg_const'
+; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV32ZBB-LABEL: 'rotl_i32_3rd_arg_const'
+; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64ZBB-LABEL: 'rotl_i32_3rd_arg_const'
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+entry:
+ %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+ ret i32 %r
+}
+
+define i32 @rotl_i32_3rd_arg_var(i32 %a, i32 %c) {
+; RV32-LABEL: 'rotl_i32_3rd_arg_var'
+; RV32-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64-LABEL: 'rotl_i32_3rd_arg_var'
+; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV32ZBB-LABEL: 'rotl_i32_3rd_arg_var'
+; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64ZBB-LABEL: 'rotl_i32_3rd_arg_var'
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+entry:
+ %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+ ret i32 %r
+}
+
+define i64 @rotl_i64_3rd_arg_const(i64 %a) {
+; RV32-LABEL: 'rotl_i64_3rd_arg_const'
+; RV32-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64-LABEL: 'rotl_i64_3rd_arg_const'
+; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV32ZBB-LABEL: 'rotl_i64_3rd_arg_const'
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64ZBB-LABEL: 'rotl_i64_3rd_arg_const'
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+entry:
+ %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+ ret i64 %r
+}
+
+define i64 @rotl_i64_3rd_arg_var(i64 %a, i64 %c) {
+; RV32-LABEL: 'rotl_i64_3rd_arg_var'
+; RV32-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64-LABEL: 'rotl_i64_3rd_arg_var'
+; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV32ZBB-LABEL: 'rotl_i64_3rd_arg_var'
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64ZBB-LABEL: 'rotl_i64_3rd_arg_var'
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+entry:
+ %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+ ret i64 %r
+}
+
+define i32 @rotr_i32_3rd_arg_const(i32 %a) {
+; RV32-LABEL: 'rotr_i32_3rd_arg_const'
+; RV32-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64-LABEL: 'rotr_i32_3rd_arg_const'
+; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV32ZBB-LABEL: 'rotr_i32_3rd_arg_const'
+; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64ZBB-LABEL: 'rotr_i32_3rd_arg_const'
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+entry:
+ %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+ ret i32 %r
+}
+
+define i32 @rotr_i32_3rd_arg_var(i32 %a, i32 %c) {
+; RV32-LABEL: 'rotr_i32_3rd_arg_var'
+; RV32-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64-LABEL: 'rotr_i32_3rd_arg_var'
+; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV32ZBB-LABEL: 'rotr_i32_3rd_arg_var'
+; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64ZBB-LABEL: 'rotr_i32_3rd_arg_var'
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+entry:
+ %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+ ret i32 %r
+}
+
+define i64 @rotr_i64_3rd_arg_const(i64 %a) {
+; RV32-LABEL: 'rotr_i64_3rd_arg_const'
+; RV32-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64-LABEL: 'rotr_i64_3rd_arg_const'
+; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV32ZBB-LABEL: 'rotr_i64_3rd_arg_const'
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64ZBB-LABEL: 'rotr_i64_3rd_arg_const'
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+entry:
+ %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+ ret i64 %r
+}
+
+define i64 @rotr_i64_3rd_arg_var(i64 %a, i64 %c) {
+; RV32-LABEL: 'rotr_i64_3rd_arg_var'
+; RV32-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64-LABEL: 'rotr_i64_3rd_arg_var'
+; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV32ZBB-LABEL: 'rotr_i64_3rd_arg_var'
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64ZBB-LABEL: 'rotr_i64_3rd_arg_var'
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+entry:
+ %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+ ret i64 %r
+}
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