[llvm] [docs] [RISCV] Update docs regarding RV32E/RV64E (PR #170707)

[Sam Elliott via llvm-commits]

lenary wrote:

> > I'm not sure these are "fully supported". iirc the ABIs are unstable
> 
> yes. This is mentioned in another place in the guide, mentioning that the ABI is experimental. But maybe it would be good to mention that here as well. I get the impression that this experimentalness is more due to psABI/standard issues, rather than any flaws in the support, is this impression correct?

Oh, I see that we already have a note about this. Can you just cross-reference to it, the ref is `riscv-rve-note`. The difficutly is the only ABIs for RV32E/RV64E are the experimental abis. 

> 
> > and i think there are some compiler features that don't work with rv32e/rv64e because they require using a higher register (t3?)
> 
> Yes. This would be good to mention, but I would need some more details, I am not intimately familiar in this area.

Grepping for `X28` in the backend points to the following features:
- hwasan (I'm not sure whether this is expected to be supported on not-linux)
- nested functions when using "cf-protection-branch" (i don't know the user-facing name for this, it's control-flow related)
- Kernel CFI

> 
> > Maybe we need a separate section listing out limitations for rv32e/rv64e?
> 
> I will be happy to help with this, but it will take more work. Meanwhile "assembler-only" is /more/ incorrect.
> 
> How about mentioning "experimentalness" here as well, and making an issue for creating a more specific list?

Link to the existing note is good enough, I now realise.


https://github.com/llvm/llvm-project/pull/170707