[llvm] [RISCV][TTI] Add cost model for ROTL/ROTR (PR #170824)
Sudharsan Veeravalli via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 5 09:16:48 PST 2025
https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/170824
>From 7747e248c05843a15b6b7c5c2e3d5c7d774137cf Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Fri, 5 Dec 2025 14:07:34 +0530
Subject: [PATCH 1/3] Pre-commit test
---
.../Analysis/CostModel/RISCV/fshl_fshr.ll | 181 ++++++++++++++++++
1 file changed, 181 insertions(+)
create mode 100644 llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll
diff --git a/llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll b/llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll
new file mode 100644
index 0000000000000..830a44af5779c
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll
@@ -0,0 +1,181 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv32 < %s | FileCheck %s --check-prefix=RV32
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv64 < %s | FileCheck %s --check-prefix=RV64
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv32 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV32ZBB
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv64 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV64ZBB
+
+define i32 @rotl_i32_3rd_arg_const(i32 %a) {
+; RV32-LABEL: 'rotl_i32_3rd_arg_const'
+; RV32-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64-LABEL: 'rotl_i32_3rd_arg_const'
+; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV32ZBB-LABEL: 'rotl_i32_3rd_arg_const'
+; RV32ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64ZBB-LABEL: 'rotl_i32_3rd_arg_const'
+; RV64ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+entry:
+ %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+ ret i32 %r
+}
+
+define i32 @rotl_i32_3rd_arg_var(i32 %a, i32 %c) {
+; RV32-LABEL: 'rotl_i32_3rd_arg_var'
+; RV32-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64-LABEL: 'rotl_i32_3rd_arg_var'
+; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV32ZBB-LABEL: 'rotl_i32_3rd_arg_var'
+; RV32ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64ZBB-LABEL: 'rotl_i32_3rd_arg_var'
+; RV64ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+entry:
+ %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+ ret i32 %r
+}
+
+define i64 @rotl_i64_3rd_arg_const(i64 %a) {
+; RV32-LABEL: 'rotl_i64_3rd_arg_const'
+; RV32-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64-LABEL: 'rotl_i64_3rd_arg_const'
+; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV32ZBB-LABEL: 'rotl_i64_3rd_arg_const'
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64ZBB-LABEL: 'rotl_i64_3rd_arg_const'
+; RV64ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+entry:
+ %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+ ret i64 %r
+}
+
+define i64 @rotl_i64_3rd_arg_var(i64 %a, i64 %c) {
+; RV32-LABEL: 'rotl_i64_3rd_arg_var'
+; RV32-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64-LABEL: 'rotl_i64_3rd_arg_var'
+; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV32ZBB-LABEL: 'rotl_i64_3rd_arg_var'
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64ZBB-LABEL: 'rotl_i64_3rd_arg_var'
+; RV64ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+entry:
+ %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+ ret i64 %r
+}
+
+define i32 @rotr_i32_3rd_arg_const(i32 %a) {
+; RV32-LABEL: 'rotr_i32_3rd_arg_const'
+; RV32-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64-LABEL: 'rotr_i32_3rd_arg_const'
+; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV32ZBB-LABEL: 'rotr_i32_3rd_arg_const'
+; RV32ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64ZBB-LABEL: 'rotr_i32_3rd_arg_const'
+; RV64ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+entry:
+ %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+ ret i32 %r
+}
+
+define i32 @rotr_i32_3rd_arg_var(i32 %a, i32 %c) {
+; RV32-LABEL: 'rotr_i32_3rd_arg_var'
+; RV32-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64-LABEL: 'rotr_i32_3rd_arg_var'
+; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV32ZBB-LABEL: 'rotr_i32_3rd_arg_var'
+; RV32ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+; RV64ZBB-LABEL: 'rotr_i32_3rd_arg_var'
+; RV64ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
+;
+entry:
+ %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+ ret i32 %r
+}
+
+define i64 @rotr_i64_3rd_arg_const(i64 %a) {
+; RV32-LABEL: 'rotr_i64_3rd_arg_const'
+; RV32-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64-LABEL: 'rotr_i64_3rd_arg_const'
+; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV32ZBB-LABEL: 'rotr_i64_3rd_arg_const'
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64ZBB-LABEL: 'rotr_i64_3rd_arg_const'
+; RV64ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+entry:
+ %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+ ret i64 %r
+}
+
+define i64 @rotr_i64_3rd_arg_var(i64 %a, i64 %c) {
+; RV32-LABEL: 'rotr_i64_3rd_arg_var'
+; RV32-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64-LABEL: 'rotr_i64_3rd_arg_var'
+; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV32ZBB-LABEL: 'rotr_i64_3rd_arg_var'
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+; RV64ZBB-LABEL: 'rotr_i64_3rd_arg_var'
+; RV64ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
+;
+entry:
+ %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+ ret i64 %r
+}
>From ee005a511f021125b468ad34d795b415dbd5e7c9 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Fri, 5 Dec 2025 14:50:52 +0530
Subject: [PATCH 2/3] Cost model
---
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 14 +++++++++++
.../Analysis/CostModel/RISCV/fshl_fshr.ll | 24 +++++++++----------
2 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index aedd7f124cef5..d146a2d60d874 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1559,6 +1559,20 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
}
break;
}
+ case Intrinsic::fshl:
+ case Intrinsic::fshr: {
+ // Funnel-shifts are ROTL/ROTR when the first and second operand are equal.
+ // When Zbb/Zbkb is enabled we can use a single ROL(W)/ROR(I)(W)
+ // instruction.
+ if ((ST->hasStdExtZbb() || ST->hasStdExtZbkb()) && RetTy->isIntegerTy() &&
+ ICA.getArgs()[0] == ICA.getArgs()[1] &&
+ (RetTy->getPrimitiveSizeInBits() == 32 ||
+ RetTy->getPrimitiveSizeInBits() == 64) &&
+ RetTy->getPrimitiveSizeInBits() <= ST->getXLen()) {
+ return 1;
+ }
+ break;
+ }
case Intrinsic::get_active_lane_mask: {
if (ST->hasVInstructions()) {
Type *ExpRetTy = VectorType::get(
diff --git a/llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll b/llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll
index 830a44af5779c..04e6745d137e4 100644
--- a/llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll
@@ -14,11 +14,11 @@ define i32 @rotl_i32_3rd_arg_const(i32 %a) {
; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV32ZBB-LABEL: 'rotl_i32_3rd_arg_const'
-; RV32ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64ZBB-LABEL: 'rotl_i32_3rd_arg_const'
-; RV64ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
entry:
@@ -36,11 +36,11 @@ define i32 @rotl_i32_3rd_arg_var(i32 %a, i32 %c) {
; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV32ZBB-LABEL: 'rotl_i32_3rd_arg_var'
-; RV32ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64ZBB-LABEL: 'rotl_i32_3rd_arg_var'
-; RV64ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
entry:
@@ -62,7 +62,7 @@ define i64 @rotl_i64_3rd_arg_const(i64 %a) {
; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64ZBB-LABEL: 'rotl_i64_3rd_arg_const'
-; RV64ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
entry:
@@ -84,7 +84,7 @@ define i64 @rotl_i64_3rd_arg_var(i64 %a, i64 %c) {
; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64ZBB-LABEL: 'rotl_i64_3rd_arg_var'
-; RV64ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
entry:
@@ -102,11 +102,11 @@ define i32 @rotr_i32_3rd_arg_const(i32 %a) {
; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV32ZBB-LABEL: 'rotr_i32_3rd_arg_const'
-; RV32ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64ZBB-LABEL: 'rotr_i32_3rd_arg_const'
-; RV64ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
entry:
@@ -124,11 +124,11 @@ define i32 @rotr_i32_3rd_arg_var(i32 %a, i32 %c) {
; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV32ZBB-LABEL: 'rotr_i32_3rd_arg_var'
-; RV32ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
; RV64ZBB-LABEL: 'rotr_i32_3rd_arg_var'
-; RV64ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
;
entry:
@@ -150,7 +150,7 @@ define i64 @rotr_i64_3rd_arg_const(i64 %a) {
; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64ZBB-LABEL: 'rotr_i64_3rd_arg_const'
-; RV64ZBB-NEXT: Cost Model: Found costs of 4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
entry:
@@ -172,7 +172,7 @@ define i64 @rotr_i64_3rd_arg_var(i64 %a, i64 %c) {
; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
; RV64ZBB-LABEL: 'rotr_i64_3rd_arg_var'
-; RV64ZBB-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
+; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
;
entry:
>From c2c79f3eea96fc702232a832ad2b8b610705ece3 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Fri, 5 Dec 2025 22:46:12 +0530
Subject: [PATCH 3/3] Add empty check
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index d146a2d60d874..cca6981292c0f 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1561,6 +1561,9 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
}
case Intrinsic::fshl:
case Intrinsic::fshr: {
+ if (ICA.getArgs().empty())
+ break;
+
// Funnel-shifts are ROTL/ROTR when the first and second operand are equal.
// When Zbb/Zbkb is enabled we can use a single ROL(W)/ROR(I)(W)
// instruction.
More information about the llvm-commits
mailing list