[llvm] [AArch64] Allow single-element vector FP converts with +fprcvt (PR #169692)
Amina Chabane via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 5 08:13:28 PST 2025
https://github.com/Amichaxx updated https://github.com/llvm/llvm-project/pull/169692
>From 04b2e863edce75db6840ec68155dab7fed9443c1 Mon Sep 17 00:00:00 2001
From: Amichaxx <amina.chabane at arm.com>
Date: Tue, 25 Nov 2025 14:23:39 +0000
Subject: [PATCH 1/4] Allow single-element vector FP converts with +fprcvt
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 12 +-
llvm/lib/Target/AArch64/AArch64Subtarget.h | 4 +
.../sve-streaming-mode-cvt-fp-int-fp.ll | 218 ++++++++++++------
3 files changed, 160 insertions(+), 74 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0d63a9121310e..0fa5ca8e21b9c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -329,8 +329,8 @@ def HasNEONandIsStreamingSafe
: Predicate<"Subtarget->hasNEON()">,
AssemblerPredicateWithAll<(any_of FeatureNEON), "neon">;
// A subset of NEON instructions are legal in Streaming SVE mode only with +sme2p2.
-def HasNEONandIsSME2p2StreamingSafe
- : Predicate<"Subtarget->isNeonAvailable() || (Subtarget->hasNEON() && Subtarget->hasSME2p2())">,
+def HasNEONandFPRCVTIsStreamingSafe
+ : Predicate<"Subtarget->isNeonAvailable() || (Subtarget->hasNEON() && Subtarget->isFPRCVTStreamingSafe())">,
AssemblerPredicateWithAll<(any_of FeatureNEON), "neon">;
def HasRCPC : Predicate<"Subtarget->hasRCPC()">,
AssemblerPredicateWithAll<(all_of FeatureRCPC), "rcpc">;
@@ -6952,7 +6952,7 @@ let HasOneUse = 1 in {
def any_fp_to_sint_oneuse: PatFrag<(ops node:$src0), (any_fp_to_sint $src0)>;
def any_fp_to_uint_oneuse: PatFrag<(ops node:$src0), (any_fp_to_uint $src0)>;
}
-let Predicates = [HasNEONandIsSME2p2StreamingSafe] in {
+let Predicates = [HasNEONandFPRCVTIsStreamingSafe] in {
def : Pat<(f64 (any_sint_to_fp (i64 (any_fp_to_sint_oneuse f64:$Rn)))),
(SCVTFv1i64 (i64 (FCVTZSv1i64 f64:$Rn)))>;
def : Pat<(f32 (any_sint_to_fp (i32 (any_fp_to_sint_oneuse f32:$Rn)))),
@@ -6962,7 +6962,7 @@ def : Pat<(f64 (any_uint_to_fp (i64 (any_fp_to_uint_oneuse f64:$Rn)))),
def : Pat<(f32 (any_uint_to_fp (i32 (any_fp_to_uint_oneuse f32:$Rn)))),
(UCVTFv1i32 (i32 (FCVTZUv1i32 f32:$Rn)))>;
-let Predicates = [HasNEONandIsSME2p2StreamingSafe, HasFullFP16] in {
+let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : Pat<(f16 (any_sint_to_fp (i32 (any_fp_to_sint_oneuse f16:$Rn)))),
(SCVTFv1i16 (f16 (FCVTZSv1f16 f16:$Rn)))>;
def : Pat<(f16 (any_uint_to_fp (i32 (any_fp_to_uint_oneuse f16:$Rn)))),
@@ -6994,7 +6994,7 @@ def : Pat<(f64 (uint_to_fp (i64 (vector_extract (v2i64 FPR128:$Rn), (i64 0))))),
// fp16: integer extraction from vector must be at least 32-bits to be legal.
// Actual extraction result is then an in-reg sign-extension of lower 16-bits.
-let Predicates = [HasNEONandIsSME2p2StreamingSafe, HasFullFP16] in {
+let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : Pat<(f16 (sint_to_fp (i32 (sext_inreg (i32 (vector_extract
(v8i16 FPR128:$Rn), (i64 0))), i16)))),
(SCVTFv1i16 (f16 (EXTRACT_SUBREG (v8i16 FPR128:$Rn), hsub)))>;
@@ -7028,7 +7028,7 @@ multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
sub))>;
}
-let Predicates = [HasNEONandIsSME2p2StreamingSafe, HasFullFP16] in {
+let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
defm : UIntToFPROLoadPat<f16, i32, zextloadi8,
UCVTFv1i16, ro8, LDRBroW, LDRBroX, bsub>;
def : Pat <(f16 (uint_to_fp (i32
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 8974965c41fe3..9edb524b16f18 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -217,6 +217,10 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
return isSVEAvailable() || (isSVEorStreamingSVEAvailable() && hasSME2());
}
+ bool isFPRCVTStreamingSafe() const {
+ return hasFPRCVT() && (!hasSMEFA64() && (isStreaming() || isStreamingCompatible()));
+ }
+
unsigned getMinVectorRegisterBitWidth() const {
// Don't assume any minimum vector size when PSTATE.SM may not be 0, because
// we don't yet support streaming-compatible codegen support that we trust
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
index 4ad5b38b256fe..5bb7674c684ed 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
@@ -1,19 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
-; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s
-; RUN: llc -mattr=+sme2p2 -force-streaming-compatible < %s | FileCheck %s --check-prefix=USE-NEON-NO-GPRS
-; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
+; RUN: llc -force-streaming-compatible < %s | FileCheck %s
+; RUN: llc -force-streaming-compatible -mattr=+fprcvt,+fullfp16 < %s | FileCheck %s --check-prefix=USE-NEON-NO-GPRS
+; RUN: llc -force-streaming-compatible -mattr=+fprcvt,+fullfp16,-neon < %s | FileCheck %s --check-prefix=NO-NEON
+; RUN: llc < %s | FileCheck %s --check-prefix=CHECK-NO-STREAMING
target triple = "aarch64-unknown-linux-gnu"
define double @t1(double %x) {
; CHECK-LABEL: t1:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
-; CHECK-NEXT: scvtf z0.d, p0/m, z0.d
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT: fcvtzs x8, d0
+; CHECK-NEXT: scvtf d0, x8
; CHECK-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t1:
@@ -22,11 +19,27 @@ define double @t1(double %x) {
; USE-NEON-NO-GPRS-NEXT: scvtf d0, d0
; USE-NEON-NO-GPRS-NEXT: ret
;
-; NONEON-NOSVE-LABEL: t1:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvtzs x8, d0
-; NONEON-NOSVE-NEXT: scvtf d0, x8
-; NONEON-NOSVE-NEXT: ret
+; NO-NEON-LABEL: t1:
+; NO-NEON: // %bb.0: // %entry
+; NO-NEON-NEXT: fcvtzs x8, d0
+; NO-NEON-NEXT: scvtf d0, x8
+; NO-NEON-NEXT: ret
+;
+; CHECK-NO-STREAMING-LABEL: t1:
+; CHECK-NO-STREAMING: // %bb.0: // %entry
+; CHECK-NO-STREAMING-NEXT: fcvtzs d0, d0
+; CHECK-NO-STREAMING-NEXT: scvtf d0, d0
+; CHECK-NO-STREAMING-NEXT: ret
+; NO-NEON-NO-GPRS-LABEL: t1:
+; NO-NEON-NO-GPRS: // %bb.0: // %entry
+; NO-NEON-NO-GPRS-NEXT: fcvtzs x8, d0
+; NO-NEON-NO-GPRS-NEXT: scvtf d0, x8
+; NO-NEON-NO-GPRS-NEXT: ret
+; USE-NEON-LABEL: t1:
+; USE-NEON: // %bb.0: // %entry
+; USE-NEON-NEXT: fcvtzs d0, d0
+; USE-NEON-NEXT: scvtf d0, d0
+; USE-NEON-NEXT: ret
entry:
%conv = fptosi double %x to i64
%conv1 = sitofp i64 %conv to double
@@ -36,11 +49,8 @@ entry:
define float @t2(float %x) {
; CHECK-LABEL: t2:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0
-; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
-; CHECK-NEXT: scvtf z0.s, p0/m, z0.s
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: scvtf s0, w8
; CHECK-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t2:
@@ -49,11 +59,27 @@ define float @t2(float %x) {
; USE-NEON-NO-GPRS-NEXT: scvtf s0, s0
; USE-NEON-NO-GPRS-NEXT: ret
;
-; NONEON-NOSVE-LABEL: t2:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvtzs w8, s0
-; NONEON-NOSVE-NEXT: scvtf s0, w8
-; NONEON-NOSVE-NEXT: ret
+; NO-NEON-LABEL: t2:
+; NO-NEON: // %bb.0: // %entry
+; NO-NEON-NEXT: fcvtzs w8, s0
+; NO-NEON-NEXT: scvtf s0, w8
+; NO-NEON-NEXT: ret
+;
+; CHECK-NO-STREAMING-LABEL: t2:
+; CHECK-NO-STREAMING: // %bb.0: // %entry
+; CHECK-NO-STREAMING-NEXT: fcvtzs s0, s0
+; CHECK-NO-STREAMING-NEXT: scvtf s0, s0
+; CHECK-NO-STREAMING-NEXT: ret
+; NO-NEON-NO-GPRS-LABEL: t2:
+; NO-NEON-NO-GPRS: // %bb.0: // %entry
+; NO-NEON-NO-GPRS-NEXT: fcvtzs w8, s0
+; NO-NEON-NO-GPRS-NEXT: scvtf s0, w8
+; NO-NEON-NO-GPRS-NEXT: ret
+; USE-NEON-LABEL: t2:
+; USE-NEON: // %bb.0: // %entry
+; USE-NEON-NEXT: fcvtzs s0, s0
+; USE-NEON-NEXT: scvtf s0, s0
+; USE-NEON-NEXT: ret
entry:
%conv = fptosi float %x to i32
%conv1 = sitofp i32 %conv to float
@@ -63,11 +89,10 @@ entry:
define half @t3(half %x) {
; CHECK-LABEL: t3:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
-; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
-; CHECK-NEXT: scvtf z0.h, p0/m, z0.s
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: scvtf s0, w8
+; CHECK-NEXT: fcvt h0, s0
; CHECK-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t3:
@@ -76,13 +101,29 @@ define half @t3(half %x) {
; USE-NEON-NO-GPRS-NEXT: scvtf h0, h0
; USE-NEON-NO-GPRS-NEXT: ret
;
-; NONEON-NOSVE-LABEL: t3:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvt s0, h0
-; NONEON-NOSVE-NEXT: fcvtzs w8, s0
-; NONEON-NOSVE-NEXT: scvtf s0, w8
-; NONEON-NOSVE-NEXT: fcvt h0, s0
-; NONEON-NOSVE-NEXT: ret
+; NO-NEON-LABEL: t3:
+; NO-NEON: // %bb.0: // %entry
+; NO-NEON-NEXT: fcvtzs w8, h0
+; NO-NEON-NEXT: scvtf h0, w8
+; NO-NEON-NEXT: ret
+;
+; CHECK-NO-STREAMING-LABEL: t3:
+; CHECK-NO-STREAMING: // %bb.0: // %entry
+; CHECK-NO-STREAMING-NEXT: fcvt s0, h0
+; CHECK-NO-STREAMING-NEXT: fcvtzs s0, s0
+; CHECK-NO-STREAMING-NEXT: scvtf s0, s0
+; CHECK-NO-STREAMING-NEXT: fcvt h0, s0
+; CHECK-NO-STREAMING-NEXT: ret
+; NO-NEON-NO-GPRS-LABEL: t3:
+; NO-NEON-NO-GPRS: // %bb.0: // %entry
+; NO-NEON-NO-GPRS-NEXT: fcvtzs w8, h0
+; NO-NEON-NO-GPRS-NEXT: scvtf h0, w8
+; NO-NEON-NO-GPRS-NEXT: ret
+; USE-NEON-LABEL: t3:
+; USE-NEON: // %bb.0: // %entry
+; USE-NEON-NEXT: fcvtzs h0, h0
+; USE-NEON-NEXT: scvtf h0, h0
+; USE-NEON-NEXT: ret
entry:
%conv = fptosi half %x to i32
%conv1 = sitofp i32 %conv to half
@@ -92,11 +133,8 @@ entry:
define double @t4(double %x) {
; CHECK-LABEL: t4:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
-; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT: fcvtzu x8, d0
+; CHECK-NEXT: ucvtf d0, x8
; CHECK-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t4:
@@ -105,11 +143,27 @@ define double @t4(double %x) {
; USE-NEON-NO-GPRS-NEXT: ucvtf d0, d0
; USE-NEON-NO-GPRS-NEXT: ret
;
-; NONEON-NOSVE-LABEL: t4:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvtzu x8, d0
-; NONEON-NOSVE-NEXT: ucvtf d0, x8
-; NONEON-NOSVE-NEXT: ret
+; NO-NEON-LABEL: t4:
+; NO-NEON: // %bb.0: // %entry
+; NO-NEON-NEXT: fcvtzu x8, d0
+; NO-NEON-NEXT: ucvtf d0, x8
+; NO-NEON-NEXT: ret
+;
+; CHECK-NO-STREAMING-LABEL: t4:
+; CHECK-NO-STREAMING: // %bb.0: // %entry
+; CHECK-NO-STREAMING-NEXT: fcvtzu d0, d0
+; CHECK-NO-STREAMING-NEXT: ucvtf d0, d0
+; CHECK-NO-STREAMING-NEXT: ret
+; NO-NEON-NO-GPRS-LABEL: t4:
+; NO-NEON-NO-GPRS: // %bb.0: // %entry
+; NO-NEON-NO-GPRS-NEXT: fcvtzu x8, d0
+; NO-NEON-NO-GPRS-NEXT: ucvtf d0, x8
+; NO-NEON-NO-GPRS-NEXT: ret
+; USE-NEON-LABEL: t4:
+; USE-NEON: // %bb.0: // %entry
+; USE-NEON-NEXT: fcvtzu d0, d0
+; USE-NEON-NEXT: ucvtf d0, d0
+; USE-NEON-NEXT: ret
entry:
%conv = fptoui double %x to i64
%conv1 = uitofp i64 %conv to double
@@ -119,11 +173,8 @@ entry:
define float @t5(float %x) {
; CHECK-LABEL: t5:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0
-; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
-; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: ucvtf s0, w8
; CHECK-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t5:
@@ -132,11 +183,27 @@ define float @t5(float %x) {
; USE-NEON-NO-GPRS-NEXT: ucvtf s0, s0
; USE-NEON-NO-GPRS-NEXT: ret
;
-; NONEON-NOSVE-LABEL: t5:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvtzu w8, s0
-; NONEON-NOSVE-NEXT: ucvtf s0, w8
-; NONEON-NOSVE-NEXT: ret
+; NO-NEON-LABEL: t5:
+; NO-NEON: // %bb.0: // %entry
+; NO-NEON-NEXT: fcvtzu w8, s0
+; NO-NEON-NEXT: ucvtf s0, w8
+; NO-NEON-NEXT: ret
+;
+; CHECK-NO-STREAMING-LABEL: t5:
+; CHECK-NO-STREAMING: // %bb.0: // %entry
+; CHECK-NO-STREAMING-NEXT: fcvtzu s0, s0
+; CHECK-NO-STREAMING-NEXT: ucvtf s0, s0
+; CHECK-NO-STREAMING-NEXT: ret
+; NO-NEON-NO-GPRS-LABEL: t5:
+; NO-NEON-NO-GPRS: // %bb.0: // %entry
+; NO-NEON-NO-GPRS-NEXT: fcvtzu w8, s0
+; NO-NEON-NO-GPRS-NEXT: ucvtf s0, w8
+; NO-NEON-NO-GPRS-NEXT: ret
+; USE-NEON-LABEL: t5:
+; USE-NEON: // %bb.0: // %entry
+; USE-NEON-NEXT: fcvtzu s0, s0
+; USE-NEON-NEXT: ucvtf s0, s0
+; USE-NEON-NEXT: ret
entry:
%conv = fptoui float %x to i32
%conv1 = uitofp i32 %conv to float
@@ -146,11 +213,10 @@ entry:
define half @t6(half %x) {
; CHECK-LABEL: t6:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
-; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
-; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: ucvtf s0, w8
+; CHECK-NEXT: fcvt h0, s0
; CHECK-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t6:
@@ -159,13 +225,29 @@ define half @t6(half %x) {
; USE-NEON-NO-GPRS-NEXT: ucvtf h0, h0
; USE-NEON-NO-GPRS-NEXT: ret
;
-; NONEON-NOSVE-LABEL: t6:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvt s0, h0
-; NONEON-NOSVE-NEXT: fcvtzu w8, s0
-; NONEON-NOSVE-NEXT: ucvtf s0, w8
-; NONEON-NOSVE-NEXT: fcvt h0, s0
-; NONEON-NOSVE-NEXT: ret
+; NO-NEON-LABEL: t6:
+; NO-NEON: // %bb.0: // %entry
+; NO-NEON-NEXT: fcvtzu w8, h0
+; NO-NEON-NEXT: ucvtf h0, w8
+; NO-NEON-NEXT: ret
+;
+; CHECK-NO-STREAMING-LABEL: t6:
+; CHECK-NO-STREAMING: // %bb.0: // %entry
+; CHECK-NO-STREAMING-NEXT: fcvt s0, h0
+; CHECK-NO-STREAMING-NEXT: fcvtzu s0, s0
+; CHECK-NO-STREAMING-NEXT: ucvtf s0, s0
+; CHECK-NO-STREAMING-NEXT: fcvt h0, s0
+; CHECK-NO-STREAMING-NEXT: ret
+; NO-NEON-NO-GPRS-LABEL: t6:
+; NO-NEON-NO-GPRS: // %bb.0: // %entry
+; NO-NEON-NO-GPRS-NEXT: fcvtzu w8, h0
+; NO-NEON-NO-GPRS-NEXT: ucvtf h0, w8
+; NO-NEON-NO-GPRS-NEXT: ret
+; USE-NEON-LABEL: t6:
+; USE-NEON: // %bb.0: // %entry
+; USE-NEON-NEXT: fcvtzu h0, h0
+; USE-NEON-NEXT: ucvtf h0, h0
+; USE-NEON-NEXT: ret
entry:
%conv = fptoui half %x to i32
%conv1 = uitofp i32 %conv to half
>From fd13366c4c9749a41ccce19c7862a9e127509a44 Mon Sep 17 00:00:00 2001
From: Amichaxx <amina.chabane at arm.com>
Date: Wed, 26 Nov 2025 17:35:21 +0000
Subject: [PATCH 2/4] Updated run lines
---
llvm/lib/Target/AArch64/AArch64Subtarget.h | 3 +-
.../sve-streaming-mode-cvt-fp-int-fp.ll | 220 +++++++++---------
2 files changed, 110 insertions(+), 113 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 9edb524b16f18..8d20498b4c68e 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -218,7 +218,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
}
bool isFPRCVTStreamingSafe() const {
- return hasFPRCVT() && (!hasSMEFA64() && (isStreaming() || isStreamingCompatible()));
+ return hasFPRCVT() &&
+ (!hasSMEFA64() && (isStreaming() || isStreamingCompatible()));
}
unsigned getMinVectorRegisterBitWidth() const {
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
index 5bb7674c684ed..bd4b1e3e7580f 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
@@ -1,18 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -force-streaming-compatible < %s | FileCheck %s
+; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
+; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s
+; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=CHECK-STREAMING
; RUN: llc -force-streaming-compatible -mattr=+fprcvt,+fullfp16 < %s | FileCheck %s --check-prefix=USE-NEON-NO-GPRS
; RUN: llc -force-streaming-compatible -mattr=+fprcvt,+fullfp16,-neon < %s | FileCheck %s --check-prefix=NO-NEON
-; RUN: llc < %s | FileCheck %s --check-prefix=CHECK-NO-STREAMING
+; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
target triple = "aarch64-unknown-linux-gnu"
define double @t1(double %x) {
; CHECK-LABEL: t1:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs x8, d0
-; CHECK-NEXT: scvtf d0, x8
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: scvtf z0.d, p0/m, z0.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
+; CHECK-STREAMING-LABEL: t1:
+; CHECK-STREAMING: // %bb.0: // %entry
+; CHECK-STREAMING-NEXT: fcvtzs x8, d0
+; CHECK-STREAMING-NEXT: scvtf d0, x8
+; CHECK-STREAMING-NEXT: ret
+;
; USE-NEON-NO-GPRS-LABEL: t1:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzs d0, d0
@@ -25,21 +36,11 @@ define double @t1(double %x) {
; NO-NEON-NEXT: scvtf d0, x8
; NO-NEON-NEXT: ret
;
-; CHECK-NO-STREAMING-LABEL: t1:
-; CHECK-NO-STREAMING: // %bb.0: // %entry
-; CHECK-NO-STREAMING-NEXT: fcvtzs d0, d0
-; CHECK-NO-STREAMING-NEXT: scvtf d0, d0
-; CHECK-NO-STREAMING-NEXT: ret
-; NO-NEON-NO-GPRS-LABEL: t1:
-; NO-NEON-NO-GPRS: // %bb.0: // %entry
-; NO-NEON-NO-GPRS-NEXT: fcvtzs x8, d0
-; NO-NEON-NO-GPRS-NEXT: scvtf d0, x8
-; NO-NEON-NO-GPRS-NEXT: ret
-; USE-NEON-LABEL: t1:
-; USE-NEON: // %bb.0: // %entry
-; USE-NEON-NEXT: fcvtzs d0, d0
-; USE-NEON-NEXT: scvtf d0, d0
-; USE-NEON-NEXT: ret
+; NONEON-NOSVE-LABEL: t1:
+; NONEON-NOSVE: // %bb.0: // %entry
+; NONEON-NOSVE-NEXT: fcvtzs x8, d0
+; NONEON-NOSVE-NEXT: scvtf d0, x8
+; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptosi double %x to i64
%conv1 = sitofp i64 %conv to double
@@ -49,10 +50,19 @@ entry:
define float @t2(float %x) {
; CHECK-LABEL: t2:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: scvtf s0, w8
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: scvtf z0.s, p0/m, z0.s
+; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0
; CHECK-NEXT: ret
;
+; CHECK-STREAMING-LABEL: t2:
+; CHECK-STREAMING: // %bb.0: // %entry
+; CHECK-STREAMING-NEXT: fcvtzs w8, s0
+; CHECK-STREAMING-NEXT: scvtf s0, w8
+; CHECK-STREAMING-NEXT: ret
+;
; USE-NEON-NO-GPRS-LABEL: t2:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzs s0, s0
@@ -65,21 +75,11 @@ define float @t2(float %x) {
; NO-NEON-NEXT: scvtf s0, w8
; NO-NEON-NEXT: ret
;
-; CHECK-NO-STREAMING-LABEL: t2:
-; CHECK-NO-STREAMING: // %bb.0: // %entry
-; CHECK-NO-STREAMING-NEXT: fcvtzs s0, s0
-; CHECK-NO-STREAMING-NEXT: scvtf s0, s0
-; CHECK-NO-STREAMING-NEXT: ret
-; NO-NEON-NO-GPRS-LABEL: t2:
-; NO-NEON-NO-GPRS: // %bb.0: // %entry
-; NO-NEON-NO-GPRS-NEXT: fcvtzs w8, s0
-; NO-NEON-NO-GPRS-NEXT: scvtf s0, w8
-; NO-NEON-NO-GPRS-NEXT: ret
-; USE-NEON-LABEL: t2:
-; USE-NEON: // %bb.0: // %entry
-; USE-NEON-NEXT: fcvtzs s0, s0
-; USE-NEON-NEXT: scvtf s0, s0
-; USE-NEON-NEXT: ret
+; NONEON-NOSVE-LABEL: t2:
+; NONEON-NOSVE: // %bb.0: // %entry
+; NONEON-NOSVE-NEXT: fcvtzs w8, s0
+; NONEON-NOSVE-NEXT: scvtf s0, w8
+; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptosi float %x to i32
%conv1 = sitofp i32 %conv to float
@@ -89,12 +89,21 @@ entry:
define half @t3(half %x) {
; CHECK-LABEL: t3:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: scvtf s0, w8
-; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
+; CHECK-NEXT: scvtf z0.h, p0/m, z0.s
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
; CHECK-NEXT: ret
;
+; CHECK-STREAMING-LABEL: t3:
+; CHECK-STREAMING: // %bb.0: // %entry
+; CHECK-STREAMING-NEXT: fcvt s0, h0
+; CHECK-STREAMING-NEXT: fcvtzs w8, s0
+; CHECK-STREAMING-NEXT: scvtf s0, w8
+; CHECK-STREAMING-NEXT: fcvt h0, s0
+; CHECK-STREAMING-NEXT: ret
+;
; USE-NEON-NO-GPRS-LABEL: t3:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzs h0, h0
@@ -107,23 +116,13 @@ define half @t3(half %x) {
; NO-NEON-NEXT: scvtf h0, w8
; NO-NEON-NEXT: ret
;
-; CHECK-NO-STREAMING-LABEL: t3:
-; CHECK-NO-STREAMING: // %bb.0: // %entry
-; CHECK-NO-STREAMING-NEXT: fcvt s0, h0
-; CHECK-NO-STREAMING-NEXT: fcvtzs s0, s0
-; CHECK-NO-STREAMING-NEXT: scvtf s0, s0
-; CHECK-NO-STREAMING-NEXT: fcvt h0, s0
-; CHECK-NO-STREAMING-NEXT: ret
-; NO-NEON-NO-GPRS-LABEL: t3:
-; NO-NEON-NO-GPRS: // %bb.0: // %entry
-; NO-NEON-NO-GPRS-NEXT: fcvtzs w8, h0
-; NO-NEON-NO-GPRS-NEXT: scvtf h0, w8
-; NO-NEON-NO-GPRS-NEXT: ret
-; USE-NEON-LABEL: t3:
-; USE-NEON: // %bb.0: // %entry
-; USE-NEON-NEXT: fcvtzs h0, h0
-; USE-NEON-NEXT: scvtf h0, h0
-; USE-NEON-NEXT: ret
+; NONEON-NOSVE-LABEL: t3:
+; NONEON-NOSVE: // %bb.0: // %entry
+; NONEON-NOSVE-NEXT: fcvt s0, h0
+; NONEON-NOSVE-NEXT: fcvtzs w8, s0
+; NONEON-NOSVE-NEXT: scvtf s0, w8
+; NONEON-NOSVE-NEXT: fcvt h0, s0
+; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptosi half %x to i32
%conv1 = sitofp i32 %conv to half
@@ -133,10 +132,19 @@ entry:
define double @t4(double %x) {
; CHECK-LABEL: t4:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu x8, d0
-; CHECK-NEXT: ucvtf d0, x8
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
+; CHECK-STREAMING-LABEL: t4:
+; CHECK-STREAMING: // %bb.0: // %entry
+; CHECK-STREAMING-NEXT: fcvtzu x8, d0
+; CHECK-STREAMING-NEXT: ucvtf d0, x8
+; CHECK-STREAMING-NEXT: ret
+;
; USE-NEON-NO-GPRS-LABEL: t4:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzu d0, d0
@@ -149,21 +157,11 @@ define double @t4(double %x) {
; NO-NEON-NEXT: ucvtf d0, x8
; NO-NEON-NEXT: ret
;
-; CHECK-NO-STREAMING-LABEL: t4:
-; CHECK-NO-STREAMING: // %bb.0: // %entry
-; CHECK-NO-STREAMING-NEXT: fcvtzu d0, d0
-; CHECK-NO-STREAMING-NEXT: ucvtf d0, d0
-; CHECK-NO-STREAMING-NEXT: ret
-; NO-NEON-NO-GPRS-LABEL: t4:
-; NO-NEON-NO-GPRS: // %bb.0: // %entry
-; NO-NEON-NO-GPRS-NEXT: fcvtzu x8, d0
-; NO-NEON-NO-GPRS-NEXT: ucvtf d0, x8
-; NO-NEON-NO-GPRS-NEXT: ret
-; USE-NEON-LABEL: t4:
-; USE-NEON: // %bb.0: // %entry
-; USE-NEON-NEXT: fcvtzu d0, d0
-; USE-NEON-NEXT: ucvtf d0, d0
-; USE-NEON-NEXT: ret
+; NONEON-NOSVE-LABEL: t4:
+; NONEON-NOSVE: // %bb.0: // %entry
+; NONEON-NOSVE-NEXT: fcvtzu x8, d0
+; NONEON-NOSVE-NEXT: ucvtf d0, x8
+; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptoui double %x to i64
%conv1 = uitofp i64 %conv to double
@@ -173,10 +171,19 @@ entry:
define float @t5(float %x) {
; CHECK-LABEL: t5:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu w8, s0
-; CHECK-NEXT: ucvtf s0, w8
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s
+; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0
; CHECK-NEXT: ret
;
+; CHECK-STREAMING-LABEL: t5:
+; CHECK-STREAMING: // %bb.0: // %entry
+; CHECK-STREAMING-NEXT: fcvtzu w8, s0
+; CHECK-STREAMING-NEXT: ucvtf s0, w8
+; CHECK-STREAMING-NEXT: ret
+;
; USE-NEON-NO-GPRS-LABEL: t5:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzu s0, s0
@@ -189,21 +196,11 @@ define float @t5(float %x) {
; NO-NEON-NEXT: ucvtf s0, w8
; NO-NEON-NEXT: ret
;
-; CHECK-NO-STREAMING-LABEL: t5:
-; CHECK-NO-STREAMING: // %bb.0: // %entry
-; CHECK-NO-STREAMING-NEXT: fcvtzu s0, s0
-; CHECK-NO-STREAMING-NEXT: ucvtf s0, s0
-; CHECK-NO-STREAMING-NEXT: ret
-; NO-NEON-NO-GPRS-LABEL: t5:
-; NO-NEON-NO-GPRS: // %bb.0: // %entry
-; NO-NEON-NO-GPRS-NEXT: fcvtzu w8, s0
-; NO-NEON-NO-GPRS-NEXT: ucvtf s0, w8
-; NO-NEON-NO-GPRS-NEXT: ret
-; USE-NEON-LABEL: t5:
-; USE-NEON: // %bb.0: // %entry
-; USE-NEON-NEXT: fcvtzu s0, s0
-; USE-NEON-NEXT: ucvtf s0, s0
-; USE-NEON-NEXT: ret
+; NONEON-NOSVE-LABEL: t5:
+; NONEON-NOSVE: // %bb.0: // %entry
+; NONEON-NOSVE-NEXT: fcvtzu w8, s0
+; NONEON-NOSVE-NEXT: ucvtf s0, w8
+; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptoui float %x to i32
%conv1 = uitofp i32 %conv to float
@@ -213,12 +210,21 @@ entry:
define half @t6(half %x) {
; CHECK-LABEL: t6:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvtzu w8, s0
-; CHECK-NEXT: ucvtf s0, w8
-; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
+; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
; CHECK-NEXT: ret
;
+; CHECK-STREAMING-LABEL: t6:
+; CHECK-STREAMING: // %bb.0: // %entry
+; CHECK-STREAMING-NEXT: fcvt s0, h0
+; CHECK-STREAMING-NEXT: fcvtzu w8, s0
+; CHECK-STREAMING-NEXT: ucvtf s0, w8
+; CHECK-STREAMING-NEXT: fcvt h0, s0
+; CHECK-STREAMING-NEXT: ret
+;
; USE-NEON-NO-GPRS-LABEL: t6:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzu h0, h0
@@ -231,23 +237,13 @@ define half @t6(half %x) {
; NO-NEON-NEXT: ucvtf h0, w8
; NO-NEON-NEXT: ret
;
-; CHECK-NO-STREAMING-LABEL: t6:
-; CHECK-NO-STREAMING: // %bb.0: // %entry
-; CHECK-NO-STREAMING-NEXT: fcvt s0, h0
-; CHECK-NO-STREAMING-NEXT: fcvtzu s0, s0
-; CHECK-NO-STREAMING-NEXT: ucvtf s0, s0
-; CHECK-NO-STREAMING-NEXT: fcvt h0, s0
-; CHECK-NO-STREAMING-NEXT: ret
-; NO-NEON-NO-GPRS-LABEL: t6:
-; NO-NEON-NO-GPRS: // %bb.0: // %entry
-; NO-NEON-NO-GPRS-NEXT: fcvtzu w8, h0
-; NO-NEON-NO-GPRS-NEXT: ucvtf h0, w8
-; NO-NEON-NO-GPRS-NEXT: ret
-; USE-NEON-LABEL: t6:
-; USE-NEON: // %bb.0: // %entry
-; USE-NEON-NEXT: fcvtzu h0, h0
-; USE-NEON-NEXT: ucvtf h0, h0
-; USE-NEON-NEXT: ret
+; NONEON-NOSVE-LABEL: t6:
+; NONEON-NOSVE: // %bb.0: // %entry
+; NONEON-NOSVE-NEXT: fcvt s0, h0
+; NONEON-NOSVE-NEXT: fcvtzu w8, s0
+; NONEON-NOSVE-NEXT: ucvtf s0, w8
+; NONEON-NOSVE-NEXT: fcvt h0, s0
+; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptoui half %x to i32
%conv1 = uitofp i32 %conv to half
>From 0d83e412f336b081a00ab078ae2eb1d4b63dfc2b Mon Sep 17 00:00:00 2001
From: Amichaxx <amina.chabane at arm.com>
Date: Thu, 27 Nov 2025 10:30:23 +0000
Subject: [PATCH 3/4] Formatting
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0fa5ca8e21b9c..318be91ca1972 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -330,7 +330,7 @@ def HasNEONandIsStreamingSafe
AssemblerPredicateWithAll<(any_of FeatureNEON), "neon">;
// A subset of NEON instructions are legal in Streaming SVE mode only with +sme2p2.
def HasNEONandFPRCVTIsStreamingSafe
- : Predicate<"Subtarget->isNeonAvailable() || (Subtarget->hasNEON() && Subtarget->isFPRCVTStreamingSafe())">,
+ : Predicate<"Subtarget->isNeonAvailable() || (Subtarget->hasNEON() && Subtarget->isFPRCVTStreamingSafe())">,
AssemblerPredicateWithAll<(any_of FeatureNEON), "neon">;
def HasRCPC : Predicate<"Subtarget->hasRCPC()">,
AssemblerPredicateWithAll<(all_of FeatureRCPC), "rcpc">;
>From 0398feb8b636b8d9a4deababbd79fa54f2fdcb9c Mon Sep 17 00:00:00 2001
From: Amichaxx <amina.chabane at arm.com>
Date: Fri, 5 Dec 2025 15:33:45 +0000
Subject: [PATCH 4/4] Included further fp to int/int to fp patterns and updated
relevant tests. Removed predicate in AArch64Subtarget.h.
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 38 +-
llvm/lib/Target/AArch64/AArch64Subtarget.h | 5 -
.../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 541 +-----------------
.../AArch64/arm64-cvt-simd-intrinsics.ll | 2 +-
.../sve-streaming-mode-cvt-fp-int-fp.ll | 190 +++---
5 files changed, 98 insertions(+), 678 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 318be91ca1972..5e0a8be790da3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -330,7 +330,7 @@ def HasNEONandIsStreamingSafe
AssemblerPredicateWithAll<(any_of FeatureNEON), "neon">;
// A subset of NEON instructions are legal in Streaming SVE mode only with +sme2p2.
def HasNEONandFPRCVTIsStreamingSafe
- : Predicate<"Subtarget->isNeonAvailable() || (Subtarget->hasNEON() && Subtarget->isFPRCVTStreamingSafe())">,
+ : Predicate<"Subtarget->isNeonAvailable() || (Subtarget->hasNEON() && Subtarget->hasFPRCVT())">,
AssemblerPredicateWithAll<(any_of FeatureNEON), "neon">;
def HasRCPC : Predicate<"Subtarget->hasRCPC()">,
AssemblerPredicateWithAll<(all_of FeatureRCPC), "rcpc">;
@@ -6547,7 +6547,7 @@ defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
// Floating-point conversion patterns.
multiclass FPToIntegerSIMDScalarPatterns<SDPatternOperator OpN, string INST> {
- let Predicates = [HasFPRCVT] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe] in {
def : Pat<(f32 (bitconvert (i32 (OpN (f64 FPR64:$Rn))))),
(!cast<Instruction>(INST # SDr) FPR64:$Rn)>;
def : Pat<(f32 (bitconvert (i32 (OpN (f16 FPR16:$Rn))))),
@@ -6575,7 +6575,7 @@ defm: FPToIntegerSIMDScalarPatterns<any_fp_to_sint, "FCVTZS">;
defm: FPToIntegerSIMDScalarPatterns<any_fp_to_uint, "FCVTZU">;
multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
- let Predicates = [HasFullFP16] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>;
def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>;
}
@@ -6586,7 +6586,7 @@ multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
// For global-isel we can use register classes to determine
// which FCVT instruction to use.
- let Predicates = [HasFPRCVT] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe] in {
def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # SHr) $Rn)>;
def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # DHr) $Rn)>;
def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # DSr) $Rn)>;
@@ -6595,7 +6595,7 @@ multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # v1i32) $Rn)>;
def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # v1i64) $Rn)>;
- let Predicates = [HasFPRCVT] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe] in {
def : Pat<(f32 (bitconvert (i32 (round f16:$Rn)))),
(!cast<Instruction>(INST # SHr) $Rn)>;
def : Pat<(f64 (bitconvert (i64 (round f16:$Rn)))),
@@ -6610,7 +6610,7 @@ multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
def : Pat<(f64 (bitconvert (i64 (round f64:$Rn)))),
(!cast<Instruction>(INST # v1i64) $Rn)>;
- let Predicates = [HasFullFP16] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),
(!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),
@@ -6631,7 +6631,7 @@ defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">;
// AArch64's FCVT instructions saturate when out of range.
multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string INST> {
- let Predicates = [HasFullFP16] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : Pat<(i32 (to_int_sat f16:$Rn, i32)),
(!cast<Instruction>(INST # UWHr) f16:$Rn)>;
def : Pat<(i64 (to_int_sat f16:$Rn, i64)),
@@ -6646,7 +6646,7 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string IN
def : Pat<(i64 (to_int_sat f64:$Rn, i64)),
(!cast<Instruction>(INST # UXDr) f64:$Rn)>;
- let Predicates = [HasFullFP16] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : Pat<(i32 (to_int_sat_gi f16:$Rn)),
(!cast<Instruction>(INST # UWHr) f16:$Rn)>;
def : Pat<(i64 (to_int_sat_gi f16:$Rn)),
@@ -6663,7 +6663,7 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string IN
// For global-isel we can use register classes to determine
// which FCVT instruction to use.
- let Predicates = [HasFPRCVT] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe] in {
def : Pat<(i32 (to_int_sat_gi f16:$Rn)),
(!cast<Instruction>(INST # SHr) f16:$Rn)>;
def : Pat<(i64 (to_int_sat_gi f16:$Rn)),
@@ -6678,7 +6678,7 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string IN
def : Pat<(i64 (to_int_sat_gi f64:$Rn)),
(!cast<Instruction>(INST # v1i64) f64:$Rn)>;
- let Predicates = [HasFPRCVT] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe] in {
def : Pat<(f32 (bitconvert (i32 (to_int_sat f16:$Rn, i32)))),
(!cast<Instruction>(INST # SHr) f16:$Rn)>;
def : Pat<(f64 (bitconvert (i64 (to_int_sat f16:$Rn, i64)))),
@@ -6693,7 +6693,7 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string IN
def : Pat<(f64 (bitconvert (i64 (to_int_sat f64:$Rn, i64)))),
(!cast<Instruction>(INST # v1i64) f64:$Rn)>;
- let Predicates = [HasFullFP16] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : Pat<(i32 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i32:$scale), i32)),
(!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
def : Pat<(i64 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i64:$scale), i64)),
@@ -6708,7 +6708,7 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string IN
def : Pat<(i64 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i64:$scale), i64)),
(!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
- let Predicates = [HasFullFP16] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : Pat<(i32 (to_int_sat_gi (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),
(!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
def : Pat<(i64 (to_int_sat_gi (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),
@@ -6739,7 +6739,7 @@ multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode to_int_sat_g
// For global-isel we can use register classes to determine
// which FCVT instruction to use.
- let Predicates = [HasFPRCVT] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe] in {
def : Pat<(i64 (to_int (round f32:$Rn))),
(!cast<Instruction>(INST # DSr) f32:$Rn)>;
def : Pat<(i32 (to_int (round f64:$Rn))),
@@ -6750,7 +6750,7 @@ multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode to_int_sat_g
def : Pat<(i64 (to_int (round f64:$Rn))),
(!cast<Instruction>(INST # v1i64) f64:$Rn)>;
- let Predicates = [HasFPRCVT] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe] in {
def : Pat<(f64 (bitconvert (i64 (to_int (round f32:$Rn))))),
(!cast<Instruction>(INST # DSr) f32:$Rn)>;
def : Pat<(f32 (bitconvert (i32 (to_int (round f64:$Rn))))),
@@ -6762,7 +6762,7 @@ multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode to_int_sat_g
(!cast<Instruction>(INST # v1i64) f64:$Rn)>;
// These instructions saturate like fp_to_[su]int_sat.
- let Predicates = [HasFullFP16] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : Pat<(i32 (to_int_sat (round f16:$Rn), i32)),
(!cast<Instruction>(INST # UWHr) f16:$Rn)>;
def : Pat<(i64 (to_int_sat (round f16:$Rn), i64)),
@@ -6779,7 +6779,7 @@ multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode to_int_sat_g
// For global-isel we can use register classes to determine
// which FCVT instruction to use.
- let Predicates = [HasFPRCVT] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe] in {
def : Pat<(i32 (to_int_sat_gi (round f16:$Rn))),
(!cast<Instruction>(INST # SHr) f16:$Rn)>;
def : Pat<(i64 (to_int_sat_gi (round f16:$Rn))),
@@ -6794,7 +6794,7 @@ multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode to_int_sat_g
def : Pat<(i64 (to_int_sat_gi (round f64:$Rn))),
(!cast<Instruction>(INST # v1i64) f64:$Rn)>;
- let Predicates = [HasFPRCVT] in {
+ let Predicates = [HasNEONandFPRCVTIsStreamingSafe] in {
def : Pat<(f32 (bitconvert (i32 (to_int_sat (round f16:$Rn), i32)))),
(!cast<Instruction>(INST # SHr) f16:$Rn)>;
def : Pat<(f64 (bitconvert (i64 (to_int_sat (round f16:$Rn), i64)))),
@@ -6820,7 +6820,7 @@ defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, fround, "F
defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, fround, "FCVTAU">;
// f16 -> s16 conversions
-let Predicates = [HasFullFP16] in {
+let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : Pat<(i16(fp_to_sint_sat_gi f16:$Rn)), (FCVTZSv1f16 f16:$Rn)>;
def : Pat<(i16(fp_to_uint_sat_gi f16:$Rn)), (FCVTZUv1f16 f16:$Rn)>;
}
@@ -6833,7 +6833,7 @@ class F16ToI16ScalarPat<SDNode cvt_isd, BaseSIMDTwoScalar instr>
: Pat<(f32 (cvt_isd (f16 FPR16:$Rn))),
(f32 (SUBREG_TO_REG (i64 0), (instr FPR16:$Rn), hsub))>;
-let Predicates = [HasFullFP16] in {
+let Predicates = [HasNEONandFPRCVTIsStreamingSafe, HasFullFP16] in {
def : F16ToI16ScalarPat<AArch64fcvtzs_half, FCVTZSv1f16>;
def : F16ToI16ScalarPat<AArch64fcvtzu_half, FCVTZUv1f16>;
def : F16ToI16ScalarPat<AArch64fcvtas_half, FCVTASv1f16>;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 8d20498b4c68e..8974965c41fe3 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -217,11 +217,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
return isSVEAvailable() || (isSVEorStreamingSVEAvailable() && hasSME2());
}
- bool isFPRCVTStreamingSafe() const {
- return hasFPRCVT() &&
- (!hasSMEFA64() && (isStreaming() || isStreamingCompatible()));
- }
-
unsigned getMinVectorRegisterBitWidth() const {
// Don't assume any minimum vector size when PSTATE.SM may not be 0, because
// we don't yet support streaming-compatible codegen support that we trust
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
index a729772f2897a..b7ca90aeb6c97 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFPRCVT
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 --force-streaming-compatible | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK
; CHECK-GI: warning: Instruction selection used fallback path for fptosi_i32_f16_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f16_simd
@@ -21,11 +20,6 @@
;
define float @test_fptosi_f16_i32_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptosi_f16_i32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptosi_f16_i32_simd:
; CHECK: // %bb.0:
@@ -37,11 +31,6 @@ define float @test_fptosi_f16_i32_simd(half %a) {
}
define double @test_fptosi_f16_i64_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptosi_f16_i64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptosi_f16_i64_simd:
; CHECK: // %bb.0:
@@ -53,11 +42,6 @@ define double @test_fptosi_f16_i64_simd(half %a) {
}
define float @test_fptosi_f64_i32_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptosi_f64_i32_simd:
; CHECK: // %bb.0:
@@ -69,11 +53,6 @@ define float @test_fptosi_f64_i32_simd(double %a) {
}
define double @test_fptosi_f32_i64_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptosi_f32_i64_simd:
; CHECK: // %bb.0:
@@ -85,10 +64,6 @@ define double @test_fptosi_f32_i64_simd(float %a) {
}
define double @test_fptosi_f64_i64_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptosi_f64_i64_simd:
; CHECK: // %bb.0:
@@ -101,10 +76,6 @@ define double @test_fptosi_f64_i64_simd(double %a) {
define float @test_fptosi_f32_i32_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptosi_f32_i32_simd:
; CHECK: // %bb.0:
@@ -116,11 +87,6 @@ define float @test_fptosi_f32_i32_simd(float %a) {
}
define float @test_fptoui_f16_i32_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptoui_f16_i32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptoui_f16_i32_simd:
; CHECK: // %bb.0:
@@ -132,11 +98,6 @@ define float @test_fptoui_f16_i32_simd(half %a) {
}
define double @test_fptoui_f16_i64_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptoui_f16_i64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptoui_f16_i64_simd:
; CHECK: // %bb.0:
@@ -148,11 +109,6 @@ define double @test_fptoui_f16_i64_simd(half %a) {
}
define float @test_fptoui_f64_i32_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptoui_f64_i32_simd:
; CHECK: // %bb.0:
@@ -164,11 +120,6 @@ define float @test_fptoui_f64_i32_simd(double %a) {
}
define double @test_fptoui_f32_i64_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptoui_f32_i64_simd:
; CHECK: // %bb.0:
@@ -180,10 +131,6 @@ define double @test_fptoui_f32_i64_simd(float %a) {
}
define double @test_fptoui_f64_i64_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptoui_f64_i64_simd:
; CHECK: // %bb.0:
@@ -196,10 +143,6 @@ define double @test_fptoui_f64_i64_simd(double %a) {
define float @test_fptoui_f32_i32_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: test_fptoui_f32_i32_simd:
; CHECK: // %bb.0:
@@ -216,11 +159,6 @@ define float @test_fptoui_f32_i32_simd(float %a) {
;
define float @fptosi_i32_f16_simd(half %x) {
-; CHECK-NOFPRCVT-LABEL: fptosi_i32_f16_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i32_f16_simd:
; CHECK: // %bb.0:
@@ -232,11 +170,6 @@ define float @fptosi_i32_f16_simd(half %x) {
}
define double @fptosi_i64_f16_simd(half %x) {
-; CHECK-NOFPRCVT-LABEL: fptosi_i64_f16_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i64_f16_simd:
; CHECK: // %bb.0:
@@ -248,11 +181,6 @@ define double @fptosi_i64_f16_simd(half %x) {
}
define double @fptosi_i64_f32_simd(float %x) {
-; CHECK-NOFPRCVT-LABEL: fptosi_i64_f32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i64_f32_simd:
; CHECK: // %bb.0:
@@ -264,11 +192,6 @@ define double @fptosi_i64_f32_simd(float %x) {
}
define float @fptosi_i32_f64_simd(double %x) {
-; CHECK-NOFPRCVT-LABEL: fptosi_i32_f64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i32_f64_simd:
; CHECK: // %bb.0:
@@ -280,10 +203,6 @@ define float @fptosi_i32_f64_simd(double %x) {
}
define double @fptosi_i64_f64_simd(double %x) {
-; CHECK-NOFPRCVT-LABEL: fptosi_i64_f64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i64_f64_simd:
; CHECK: // %bb.0:
@@ -295,10 +214,6 @@ define double @fptosi_i64_f64_simd(double %x) {
}
define float @fptosi_i32_f32_simd(float %x) {
-; CHECK-NOFPRCVT-LABEL: fptosi_i32_f32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptosi_i32_f32_simd:
; CHECK: // %bb.0:
@@ -312,11 +227,6 @@ define float @fptosi_i32_f32_simd(float %x) {
define float @fptoui_i32_f16_simd(half %x) {
-; CHECK-NOFPRCVT-LABEL: fptoui_i32_f16_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i32_f16_simd:
; CHECK: // %bb.0:
@@ -328,11 +238,6 @@ define float @fptoui_i32_f16_simd(half %x) {
}
define double @fptoui_i64_f16_simd(half %x) {
-; CHECK-NOFPRCVT-LABEL: fptoui_i64_f16_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i64_f16_simd:
; CHECK: // %bb.0:
@@ -344,11 +249,6 @@ define double @fptoui_i64_f16_simd(half %x) {
}
define double @fptoui_i64_f32_simd(float %x) {
-; CHECK-NOFPRCVT-LABEL: fptoui_i64_f32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i64_f32_simd:
; CHECK: // %bb.0:
@@ -360,11 +260,6 @@ define double @fptoui_i64_f32_simd(float %x) {
}
define float @fptoui_i32_f64_simd(double %x) {
-; CHECK-NOFPRCVT-LABEL: fptoui_i32_f64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i32_f64_simd:
; CHECK: // %bb.0:
@@ -376,10 +271,6 @@ define float @fptoui_i32_f64_simd(double %x) {
}
define double @fptoui_i64_f64_simd(double %x) {
-; CHECK-NOFPRCVT-LABEL: fptoui_i64_f64_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i64_f64_simd:
; CHECK: // %bb.0:
@@ -391,10 +282,6 @@ define double @fptoui_i64_f64_simd(double %x) {
}
define float @fptoui_i32_f32_simd(float %x) {
-; CHECK-NOFPRCVT-LABEL: fptoui_i32_f32_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fptoui_i32_f32_simd:
; CHECK: // %bb.0:
@@ -411,11 +298,6 @@ define float @fptoui_i32_f32_simd(float %x) {
define double @fcvtas_ds_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_ds_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtas_ds_round_simd:
; CHECK: // %bb.0:
@@ -428,11 +310,6 @@ define double @fcvtas_ds_round_simd(float %a) {
}
define float @fcvtas_sd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_sd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtas_sd_round_simd:
; CHECK: // %bb.0:
@@ -445,10 +322,6 @@ define float @fcvtas_sd_round_simd(double %a) {
}
define float @fcvtas_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtas_ss_round_simd:
; CHECK: // %bb.0:
@@ -461,10 +334,6 @@ define float @fcvtas_ss_round_simd(float %a) {
}
define double @fcvtas_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtas_dd_round_simd:
; CHECK: // %bb.0:
@@ -478,11 +347,6 @@ define double @fcvtas_dd_round_simd(double %a) {
define double @fcvtau_ds_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_ds_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtau x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtau_ds_round_simd:
; CHECK: // %bb.0:
@@ -495,11 +359,6 @@ define double @fcvtau_ds_round_simd(float %a) {
}
define float @fcvtau_sd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_sd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtau w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtau_sd_round_simd:
; CHECK: // %bb.0:
@@ -512,10 +371,6 @@ define float @fcvtau_sd_round_simd(double %a) {
}
define float @fcvtau_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtau_ss_round_simd:
; CHECK: // %bb.0:
@@ -528,10 +383,6 @@ define float @fcvtau_ss_round_simd(float %a) {
}
define double @fcvtau_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtau_dd_round_simd:
; CHECK: // %bb.0:
@@ -545,11 +396,6 @@ define double @fcvtau_dd_round_simd(double %a) {
define double @fcvtms_ds_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_ds_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtms_ds_round_simd:
; CHECK: // %bb.0:
@@ -562,11 +408,6 @@ define double @fcvtms_ds_round_simd(float %a) {
}
define float @fcvtms_sd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_sd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtms_sd_round_simd:
; CHECK: // %bb.0:
@@ -579,10 +420,6 @@ define float @fcvtms_sd_round_simd(double %a) {
}
define float @fcvtms_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtms_ss_round_simd:
; CHECK: // %bb.0:
@@ -595,10 +432,6 @@ define float @fcvtms_ss_round_simd(float %a) {
}
define double @fcvtms_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtms_dd_round_simd:
; CHECK: // %bb.0:
@@ -613,11 +446,6 @@ define double @fcvtms_dd_round_simd(double %a) {
define double @fcvtmu_ds_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_ds_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtmu x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtmu_ds_round_simd:
; CHECK: // %bb.0:
@@ -630,11 +458,6 @@ define double @fcvtmu_ds_round_simd(float %a) {
}
define float @fcvtmu_sd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_sd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtmu w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtmu_sd_round_simd:
; CHECK: // %bb.0:
@@ -647,10 +470,6 @@ define float @fcvtmu_sd_round_simd(double %a) {
}
define float @fcvtmu_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtmu_ss_round_simd:
; CHECK: // %bb.0:
@@ -663,10 +482,6 @@ define float @fcvtmu_ss_round_simd(float %a) {
}
define double @fcvtmu_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtmu_dd_round_simd:
; CHECK: // %bb.0:
@@ -680,11 +495,6 @@ define double @fcvtmu_dd_round_simd(double %a) {
define double @fcvtps_ds_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_ds_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtps_ds_round_simd:
; CHECK: // %bb.0:
@@ -697,11 +507,6 @@ define double @fcvtps_ds_round_simd(float %a) {
}
define float @fcvtps_sd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_sd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtps_sd_round_simd:
; CHECK: // %bb.0:
@@ -714,10 +519,6 @@ define float @fcvtps_sd_round_simd(double %a) {
}
define float @fcvtps_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtps_ss_round_simd:
; CHECK: // %bb.0:
@@ -730,10 +531,6 @@ define float @fcvtps_ss_round_simd(float %a) {
}
define double @fcvtps_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtps_dd_round_simd:
; CHECK: // %bb.0:
@@ -747,11 +544,6 @@ define double @fcvtps_dd_round_simd(double %a) {
define double @fcvtpu_ds_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_ds_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtpu x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtpu_ds_round_simd:
; CHECK: // %bb.0:
@@ -764,11 +556,6 @@ define double @fcvtpu_ds_round_simd(float %a) {
}
define float @fcvtpu_sd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_sd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtpu w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtpu_sd_round_simd:
; CHECK: // %bb.0:
@@ -781,10 +568,6 @@ define float @fcvtpu_sd_round_simd(double %a) {
}
define float @fcvtpu_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtpu_ss_round_simd:
; CHECK: // %bb.0:
@@ -797,10 +580,6 @@ define float @fcvtpu_ss_round_simd(float %a) {
}
define double @fcvtpu_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtpu_dd_round_simd:
; CHECK: // %bb.0:
@@ -814,11 +593,6 @@ define double @fcvtpu_dd_round_simd(double %a) {
define double @fcvtzs_ds_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_ds_round_simd:
; CHECK: // %bb.0:
@@ -831,11 +605,6 @@ define double @fcvtzs_ds_round_simd(float %a) {
}
define float @fcvtzs_sd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_sd_round_simd:
; CHECK: // %bb.0:
@@ -848,10 +617,6 @@ define float @fcvtzs_sd_round_simd(double %a) {
}
define float @fcvtzs_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_ss_round_simd:
; CHECK: // %bb.0:
@@ -864,10 +629,6 @@ define float @fcvtzs_ss_round_simd(float %a) {
}
define double @fcvtzs_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_dd_round_simd:
; CHECK: // %bb.0:
@@ -880,11 +641,6 @@ define double @fcvtzs_dd_round_simd(double %a) {
}
define double @fcvtzu_ds_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_ds_round_simd:
; CHECK: // %bb.0:
@@ -897,11 +653,6 @@ define double @fcvtzu_ds_round_simd(float %a) {
}
define float @fcvtzu_sd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_sd_round_simd:
; CHECK: // %bb.0:
@@ -914,10 +665,6 @@ define float @fcvtzu_sd_round_simd(double %a) {
}
define float @fcvtzu_ss_round_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_ss_round_simd:
; CHECK: // %bb.0:
@@ -930,10 +677,6 @@ define float @fcvtzu_ss_round_simd(float %a) {
}
define double @fcvtzu_dd_round_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_round_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_dd_round_simd:
; CHECK: // %bb.0:
@@ -951,11 +694,6 @@ define double @fcvtzu_dd_round_simd(double %a) {
;
define float @fcvtzs_sh_sat_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_sh_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_sh_sat_simd:
; CHECK: // %bb.0:
@@ -967,11 +705,6 @@ define float @fcvtzs_sh_sat_simd(half %a) {
}
define double @fcvtzs_dh_sat_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dh_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_dh_sat_simd:
; CHECK: // %bb.0:
@@ -983,11 +716,6 @@ define double @fcvtzs_dh_sat_simd(half %a) {
}
define double @fcvtzs_ds_sat_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_ds_sat_simd:
; CHECK: // %bb.0:
@@ -999,11 +727,6 @@ define double @fcvtzs_ds_sat_simd(float %a) {
}
define float @fcvtzs_sd_sat_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_sd_sat_simd:
; CHECK: // %bb.0:
@@ -1015,10 +738,6 @@ define float @fcvtzs_sd_sat_simd(double %a) {
}
define float @fcvtzs_ss_sat_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_ss_sat_simd:
; CHECK: // %bb.0:
@@ -1030,10 +749,6 @@ define float @fcvtzs_ss_sat_simd(float %a) {
}
define double @fcvtzs_dd_sat_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_dd_sat_simd:
; CHECK: // %bb.0:
@@ -1045,11 +760,6 @@ define double @fcvtzs_dd_sat_simd(double %a) {
}
define float @fcvtzu_sh_sat_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_sh_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_sh_sat_simd:
; CHECK: // %bb.0:
@@ -1061,11 +771,6 @@ define float @fcvtzu_sh_sat_simd(half %a) {
}
define double @fcvtzu_dh_sat_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dh_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_dh_sat_simd:
; CHECK: // %bb.0:
@@ -1077,11 +782,6 @@ define double @fcvtzu_dh_sat_simd(half %a) {
}
define double @fcvtzu_ds_sat_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_ds_sat_simd:
; CHECK: // %bb.0:
@@ -1093,11 +793,6 @@ define double @fcvtzu_ds_sat_simd(float %a) {
}
define float @fcvtzu_sd_sat_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_sd_sat_simd:
; CHECK: // %bb.0:
@@ -1109,10 +804,6 @@ define float @fcvtzu_sd_sat_simd(double %a) {
}
define float @fcvtzu_ss_sat_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_ss_sat_simd:
; CHECK: // %bb.0:
@@ -1124,10 +815,6 @@ define float @fcvtzu_ss_sat_simd(float %a) {
}
define double @fcvtzu_dd_sat_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_sat_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_dd_sat_simd:
; CHECK: // %bb.0:
@@ -1143,11 +830,6 @@ define double @fcvtzu_dd_sat_simd(double %a) {
;
define float @fcvtas_sh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_sh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtas_sh_simd:
; CHECK: // %bb.0:
@@ -1160,11 +842,6 @@ define float @fcvtas_sh_simd(half %a) {
}
define double @fcvtas_dh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_dh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtas_dh_simd:
; CHECK: // %bb.0:
@@ -1177,11 +854,6 @@ define double @fcvtas_dh_simd(half %a) {
}
define double @fcvtas_ds_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_ds_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtas_ds_simd:
; CHECK: // %bb.0:
@@ -1194,11 +866,6 @@ define double @fcvtas_ds_simd(float %a) {
}
define float @fcvtas_sd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_sd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtas_sd_simd:
; CHECK: // %bb.0:
@@ -1211,10 +878,6 @@ define float @fcvtas_sd_simd(double %a) {
}
define float @fcvtas_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtas_ss_simd:
; CHECK: // %bb.0:
@@ -1227,10 +890,6 @@ define float @fcvtas_ss_simd(float %a) {
}
define double @fcvtas_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtas_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtas_dd_simd:
; CHECK: // %bb.0:
@@ -1243,11 +902,6 @@ define double @fcvtas_dd_simd(double %a) {
}
define float @fcvtau_sh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_sh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtau w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtau_sh_simd:
; CHECK: // %bb.0:
@@ -1260,11 +914,6 @@ define float @fcvtau_sh_simd(half %a) {
}
define double @fcvtau_dh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_dh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtau x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtau_dh_simd:
; CHECK: // %bb.0:
@@ -1277,11 +926,6 @@ define double @fcvtau_dh_simd(half %a) {
}
define double @fcvtau_ds_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_ds_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtau x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtau_ds_simd:
; CHECK: // %bb.0:
@@ -1294,11 +938,6 @@ define double @fcvtau_ds_simd(float %a) {
}
define float @fcvtau_sd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_sd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtau w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtau_sd_simd:
; CHECK: // %bb.0:
@@ -1311,10 +950,6 @@ define float @fcvtau_sd_simd(double %a) {
}
define float @fcvtau_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtau_ss_simd:
; CHECK: // %bb.0:
@@ -1327,10 +962,6 @@ define float @fcvtau_ss_simd(float %a) {
}
define double @fcvtau_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtau_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtas d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtau_dd_simd:
; CHECK: // %bb.0:
@@ -1343,11 +974,6 @@ define double @fcvtau_dd_simd(double %a) {
}
define float @fcvtms_sh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_sh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtms_sh_simd:
; CHECK: // %bb.0:
@@ -1360,11 +986,6 @@ define float @fcvtms_sh_simd(half %a) {
}
define double @fcvtms_dh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_dh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtms_dh_simd:
; CHECK: // %bb.0:
@@ -1377,11 +998,6 @@ define double @fcvtms_dh_simd(half %a) {
}
define double @fcvtms_ds_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_ds_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtms_ds_simd:
; CHECK: // %bb.0:
@@ -1394,11 +1010,6 @@ define double @fcvtms_ds_simd(float %a) {
}
define float @fcvtms_sd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_sd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtms_sd_simd:
; CHECK: // %bb.0:
@@ -1411,10 +1022,6 @@ define float @fcvtms_sd_simd(double %a) {
}
define float @fcvtms_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtms_ss_simd:
; CHECK: // %bb.0:
@@ -1427,10 +1034,6 @@ define float @fcvtms_ss_simd(float %a) {
}
define double @fcvtms_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtms_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtms_dd_simd:
; CHECK: // %bb.0:
@@ -1443,11 +1046,6 @@ define double @fcvtms_dd_simd(double %a) {
}
define float @fcvtmu_sh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_sh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtmu w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtmu_sh_simd:
; CHECK: // %bb.0:
@@ -1460,11 +1058,6 @@ define float @fcvtmu_sh_simd(half %a) {
}
define double @fcvtmu_dh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_dh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtmu x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtmu_dh_simd:
; CHECK: // %bb.0:
@@ -1477,11 +1070,6 @@ define double @fcvtmu_dh_simd(half %a) {
}
define double @fcvtmu_ds_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_ds_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtmu x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtmu_ds_simd:
; CHECK: // %bb.0:
@@ -1494,11 +1082,6 @@ define double @fcvtmu_ds_simd(float %a) {
}
define float @fcvtmu_sd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_sd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtmu w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtmu_sd_simd:
; CHECK: // %bb.0:
@@ -1511,10 +1094,6 @@ define float @fcvtmu_sd_simd(double %a) {
}
define float @fcvtmu_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtmu_ss_simd:
; CHECK: // %bb.0:
@@ -1527,10 +1106,6 @@ define float @fcvtmu_ss_simd(float %a) {
}
define double @fcvtmu_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtms d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtmu_dd_simd:
; CHECK: // %bb.0:
@@ -1543,11 +1118,6 @@ define double @fcvtmu_dd_simd(double %a) {
}
define float @fcvtps_sh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_sh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtps_sh_simd:
; CHECK: // %bb.0:
@@ -1560,11 +1130,6 @@ define float @fcvtps_sh_simd(half %a) {
}
define double @fcvtps_dh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_dh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtps_dh_simd:
; CHECK: // %bb.0:
@@ -1577,11 +1142,6 @@ define double @fcvtps_dh_simd(half %a) {
}
define double @fcvtps_ds_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_ds_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtps_ds_simd:
; CHECK: // %bb.0:
@@ -1594,11 +1154,6 @@ define double @fcvtps_ds_simd(float %a) {
}
define float @fcvtps_sd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_sd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtps_sd_simd:
; CHECK: // %bb.0:
@@ -1611,10 +1166,6 @@ define float @fcvtps_sd_simd(double %a) {
}
define float @fcvtps_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtps_ss_simd:
; CHECK: // %bb.0:
@@ -1627,10 +1178,6 @@ define float @fcvtps_ss_simd(float %a) {
}
define double @fcvtps_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtps_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtps_dd_simd:
; CHECK: // %bb.0:
@@ -1643,11 +1190,6 @@ define double @fcvtps_dd_simd(double %a) {
}
define float @fcvtpu_sh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_sh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtpu w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtpu_sh_simd:
; CHECK: // %bb.0:
@@ -1660,11 +1202,6 @@ define float @fcvtpu_sh_simd(half %a) {
}
define double @fcvtpu_dh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_dh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtpu x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtpu_dh_simd:
; CHECK: // %bb.0:
@@ -1677,11 +1214,6 @@ define double @fcvtpu_dh_simd(half %a) {
}
define double @fcvtpu_ds_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_ds_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtpu x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtpu_ds_simd:
; CHECK: // %bb.0:
@@ -1694,11 +1226,6 @@ define double @fcvtpu_ds_simd(float %a) {
}
define float @fcvtpu_sd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_sd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtpu w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtpu_sd_simd:
; CHECK: // %bb.0:
@@ -1711,10 +1238,6 @@ define float @fcvtpu_sd_simd(double %a) {
}
define float @fcvtpu_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtpu_ss_simd:
; CHECK: // %bb.0:
@@ -1727,10 +1250,6 @@ define float @fcvtpu_ss_simd(float %a) {
}
define double @fcvtpu_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtps d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtpu_dd_simd:
; CHECK: // %bb.0:
@@ -1743,11 +1262,6 @@ define double @fcvtpu_dd_simd(double %a) {
}
define float @fcvtzs_sh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_sh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_sh_simd:
; CHECK: // %bb.0:
@@ -1760,11 +1274,6 @@ define float @fcvtzs_sh_simd(half %a) {
}
define double @fcvtzs_dh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_dh_simd:
; CHECK: // %bb.0:
@@ -1777,11 +1286,6 @@ define double @fcvtzs_dh_simd(half %a) {
}
define double @fcvtzs_ds_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_ds_simd:
; CHECK: // %bb.0:
@@ -1794,11 +1298,6 @@ define double @fcvtzs_ds_simd(float %a) {
}
define float @fcvtzs_sd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_sd_simd:
; CHECK: // %bb.0:
@@ -1811,10 +1310,6 @@ define float @fcvtzs_sd_simd(double %a) {
}
define float @fcvtzs_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_ss_simd:
; CHECK: // %bb.0:
@@ -1827,10 +1322,6 @@ define float @fcvtzs_ss_simd(float %a) {
}
define double @fcvtzs_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzs d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzs_dd_simd:
; CHECK: // %bb.0:
@@ -1843,11 +1334,6 @@ define double @fcvtzs_dd_simd(double %a) {
}
define float @fcvtzu_sh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_sh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu w8, h0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_sh_simd:
; CHECK: // %bb.0:
@@ -1860,11 +1346,6 @@ define float @fcvtzu_sh_simd(half %a) {
}
define double @fcvtzu_dh_simd(half %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dh_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu x8, h0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_dh_simd:
; CHECK: // %bb.0:
@@ -1877,11 +1358,6 @@ define double @fcvtzu_dh_simd(half %a) {
}
define double @fcvtzu_ds_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu x8, s0
-; CHECK-NOFPRCVT-NEXT: fmov d0, x8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_ds_simd:
; CHECK: // %bb.0:
@@ -1894,11 +1370,6 @@ define double @fcvtzu_ds_simd(float %a) {
}
define float @fcvtzu_sd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu w8, d0
-; CHECK-NOFPRCVT-NEXT: fmov s0, w8
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_sd_simd:
; CHECK: // %bb.0:
@@ -1911,10 +1382,6 @@ define float @fcvtzu_sd_simd(double %a) {
}
define float @fcvtzu_ss_simd(float %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu s0, s0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_ss_simd:
; CHECK: // %bb.0:
@@ -1927,10 +1394,6 @@ define float @fcvtzu_ss_simd(float %a) {
}
define double @fcvtzu_dd_simd(double %a) {
-; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_simd:
-; CHECK-NOFPRCVT: // %bb.0:
-; CHECK-NOFPRCVT-NEXT: fcvtzu d0, d0
-; CHECK-NOFPRCVT-NEXT: ret
;
; CHECK-LABEL: fcvtzu_dd_simd:
; CHECK: // %bb.0:
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll
index b1b9fcf8a8b3c..1e8135be4fa32 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 --force-streaming-compatible | FileCheck %s --check-prefixes=CHECK
; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
index bd4b1e3e7580f..2f70343954bb8 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
@@ -1,10 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s
-; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=CHECK-STREAMING
+; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=CHECK-STREAMING-COMPATIBLE
+; RUN: llc -mattr=+fprcvt < %s | FileCheck %s --check-prefix=CHECK-FPRCVT
; RUN: llc -force-streaming-compatible -mattr=+fprcvt,+fullfp16 < %s | FileCheck %s --check-prefix=USE-NEON-NO-GPRS
-; RUN: llc -force-streaming-compatible -mattr=+fprcvt,+fullfp16,-neon < %s | FileCheck %s --check-prefix=NO-NEON
-; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
target triple = "aarch64-unknown-linux-gnu"
@@ -18,29 +16,23 @@ define double @t1(double %x) {
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
-; CHECK-STREAMING-LABEL: t1:
-; CHECK-STREAMING: // %bb.0: // %entry
-; CHECK-STREAMING-NEXT: fcvtzs x8, d0
-; CHECK-STREAMING-NEXT: scvtf d0, x8
-; CHECK-STREAMING-NEXT: ret
+; CHECK-STREAMING-COMPATIBLE-LABEL: t1:
+; CHECK-STREAMING-COMPATIBLE: // %bb.0: // %entry
+; CHECK-STREAMING-COMPATIBLE-NEXT: fcvtzs x8, d0
+; CHECK-STREAMING-COMPATIBLE-NEXT: scvtf d0, x8
+; CHECK-STREAMING-COMPATIBLE-NEXT: ret
+;
+; CHECK-FPRCVT-LABEL: t1:
+; CHECK-FPRCVT: // %bb.0: // %entry
+; CHECK-FPRCVT-NEXT: fcvtzs d0, d0
+; CHECK-FPRCVT-NEXT: scvtf d0, d0
+; CHECK-FPRCVT-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t1:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzs d0, d0
; USE-NEON-NO-GPRS-NEXT: scvtf d0, d0
; USE-NEON-NO-GPRS-NEXT: ret
-;
-; NO-NEON-LABEL: t1:
-; NO-NEON: // %bb.0: // %entry
-; NO-NEON-NEXT: fcvtzs x8, d0
-; NO-NEON-NEXT: scvtf d0, x8
-; NO-NEON-NEXT: ret
-;
-; NONEON-NOSVE-LABEL: t1:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvtzs x8, d0
-; NONEON-NOSVE-NEXT: scvtf d0, x8
-; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptosi double %x to i64
%conv1 = sitofp i64 %conv to double
@@ -57,29 +49,23 @@ define float @t2(float %x) {
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0
; CHECK-NEXT: ret
;
-; CHECK-STREAMING-LABEL: t2:
-; CHECK-STREAMING: // %bb.0: // %entry
-; CHECK-STREAMING-NEXT: fcvtzs w8, s0
-; CHECK-STREAMING-NEXT: scvtf s0, w8
-; CHECK-STREAMING-NEXT: ret
+; CHECK-STREAMING-COMPATIBLE-LABEL: t2:
+; CHECK-STREAMING-COMPATIBLE: // %bb.0: // %entry
+; CHECK-STREAMING-COMPATIBLE-NEXT: fcvtzs w8, s0
+; CHECK-STREAMING-COMPATIBLE-NEXT: scvtf s0, w8
+; CHECK-STREAMING-COMPATIBLE-NEXT: ret
+;
+; CHECK-FPRCVT-LABEL: t2:
+; CHECK-FPRCVT: // %bb.0: // %entry
+; CHECK-FPRCVT-NEXT: fcvtzs s0, s0
+; CHECK-FPRCVT-NEXT: scvtf s0, s0
+; CHECK-FPRCVT-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t2:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzs s0, s0
; USE-NEON-NO-GPRS-NEXT: scvtf s0, s0
; USE-NEON-NO-GPRS-NEXT: ret
-;
-; NO-NEON-LABEL: t2:
-; NO-NEON: // %bb.0: // %entry
-; NO-NEON-NEXT: fcvtzs w8, s0
-; NO-NEON-NEXT: scvtf s0, w8
-; NO-NEON-NEXT: ret
-;
-; NONEON-NOSVE-LABEL: t2:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvtzs w8, s0
-; NONEON-NOSVE-NEXT: scvtf s0, w8
-; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptosi float %x to i32
%conv1 = sitofp i32 %conv to float
@@ -96,33 +82,27 @@ define half @t3(half %x) {
; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
; CHECK-NEXT: ret
;
-; CHECK-STREAMING-LABEL: t3:
-; CHECK-STREAMING: // %bb.0: // %entry
-; CHECK-STREAMING-NEXT: fcvt s0, h0
-; CHECK-STREAMING-NEXT: fcvtzs w8, s0
-; CHECK-STREAMING-NEXT: scvtf s0, w8
-; CHECK-STREAMING-NEXT: fcvt h0, s0
-; CHECK-STREAMING-NEXT: ret
+; CHECK-STREAMING-COMPATIBLE-LABEL: t3:
+; CHECK-STREAMING-COMPATIBLE: // %bb.0: // %entry
+; CHECK-STREAMING-COMPATIBLE-NEXT: fcvt s0, h0
+; CHECK-STREAMING-COMPATIBLE-NEXT: fcvtzs w8, s0
+; CHECK-STREAMING-COMPATIBLE-NEXT: scvtf s0, w8
+; CHECK-STREAMING-COMPATIBLE-NEXT: fcvt h0, s0
+; CHECK-STREAMING-COMPATIBLE-NEXT: ret
+;
+; CHECK-FPRCVT-LABEL: t3:
+; CHECK-FPRCVT: // %bb.0: // %entry
+; CHECK-FPRCVT-NEXT: fcvt s0, h0
+; CHECK-FPRCVT-NEXT: fcvtzs s0, s0
+; CHECK-FPRCVT-NEXT: scvtf s0, s0
+; CHECK-FPRCVT-NEXT: fcvt h0, s0
+; CHECK-FPRCVT-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t3:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzs h0, h0
; USE-NEON-NO-GPRS-NEXT: scvtf h0, h0
; USE-NEON-NO-GPRS-NEXT: ret
-;
-; NO-NEON-LABEL: t3:
-; NO-NEON: // %bb.0: // %entry
-; NO-NEON-NEXT: fcvtzs w8, h0
-; NO-NEON-NEXT: scvtf h0, w8
-; NO-NEON-NEXT: ret
-;
-; NONEON-NOSVE-LABEL: t3:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvt s0, h0
-; NONEON-NOSVE-NEXT: fcvtzs w8, s0
-; NONEON-NOSVE-NEXT: scvtf s0, w8
-; NONEON-NOSVE-NEXT: fcvt h0, s0
-; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptosi half %x to i32
%conv1 = sitofp i32 %conv to half
@@ -139,29 +119,23 @@ define double @t4(double %x) {
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
-; CHECK-STREAMING-LABEL: t4:
-; CHECK-STREAMING: // %bb.0: // %entry
-; CHECK-STREAMING-NEXT: fcvtzu x8, d0
-; CHECK-STREAMING-NEXT: ucvtf d0, x8
-; CHECK-STREAMING-NEXT: ret
+; CHECK-STREAMING-COMPATIBLE-LABEL: t4:
+; CHECK-STREAMING-COMPATIBLE: // %bb.0: // %entry
+; CHECK-STREAMING-COMPATIBLE-NEXT: fcvtzu x8, d0
+; CHECK-STREAMING-COMPATIBLE-NEXT: ucvtf d0, x8
+; CHECK-STREAMING-COMPATIBLE-NEXT: ret
+;
+; CHECK-FPRCVT-LABEL: t4:
+; CHECK-FPRCVT: // %bb.0: // %entry
+; CHECK-FPRCVT-NEXT: fcvtzu d0, d0
+; CHECK-FPRCVT-NEXT: ucvtf d0, d0
+; CHECK-FPRCVT-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t4:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzu d0, d0
; USE-NEON-NO-GPRS-NEXT: ucvtf d0, d0
; USE-NEON-NO-GPRS-NEXT: ret
-;
-; NO-NEON-LABEL: t4:
-; NO-NEON: // %bb.0: // %entry
-; NO-NEON-NEXT: fcvtzu x8, d0
-; NO-NEON-NEXT: ucvtf d0, x8
-; NO-NEON-NEXT: ret
-;
-; NONEON-NOSVE-LABEL: t4:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvtzu x8, d0
-; NONEON-NOSVE-NEXT: ucvtf d0, x8
-; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptoui double %x to i64
%conv1 = uitofp i64 %conv to double
@@ -178,29 +152,23 @@ define float @t5(float %x) {
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0
; CHECK-NEXT: ret
;
-; CHECK-STREAMING-LABEL: t5:
-; CHECK-STREAMING: // %bb.0: // %entry
-; CHECK-STREAMING-NEXT: fcvtzu w8, s0
-; CHECK-STREAMING-NEXT: ucvtf s0, w8
-; CHECK-STREAMING-NEXT: ret
+; CHECK-STREAMING-COMPATIBLE-LABEL: t5:
+; CHECK-STREAMING-COMPATIBLE: // %bb.0: // %entry
+; CHECK-STREAMING-COMPATIBLE-NEXT: fcvtzu w8, s0
+; CHECK-STREAMING-COMPATIBLE-NEXT: ucvtf s0, w8
+; CHECK-STREAMING-COMPATIBLE-NEXT: ret
+;
+; CHECK-FPRCVT-LABEL: t5:
+; CHECK-FPRCVT: // %bb.0: // %entry
+; CHECK-FPRCVT-NEXT: fcvtzu s0, s0
+; CHECK-FPRCVT-NEXT: ucvtf s0, s0
+; CHECK-FPRCVT-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t5:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzu s0, s0
; USE-NEON-NO-GPRS-NEXT: ucvtf s0, s0
; USE-NEON-NO-GPRS-NEXT: ret
-;
-; NO-NEON-LABEL: t5:
-; NO-NEON: // %bb.0: // %entry
-; NO-NEON-NEXT: fcvtzu w8, s0
-; NO-NEON-NEXT: ucvtf s0, w8
-; NO-NEON-NEXT: ret
-;
-; NONEON-NOSVE-LABEL: t5:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvtzu w8, s0
-; NONEON-NOSVE-NEXT: ucvtf s0, w8
-; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptoui float %x to i32
%conv1 = uitofp i32 %conv to float
@@ -217,33 +185,27 @@ define half @t6(half %x) {
; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
; CHECK-NEXT: ret
;
-; CHECK-STREAMING-LABEL: t6:
-; CHECK-STREAMING: // %bb.0: // %entry
-; CHECK-STREAMING-NEXT: fcvt s0, h0
-; CHECK-STREAMING-NEXT: fcvtzu w8, s0
-; CHECK-STREAMING-NEXT: ucvtf s0, w8
-; CHECK-STREAMING-NEXT: fcvt h0, s0
-; CHECK-STREAMING-NEXT: ret
+; CHECK-STREAMING-COMPATIBLE-LABEL: t6:
+; CHECK-STREAMING-COMPATIBLE: // %bb.0: // %entry
+; CHECK-STREAMING-COMPATIBLE-NEXT: fcvt s0, h0
+; CHECK-STREAMING-COMPATIBLE-NEXT: fcvtzu w8, s0
+; CHECK-STREAMING-COMPATIBLE-NEXT: ucvtf s0, w8
+; CHECK-STREAMING-COMPATIBLE-NEXT: fcvt h0, s0
+; CHECK-STREAMING-COMPATIBLE-NEXT: ret
+;
+; CHECK-FPRCVT-LABEL: t6:
+; CHECK-FPRCVT: // %bb.0: // %entry
+; CHECK-FPRCVT-NEXT: fcvt s0, h0
+; CHECK-FPRCVT-NEXT: fcvtzu s0, s0
+; CHECK-FPRCVT-NEXT: ucvtf s0, s0
+; CHECK-FPRCVT-NEXT: fcvt h0, s0
+; CHECK-FPRCVT-NEXT: ret
;
; USE-NEON-NO-GPRS-LABEL: t6:
; USE-NEON-NO-GPRS: // %bb.0: // %entry
; USE-NEON-NO-GPRS-NEXT: fcvtzu h0, h0
; USE-NEON-NO-GPRS-NEXT: ucvtf h0, h0
; USE-NEON-NO-GPRS-NEXT: ret
-;
-; NO-NEON-LABEL: t6:
-; NO-NEON: // %bb.0: // %entry
-; NO-NEON-NEXT: fcvtzu w8, h0
-; NO-NEON-NEXT: ucvtf h0, w8
-; NO-NEON-NEXT: ret
-;
-; NONEON-NOSVE-LABEL: t6:
-; NONEON-NOSVE: // %bb.0: // %entry
-; NONEON-NOSVE-NEXT: fcvt s0, h0
-; NONEON-NOSVE-NEXT: fcvtzu w8, s0
-; NONEON-NOSVE-NEXT: ucvtf s0, w8
-; NONEON-NOSVE-NEXT: fcvt h0, s0
-; NONEON-NOSVE-NEXT: ret
entry:
%conv = fptoui half %x to i32
%conv1 = uitofp i32 %conv to half
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