[llvm] [AArch64] Fold scalar-to-vector shuffles into DUP/FMOV (PR #166962)

[David Green via llvm-commits]

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@@ -696,6 +696,15 @@ static bool is64bitDefwithZeroHigh64bit(MachineInstr *MI,
   const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg());
   if (RC != &AArch64::FPR64RegClass)
     return false;
+  if (MI->getOpcode() == TargetOpcode::COPY) {
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davemgreen wrote:

Does this say that any copy from gpr->fpr will have the top bits clear? I'm not sure that is reliable if the COPY gets elided, unless we turn the COPY into a real instruction that we know will not be optimized away.

https://github.com/llvm/llvm-project/pull/166962