[llvm] [AArch64][GlobalISel] Added support for left shift neon intrinsics (PR #170827)
Joshua Rodriguez via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 5 02:13:28 PST 2025
https://github.com/JoshdRod created https://github.com/llvm/llvm-project/pull/170827
None
>From df5a3947dfe05400c5e5b640dda048af4eb85a7e Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Tue, 25 Nov 2025 10:56:06 +0000
Subject: [PATCH 1/5] [AArch64][GlobalISel] Removed sqshl fallback occurring
for <1 x i64> operands
GISel now places sqshl operands on floating point registers. Generated code is slightly less efficient compared to SDAG.
---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 1 +
llvm/test/CodeGen/AArch64/arm64-vshift.ll | 70 ++++++++++++-------
2 files changed, 47 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 6b920f05227ad..acbec16b1cd22 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -483,6 +483,7 @@ static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
case Intrinsic::aarch64_neon_sqadd:
case Intrinsic::aarch64_neon_sqsub:
case Intrinsic::aarch64_crypto_sha1h:
+ case Intrinsic::aarch64_neon_sqshl:
case Intrinsic::aarch64_crypto_sha1c:
case Intrinsic::aarch64_crypto_sha1p:
case Intrinsic::aarch64_crypto_sha1m:
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index d27e2e69f8605..88516bd16fdbd 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -2,11 +2,7 @@
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for sqshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl1d
+; CHECK-GI: warning: Instruction selection used fallback path for uqshl1d
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl1d_constant
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl_scalar
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl_scalar_constant
@@ -155,24 +151,42 @@ define <1 x i64> @sqshl1d(ptr %A, ptr %B) nounwind {
}
define <1 x i64> @sqshl1d_constant(ptr %A) nounwind {
-; CHECK-LABEL: sqshl1d_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: sqshl d0, d0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqshl1d_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: sqshl d0, d0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqshl1d_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: sqshl d0, d0, d1
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
ret <1 x i64> %tmp3
}
define i64 @sqshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: sqshl_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: sqshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqshl_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x8, [x0]
+; CHECK-SD-NEXT: ldr x9, [x1]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: sqshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqshl_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: ldr d1, [x1]
+; CHECK-GI-NEXT: sqshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 %tmp2)
@@ -180,12 +194,21 @@ define i64 @sqshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @sqshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: sqshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: sqshl d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: sqshl d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: sqshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -2616,7 +2639,6 @@ define <4 x i32> @neon_sshl4s_wrong_ext_constant_shift(ptr %A) nounwind {
; CHECK-GI-NEXT: ret
%tmp1 = load <4 x i8>, ptr %A
%tmp2 = sext <4 x i8> %tmp1 to <4 x i32>
- %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
ret <4 x i32> %tmp3
}
>From 71e4e0d66ec1eeb5c767188aa447c52247207029 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Tue, 25 Nov 2025 11:20:22 +0000
Subject: [PATCH 2/5] [AArch64][GlobalISel] Removed fallback for uqsh, uqrsh,
and sqrsh with <1 x i64> operands
GISel now places operands for these intrinsics on floating point registers. Generated code is slightly less efficient compared to SDAG.
---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 3 +
llvm/test/CodeGen/AArch64/arm64-vshift.ll | 185 +++++++++++-------
2 files changed, 119 insertions(+), 69 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index acbec16b1cd22..ff0321c8b41d1 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -484,6 +484,9 @@ static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
case Intrinsic::aarch64_neon_sqsub:
case Intrinsic::aarch64_crypto_sha1h:
case Intrinsic::aarch64_neon_sqshl:
+ case Intrinsic::aarch64_neon_uqshl:
+ case Intrinsic::aarch64_neon_sqrshl:
+ case Intrinsic::aarch64_neon_uqrshl:
case Intrinsic::aarch64_crypto_sha1c:
case Intrinsic::aarch64_crypto_sha1p:
case Intrinsic::aarch64_crypto_sha1m:
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index 88516bd16fdbd..43efb19dbf0f2 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -2,27 +2,7 @@
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for uqshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshr1d
+; CHECK-GI: warning: Instruction selection used fallback path for urshr1d
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshr_scalar
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshr1d
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshr_scalar
@@ -371,24 +351,42 @@ define <1 x i64> @uqshl1d(ptr %A, ptr %B) nounwind {
}
define <1 x i64> @uqshl1d_constant(ptr %A) nounwind {
-; CHECK-LABEL: uqshl1d_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: uqshl d0, d0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uqshl1d_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: uqshl d0, d0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uqshl1d_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: uqshl d0, d0, d1
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
ret <1 x i64> %tmp3
}
define i64 @uqshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: uqshl_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: uqshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uqshl_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x8, [x0]
+; CHECK-SD-NEXT: ldr x9, [x1]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: uqshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uqshl_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: ldr d1, [x1]
+; CHECK-GI-NEXT: uqshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 %tmp2)
@@ -396,12 +394,21 @@ define i64 @uqshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @uqshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: uqshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: uqshl d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uqshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: uqshl d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uqshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: uqshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -905,13 +912,23 @@ define <1 x i64> @sqrshl1d_constant(ptr %A) nounwind {
}
define i64 @sqrshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: sqrshl_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: sqrshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqrshl_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x8, [x0]
+; CHECK-SD-NEXT: ldr x9, [x1]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: sqrshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqrshl_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: ldr d1, [x1]
+; CHECK-GI-NEXT: sqrshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 %tmp2)
@@ -919,14 +936,24 @@ define i64 @sqrshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @sqrshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: sqrshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #1 // =0x1
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: sqrshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqrshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x9, [x0]
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: fmov d0, x9
+; CHECK-SD-NEXT: sqrshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqrshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: sqrshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -1011,13 +1038,23 @@ define <1 x i64> @uqrshl1d_constant(ptr %A) nounwind {
}
define i64 @uqrshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: uqrshl_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: uqrshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uqrshl_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x8, [x0]
+; CHECK-SD-NEXT: ldr x9, [x1]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: uqrshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uqrshl_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: ldr d1, [x1]
+; CHECK-GI-NEXT: uqrshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 %tmp2)
@@ -1025,14 +1062,24 @@ define i64 @uqrshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @uqrshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: uqrshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #1 // =0x1
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: uqrshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uqrshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x9, [x0]
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: fmov d0, x9
+; CHECK-SD-NEXT: uqrshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uqrshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: uqrshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
>From 53c3c4bdf4c704a1d09915e643e30231a7211bc2 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Tue, 25 Nov 2025 13:55:32 +0000
Subject: [PATCH 3/5] [AArch64][GlobalISel] Updated arm64-vshift.ll to have
correct fallback lines
Check lines were previously expecting some fallbacks which no longer happen. This update fixes that.
---
llvm/test/CodeGen/AArch64/arm64-vshift.ll | 172 ++++++++++++----------
1 file changed, 97 insertions(+), 75 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index 43efb19dbf0f2..f8573e8ee0574 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -2,81 +2,103 @@
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for urshr1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshr_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshr1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshr_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu2d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu_i64_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu_i32_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for neon_ushl_vscalar_constant_shift
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for neon_ushl_scalar_constant_shift
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for neon_sshll_vscalar_constant_shift
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for neon_sshll_scalar_constant_shift
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for neon_sshll_scalar_constant_shift_m1
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ursra1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ursra_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srsra1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srsra_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli1d_imm0
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli2d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu_zero_shift_amount
+; CHECK-GI: warning: Instruction selection used fallback path for srshl1d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for srshl1d_constant
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for srshl_scalar
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for srshl_scalar_constant
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshl1d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshl1d_constant
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshl_scalar
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshl_scalar_constant
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshr1d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshr_scalar
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for srshr1d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for srshr_scalar
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu2d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu1d_constant
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu_i64_constant
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu_i32_constant
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for neon_ushl_vscalar_constant_shift
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for neon_ushl_scalar_constant_shift
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for neon_sshll_vscalar_constant_shift
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for neon_sshll_scalar_constant_shift
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for neon_sshll_scalar_constant_shift_m1
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for ursra1d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for ursra_scalar
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for srsra1d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for srsra_scalar
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli1d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli1d_imm0
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli2d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu_zero_shift_amount
define <8 x i8> @sqshl8b(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sqshl8b:
>From 80ef01ce6cdb45ca3a5c9187758a752536e806f3 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Tue, 25 Nov 2025 14:21:22 +0000
Subject: [PATCH 4/5] [AArch64][GlobalISel] Removed fallback for urshl/srshl
intrinsics with <1 x i64> operands
GISel now places urshl/srshl operands on floating point registers. Generated code is slightly less efficient compare to SDAG.
---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 2 +
llvm/test/CodeGen/AArch64/arm64-vshift.ll | 314 +++++++++++-------
llvm/test/CodeGen/AArch64/neon-addlv.ll | 27 +-
3 files changed, 220 insertions(+), 123 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index ff0321c8b41d1..652a31f4e65f2 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -483,6 +483,8 @@ static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
case Intrinsic::aarch64_neon_sqadd:
case Intrinsic::aarch64_neon_sqsub:
case Intrinsic::aarch64_crypto_sha1h:
+ case Intrinsic::aarch64_neon_srshl:
+ case Intrinsic::aarch64_neon_urshl:
case Intrinsic::aarch64_neon_sqshl:
case Intrinsic::aarch64_neon_uqshl:
case Intrinsic::aarch64_neon_sqrshl:
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index f8573e8ee0574..34843835d284a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -2,19 +2,7 @@
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for srshl1d
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for srshl1d_constant
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for srshl_scalar
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for srshl_scalar_constant
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshl1d
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshl1d_constant
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshl_scalar
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshl_scalar_constant
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshr1d
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for urshr_scalar
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for srshr1d
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for srshr_scalar
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu8b
+; CHECK-GI: warning: Instruction selection used fallback path for sqshlu8b
; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu4h
; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu2s
; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu16b
@@ -56,20 +44,6 @@
; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn8b
; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn4h
; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn2s
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn16b
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn8h
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn4s
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun1s
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun8b
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun4h
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun2s
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun16b
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun8h
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun4s
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn1s
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn8b
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn4h
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn2s
; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn16b
; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn8h
; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn4s
@@ -85,10 +59,6 @@
; CHECK-GI NEXT: warning: Instruction selection used fallback path for neon_sshll_vscalar_constant_shift
; CHECK-GI NEXT: warning: Instruction selection used fallback path for neon_sshll_scalar_constant_shift
; CHECK-GI NEXT: warning: Instruction selection used fallback path for neon_sshll_scalar_constant_shift_m1
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for ursra1d
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for ursra_scalar
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for srsra1d
-; CHECK-GI NEXT: warning: Instruction selection used fallback path for srsra_scalar
; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli8b
; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli4h
; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli2s
@@ -525,15 +495,23 @@ define <1 x i64> @srshl1d_constant(ptr %A) nounwind {
}
define i64 @srshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: srshl_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr x8, [x0]
-; CHECK-NEXT: ldr x9, [x1]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: srshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srshl_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x8, [x0]
+; CHECK-SD-NEXT: ldr x9, [x1]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: srshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srshl_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: ldr d1, [x1]
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 %tmp2)
@@ -541,15 +519,24 @@ define i64 @srshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @srshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: srshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr x9, [x0]
-; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: srshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x9, [x0]
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: fmov d0, x9
+; CHECK-SD-NEXT: srshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -621,15 +608,23 @@ define <1 x i64> @urshl1d_constant(ptr %A) nounwind {
}
define i64 @urshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: urshl_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr x8, [x0]
-; CHECK-NEXT: ldr x9, [x1]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: urshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urshl_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x8, [x0]
+; CHECK-SD-NEXT: ldr x9, [x1]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: urshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urshl_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: ldr d1, [x1]
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 %tmp2)
@@ -637,15 +632,24 @@ define i64 @urshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @urshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: urshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr x9, [x0]
-; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: urshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x9, [x0]
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: fmov d0, x9
+; CHECK-SD-NEXT: urshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -1256,23 +1260,40 @@ define <2 x i64> @urshr2d(ptr %A) nounwind {
}
define <1 x i64> @urshr1d(ptr %A) nounwind {
-; CHECK-LABEL: urshr1d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: urshr d0, d0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urshr1d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: urshr d0, d0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urshr1d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
ret <1 x i64> %tmp3
}
define i64 @urshr_scalar(ptr %A) nounwind {
-; CHECK-LABEL: urshr_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: urshr d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urshr_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: urshr d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urshr_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 -1)
ret i64 %tmp3
@@ -1405,23 +1426,40 @@ define <2 x i64> @srshr2d(ptr %A) nounwind {
}
define <1 x i64> @srshr1d(ptr %A) nounwind {
-; CHECK-LABEL: srshr1d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: srshr d0, d0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srshr1d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: srshr d0, d0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srshr1d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
ret <1 x i64> %tmp3
}
define i64 @srshr_scalar(ptr %A) nounwind {
-; CHECK-LABEL: srshr_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: srshr d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srshr_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: srshr d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srshr_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 -1)
ret i64 %tmp3
@@ -3381,12 +3419,24 @@ define <2 x i64> @ursra2d(ptr %A, ptr %B) nounwind {
}
define <1 x i64> @ursra1d(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: ursra1d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d1, [x0]
-; CHECK-NEXT: ldr d0, [x1]
-; CHECK-NEXT: ursra d0, d1, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ursra1d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x0]
+; CHECK-SD-NEXT: ldr d0, [x1]
+; CHECK-SD-NEXT: ursra d0, d1, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ursra1d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: ldr x8, [x1]
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: add x8, x9, x8
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
%tmp4 = load <1 x i64>, ptr %B
@@ -3395,13 +3445,24 @@ define <1 x i64> @ursra1d(ptr %A, ptr %B) nounwind {
}
define i64 @ursra_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: ursra_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: ursra d1, d0, #1
-; CHECK-NEXT: fmov x0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ursra_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ursra d1, d0, #1
+; CHECK-SD-NEXT: fmov x0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ursra_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: ldr x8, [x1]
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: add x0, x9, x8
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 -1)
%tmp4 = load i64, ptr %B
@@ -3571,12 +3632,24 @@ define <2 x i64> @srsra2d(ptr %A, ptr %B) nounwind {
}
define <1 x i64> @srsra1d(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: srsra1d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d1, [x0]
-; CHECK-NEXT: ldr d0, [x1]
-; CHECK-NEXT: srsra d0, d1, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srsra1d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x0]
+; CHECK-SD-NEXT: ldr d0, [x1]
+; CHECK-SD-NEXT: srsra d0, d1, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srsra1d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: ldr x8, [x1]
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: add x8, x9, x8
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
%tmp4 = load <1 x i64>, ptr %B
@@ -3585,13 +3658,24 @@ define <1 x i64> @srsra1d(ptr %A, ptr %B) nounwind {
}
define i64 @srsra_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: srsra_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: srsra d1, d0, #1
-; CHECK-NEXT: fmov x0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srsra_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: srsra d1, d0, #1
+; CHECK-SD-NEXT: fmov x0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srsra_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: ldr x8, [x1]
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: add x0, x9, x8
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 -1)
%tmp4 = load i64, ptr %B
diff --git a/llvm/test/CodeGen/AArch64/neon-addlv.ll b/llvm/test/CodeGen/AArch64/neon-addlv.ll
index a747ee661adcd..a6d2dab8f5687 100644
--- a/llvm/test/CodeGen/AArch64/neon-addlv.ll
+++ b/llvm/test/CodeGen/AArch64/neon-addlv.ll
@@ -2,8 +2,6 @@
; RUN: llc -mtriple aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple aarch64-none-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for uaddlv_v8i8_urshr
-
declare <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8>) nounwind readnone
declare <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8>) nounwind readnone
declare <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16>) nounwind readnone
@@ -223,12 +221,25 @@ declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32)
declare i64 @llvm.aarch64.neon.urshl.i64(i64, i64)
define <8 x i8> @uaddlv_v8i8_urshr(<8 x i8> %a) {
-; CHECK-LABEL: uaddlv_v8i8_urshr:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddlv h0, v0.8b
-; CHECK-NEXT: urshr d0, d0, #3
-; CHECK-NEXT: dup v0.8b, v0.b[0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uaddlv_v8i8_urshr:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddlv h0, v0.8b
+; CHECK-SD-NEXT: urshr d0, d0, #3
+; CHECK-SD-NEXT: dup v0.8b, v0.b[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uaddlv_v8i8_urshr:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddlv h0, v0.8b
+; CHECK-GI-NEXT: mov x8, #-3 // =0xfffffffffffffffd
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: and w9, w9, #0xffff
+; CHECK-GI-NEXT: fmov d0, x9
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: dup v0.8b, w8
+; CHECK-GI-NEXT: ret
entry:
%vaddlv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> %a)
%0 = and i32 %vaddlv.i, 65535
>From 7060138135143170161a24f9d3ef7ccbfc0ba393 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Thu, 4 Dec 2025 16:59:35 +0000
Subject: [PATCH 5/5] [AArch64][GlobalISel] Updated test checks
---
llvm/test/CodeGen/AArch64/arm64-int-neon.ll | 12 +--
llvm/test/CodeGen/AArch64/arm64-vshift.ll | 107 ++++++--------------
2 files changed, 36 insertions(+), 83 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-int-neon.ll b/llvm/test/CodeGen/AArch64/arm64-int-neon.ll
index f33d41b0dd6ef..ace179626f508 100644
--- a/llvm/test/CodeGen/AArch64/arm64-int-neon.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-int-neon.ll
@@ -3,15 +3,7 @@
; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for test_sqrshl_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqrshl_s64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqshl_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqshl_s64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqrshl_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqrshl_s64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqshl_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqshl_s64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqadd_s32
+; CHECK-GI: warning: Instruction selection used fallback path for test_uqadd_s32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqadd_s64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqsub_s32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqsub_s64
@@ -236,3 +228,5 @@ define i64 @test_sqdmulls_scalar(float %A){
%prod = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %cvt, i32 %cvt)
ret i64 %prod
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index 34843835d284a..acfef179aabf8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -142,23 +142,13 @@ define <1 x i64> @sqshl1d_constant(ptr %A) nounwind {
}
define i64 @sqshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-SD-LABEL: sqshl_scalar:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ldr x8, [x0]
-; CHECK-SD-NEXT: ldr x9, [x1]
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: fmov d1, x9
-; CHECK-SD-NEXT: sqshl d0, d0, d1
-; CHECK-SD-NEXT: fmov x0, d0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: sqshl_scalar:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr d0, [x0]
-; CHECK-GI-NEXT: ldr d1, [x1]
-; CHECK-GI-NEXT: sqshl d0, d0, d1
-; CHECK-GI-NEXT: fmov x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: sqshl_scalar:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: sqshl d0, d0, d1
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 %tmp2)
@@ -362,23 +352,13 @@ define <1 x i64> @uqshl1d_constant(ptr %A) nounwind {
}
define i64 @uqshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-SD-LABEL: uqshl_scalar:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ldr x8, [x0]
-; CHECK-SD-NEXT: ldr x9, [x1]
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: fmov d1, x9
-; CHECK-SD-NEXT: uqshl d0, d0, d1
-; CHECK-SD-NEXT: fmov x0, d0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: uqshl_scalar:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr d0, [x0]
-; CHECK-GI-NEXT: ldr d1, [x1]
-; CHECK-GI-NEXT: uqshl d0, d0, d1
-; CHECK-GI-NEXT: fmov x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: uqshl_scalar:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: uqshl d0, d0, d1
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 %tmp2)
@@ -938,23 +918,13 @@ define <1 x i64> @sqrshl1d_constant(ptr %A) nounwind {
}
define i64 @sqrshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-SD-LABEL: sqrshl_scalar:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ldr x8, [x0]
-; CHECK-SD-NEXT: ldr x9, [x1]
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: fmov d1, x9
-; CHECK-SD-NEXT: sqrshl d0, d0, d1
-; CHECK-SD-NEXT: fmov x0, d0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: sqrshl_scalar:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr d0, [x0]
-; CHECK-GI-NEXT: ldr d1, [x1]
-; CHECK-GI-NEXT: sqrshl d0, d0, d1
-; CHECK-GI-NEXT: fmov x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: sqrshl_scalar:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: sqrshl d0, d0, d1
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 %tmp2)
@@ -964,10 +934,9 @@ define i64 @sqrshl_scalar(ptr %A, ptr %B) nounwind {
define i64 @sqrshl_scalar_constant(ptr %A) nounwind {
; CHECK-SD-LABEL: sqrshl_scalar_constant:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ldr x9, [x0]
-; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: mov x8, #1 // =0x1
+; CHECK-SD-NEXT: ldr d0, [x0]
; CHECK-SD-NEXT: fmov d1, x8
-; CHECK-SD-NEXT: fmov d0, x9
; CHECK-SD-NEXT: sqrshl d0, d0, d1
; CHECK-SD-NEXT: fmov x0, d0
; CHECK-SD-NEXT: ret
@@ -1064,23 +1033,13 @@ define <1 x i64> @uqrshl1d_constant(ptr %A) nounwind {
}
define i64 @uqrshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-SD-LABEL: uqrshl_scalar:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ldr x8, [x0]
-; CHECK-SD-NEXT: ldr x9, [x1]
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: fmov d1, x9
-; CHECK-SD-NEXT: uqrshl d0, d0, d1
-; CHECK-SD-NEXT: fmov x0, d0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: uqrshl_scalar:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr d0, [x0]
-; CHECK-GI-NEXT: ldr d1, [x1]
-; CHECK-GI-NEXT: uqrshl d0, d0, d1
-; CHECK-GI-NEXT: fmov x0, d0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: uqrshl_scalar:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ldr d1, [x1]
+; CHECK-NEXT: uqrshl d0, d0, d1
+; CHECK-NEXT: fmov x0, d0
+; CHECK-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 %tmp2)
@@ -1090,10 +1049,9 @@ define i64 @uqrshl_scalar(ptr %A, ptr %B) nounwind {
define i64 @uqrshl_scalar_constant(ptr %A) nounwind {
; CHECK-SD-LABEL: uqrshl_scalar_constant:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ldr x9, [x0]
-; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: mov x8, #1 // =0x1
+; CHECK-SD-NEXT: ldr d0, [x0]
; CHECK-SD-NEXT: fmov d1, x8
-; CHECK-SD-NEXT: fmov d0, x9
; CHECK-SD-NEXT: uqrshl d0, d0, d1
; CHECK-SD-NEXT: fmov x0, d0
; CHECK-SD-NEXT: ret
@@ -2746,6 +2704,7 @@ define <4 x i32> @neon_sshl4s_wrong_ext_constant_shift(ptr %A) nounwind {
; CHECK-GI-NEXT: ret
%tmp1 = load <4 x i8>, ptr %A
%tmp2 = sext <4 x i8> %tmp1 to <4 x i32>
+ %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
ret <4 x i32> %tmp3
}
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