[llvm] [RISCV][llvm] Support VFADD, VFSUB, VFMUL codegen for Zvfbfa (PR #170612)

[Brandon Wu via llvm-commits]

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@@ -11,8 +11,11 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
 ; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
 ; RUN:     --check-prefixes=CHECK,ZVFHMIN
-; RUN: llc -mtriple=riscv64 -mattr=+zvfh,+experimental-zvfbfa,+v \
-; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+experimental-zvfbfa,+v \
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4vtomat wrote:

I had a patch that support `fpround` and `fpextend` previously which only update this sd-node test case. When doing this patch I tried to not change unrelated stuffs to make test case being mess lol
It should be `zvfhmin` I guess so that people won't get confused

https://github.com/llvm/llvm-project/pull/170612