[llvm] [RISCV] Sources of vmerge shouldn't overlap V0 (PR #170070)

[Min-Yih Hsu via llvm-commits]

mshockwave wrote:

RISC-V IREE also ran into a similar assertion (i.e. use not dominated by defs in all paths) by this patch: https://github.com/iree-org/iree/issues/22830

Reproducer:
``` llvm
define <4 x float> @_tensor_float_dispatch_0_elementwise_4_f32(<4 x i1> %0) {
  %2 = load <4 x float>, ptr null, align 64
  %.inv = fcmp oge <4 x float> zeroinitializer, %2
  %3 = select <4 x i1> %0, <4 x i1> zeroinitializer, <4 x i1> %.inv
  %4 = select <4 x i1> %3, <4 x float> %2, <4 x float> zeroinitializer
  ret <4 x float> %4
}
```
Command:
```
llc -mtriple=riscv64 -mattr='+m,+a,+f,+d,+c,+zvl512b,+v' input.ll
```

https://github.com/llvm/llvm-project/pull/170070