[llvm] 8f9ef4b - [RISCV] Add OPERAND_AVL to RISCVInstrInfo::verifyInstruction. (#170770)

[via llvm-commits]

Author: Craig Topper
Date: 2025-12-04T16:28:09-08:00
New Revision: 8f9ef4b52d31044edcff1ca46151052ccc26cee8

URL: https://github.com/llvm/llvm-project/commit/8f9ef4b52d31044edcff1ca46151052ccc26cee8
DIFF: https://github.com/llvm/llvm-project/commit/8f9ef4b52d31044edcff1ca46151052ccc26cee8.diff

LOG: [RISCV] Add OPERAND_AVL to RISCVInstrInfo::verifyInstruction. (#170770)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index a5f680c35124b..e878558f73b2c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3076,6 +3076,18 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         ErrInfo = "Invalid immediate";
         return false;
       }
+    } else if (OpType == RISCVOp::OPERAND_AVL) {
+      if (MO.isImm()) {
+        int64_t Imm = MO.getImm();
+        // VLMAX is represented as -1.
+        if (!isUInt<5>(Imm) && Imm != -1) {
+          ErrInfo = "Invalid immediate";
+          return false;
+        }
+      } else if (!MO.isReg()) {
+        ErrInfo = "Expected a register or immediate operand.";
+        return false;
+      }
     }
   }