[llvm] [AArch64] Fold scalar-to-vector shuffles into DUP/FMOV (PR #166962)

[Amina Chabane via llvm-commits]

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@@ -15666,6 +15654,56 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
     }
   }
 
+  // 128-bit NEON integer vectors:
+  // If BUILD_VECTOR has low half == splat(lane 0) and high half == zero,
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Amichaxx wrote:

The comment is implying that the low half of the reg is a splat of lane 0 and the high half is zeroed, but since there was confusion I have reworded it.

https://github.com/llvm/llvm-project/pull/166962