[llvm] [RISCV] LMUL lists for indexed and strided loads (PR #169756)
Petr Penzin via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 4 15:02:18 PST 2025
https://github.com/ppenzin updated https://github.com/llvm/llvm-project/pull/169756
>From 7d85a0310bbe99464c7bd1e3bcd05da09e66d496 Mon Sep 17 00:00:00 2001
From: Petr Penzin <penzin.dev at gmail.com>
Date: Wed, 26 Nov 2025 19:15:39 -0800
Subject: [PATCH 1/3] [RISCV] LMUL lists for indexed and strided loads
Create additional lists representing valid LMULs for strided and indexed load
of particular element sizes.
---
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 12 +++++-------
llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 8 ++++----
llvm/lib/Target/RISCV/RISCVScheduleV.td | 8 ++++++++
3 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 36a2f46416674..21d882ee8f426 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -562,7 +562,7 @@ multiclass SiFive7WriteResBase<int VLEN,
// resource, we do not need to use LMULSEWXXX constructors. However, we do
// use the SEW from the name to determine the number of Cycles.
- foreach mx = SchedMxList in {
+ foreach mx = SchedMxListDS8 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -582,10 +582,8 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteVSTOX8", [VCQ, VS], mx, IsWorstCase>;
}
}
- // TODO: The MxLists need to be filtered by EEW. We only need to support
- // LMUL >= SEW_min/ELEN. Here, the smallest EEW prevents us from having MF8
- // since LMUL >= 16/64.
- foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {
+
+ foreach mx = SchedMxListDS16 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -605,7 +603,7 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteVSTOX16", [VCQ, VS], mx, IsWorstCase>;
}
}
- foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {
+ foreach mx = SchedMxListDS32 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -625,7 +623,7 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteVSTOX32", [VCQ, VS], mx, IsWorstCase>;
}
}
- foreach mx = ["M1", "M2", "M4", "M8"] in {
+ foreach mx = SchedMxListDS64 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index a22552de71360..02c1b5fcf6462 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -437,7 +437,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVSTM", [AscalonLS], mx, IsWorstCase>;
}
-foreach mx = SchedMxList in {
+foreach mx = SchedMxListDS8 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
@@ -449,7 +449,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVSTOX8", [AscalonLS], mx, IsWorstCase>;
}
}
-foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {
+foreach mx = SchedMxListDS16 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
@@ -461,7 +461,7 @@ foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {
defm "" : LMULWriteResMX<"WriteVSTOX16", [AscalonLS], mx, IsWorstCase>;
}
}
-foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {
+foreach mx = SchedMxListDS32 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
@@ -473,7 +473,7 @@ foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {
defm "" : LMULWriteResMX<"WriteVSTOX32", [AscalonLS], mx, IsWorstCase>;
}
}
-foreach mx = ["M1", "M2", "M4", "M8"] in {
+foreach mx = SchedMxListDS64 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index d11b446920c4e..f0831e278332a 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -19,6 +19,14 @@ defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
// Used for widening floating-point Reduction as it doesn't contain MF8.
defvar SchedMxListFWRed = SchedMxListF;
+// Used for indexed and strided loads of 8 bit lanes, same as full MX list
+defvar SchedMxListDS8 = SchedMxList;
+// Used for indexed and strided loads of 16 bit lanes
+defvar SchedMxListDS16 = SchedMxListF;
+// Used for indexed and strided loads of 32 bit lanes
+defvar SchedMxListDS32 = !listremove(SchedMxListDS16, ["MF4"]);
+// Used for indexed and strided loads of 64 bit lanes
+defvar SchedMxListDS64 = !listremove(SchedMxListDS32, ["MF2"]);
class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
>From ee50e3d35776c519c8444e0dba40ff4ad9307cc4 Mon Sep 17 00:00:00 2001
From: Petr Penzin <penzin.dev at gmail.com>
Date: Tue, 2 Dec 2025 13:06:03 -0800
Subject: [PATCH 2/3] DS -> SX in MxLists aliases
S and UX/OX are the common parts of SchedWrite names for strided and segmented
operations, hence "SX" suffix, followed by EEW.
---
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 8 ++++----
llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 8 ++++----
llvm/lib/Target/RISCV/RISCVScheduleV.td | 8 ++++----
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 21d882ee8f426..77a2a2ccd16f9 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -562,7 +562,7 @@ multiclass SiFive7WriteResBase<int VLEN,
// resource, we do not need to use LMULSEWXXX constructors. However, we do
// use the SEW from the name to determine the number of Cycles.
- foreach mx = SchedMxListDS8 in {
+ foreach mx = SchedMxListSX8 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -583,7 +583,7 @@ multiclass SiFive7WriteResBase<int VLEN,
}
}
- foreach mx = SchedMxListDS16 in {
+ foreach mx = SchedMxListSX16 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -603,7 +603,7 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteVSTOX16", [VCQ, VS], mx, IsWorstCase>;
}
}
- foreach mx = SchedMxListDS32 in {
+ foreach mx = SchedMxListSX32 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -623,7 +623,7 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteVSTOX32", [VCQ, VS], mx, IsWorstCase>;
}
}
- foreach mx = SchedMxListDS64 in {
+ foreach mx = SchedMxListSX64 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index 02c1b5fcf6462..ce22c8f0dac77 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -437,7 +437,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVSTM", [AscalonLS], mx, IsWorstCase>;
}
-foreach mx = SchedMxListDS8 in {
+foreach mx = SchedMxListSX8 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
@@ -449,7 +449,7 @@ foreach mx = SchedMxListDS8 in {
defm "" : LMULWriteResMX<"WriteVSTOX8", [AscalonLS], mx, IsWorstCase>;
}
}
-foreach mx = SchedMxListDS16 in {
+foreach mx = SchedMxListSX16 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
@@ -461,7 +461,7 @@ foreach mx = SchedMxListDS16 in {
defm "" : LMULWriteResMX<"WriteVSTOX16", [AscalonLS], mx, IsWorstCase>;
}
}
-foreach mx = SchedMxListDS32 in {
+foreach mx = SchedMxListSX32 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
@@ -473,7 +473,7 @@ foreach mx = SchedMxListDS32 in {
defm "" : LMULWriteResMX<"WriteVSTOX32", [AscalonLS], mx, IsWorstCase>;
}
}
-foreach mx = SchedMxListDS64 in {
+foreach mx = SchedMxListSX64 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index f0831e278332a..a00851720de78 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -20,13 +20,13 @@ defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
// Used for widening floating-point Reduction as it doesn't contain MF8.
defvar SchedMxListFWRed = SchedMxListF;
// Used for indexed and strided loads of 8 bit lanes, same as full MX list
-defvar SchedMxListDS8 = SchedMxList;
+defvar SchedMxListSX8 = SchedMxList;
// Used for indexed and strided loads of 16 bit lanes
-defvar SchedMxListDS16 = SchedMxListF;
+defvar SchedMxListSX16 = SchedMxListF;
// Used for indexed and strided loads of 32 bit lanes
-defvar SchedMxListDS32 = !listremove(SchedMxListDS16, ["MF4"]);
+defvar SchedMxListSX32 = !listremove(SchedMxListSX16, ["MF4"]);
// Used for indexed and strided loads of 64 bit lanes
-defvar SchedMxListDS64 = !listremove(SchedMxListDS32, ["MF2"]);
+defvar SchedMxListSX64 = !listremove(SchedMxListSX32, ["MF2"]);
class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
>From 8760ed41f789f05df82b90b6f3cfe45d310e14f4 Mon Sep 17 00:00:00 2001
From: Petr Penzin <penzin.dev at gmail.com>
Date: Thu, 4 Dec 2025 14:49:39 -0800
Subject: [PATCH 3/3] Use EEW in MxList aliases
---
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 8 ++++----
llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 8 ++++----
llvm/lib/Target/RISCV/RISCVScheduleV.td | 8 ++++----
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 77a2a2ccd16f9..f8a7013a19a1a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -562,7 +562,7 @@ multiclass SiFive7WriteResBase<int VLEN,
// resource, we do not need to use LMULSEWXXX constructors. However, we do
// use the SEW from the name to determine the number of Cycles.
- foreach mx = SchedMxListSX8 in {
+ foreach mx = SchedMxListEEW8 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -583,7 +583,7 @@ multiclass SiFive7WriteResBase<int VLEN,
}
}
- foreach mx = SchedMxListSX16 in {
+ foreach mx = SchedMxListEEW16 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -603,7 +603,7 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteVSTOX16", [VCQ, VS], mx, IsWorstCase>;
}
}
- foreach mx = SchedMxListSX32 in {
+ foreach mx = SchedMxListEEW32 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -623,7 +623,7 @@ multiclass SiFive7WriteResBase<int VLEN,
defm : LMULWriteResMX<"WriteVSTOX32", [VCQ, VS], mx, IsWorstCase>;
}
}
- foreach mx = SchedMxListSX64 in {
+ foreach mx = SchedMxListEEW64 in {
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index ce22c8f0dac77..08ee180b2cb0f 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -437,7 +437,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVSTM", [AscalonLS], mx, IsWorstCase>;
}
-foreach mx = SchedMxListSX8 in {
+foreach mx = SchedMxListEEW8 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
@@ -449,7 +449,7 @@ foreach mx = SchedMxListSX8 in {
defm "" : LMULWriteResMX<"WriteVSTOX8", [AscalonLS], mx, IsWorstCase>;
}
}
-foreach mx = SchedMxListSX16 in {
+foreach mx = SchedMxListEEW16 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
@@ -461,7 +461,7 @@ foreach mx = SchedMxListSX16 in {
defm "" : LMULWriteResMX<"WriteVSTOX16", [AscalonLS], mx, IsWorstCase>;
}
}
-foreach mx = SchedMxListSX32 in {
+foreach mx = SchedMxListEEW32 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
@@ -473,7 +473,7 @@ foreach mx = SchedMxListSX32 in {
defm "" : LMULWriteResMX<"WriteVSTOX32", [AscalonLS], mx, IsWorstCase>;
}
}
-foreach mx = SchedMxListSX64 in {
+foreach mx = SchedMxListEEW64 in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles in {
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index a00851720de78..601308b377c6f 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -20,13 +20,13 @@ defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
// Used for widening floating-point Reduction as it doesn't contain MF8.
defvar SchedMxListFWRed = SchedMxListF;
// Used for indexed and strided loads of 8 bit lanes, same as full MX list
-defvar SchedMxListSX8 = SchedMxList;
+defvar SchedMxListEEW8 = SchedMxList;
// Used for indexed and strided loads of 16 bit lanes
-defvar SchedMxListSX16 = SchedMxListF;
+defvar SchedMxListEEW16 = SchedMxListF;
// Used for indexed and strided loads of 32 bit lanes
-defvar SchedMxListSX32 = !listremove(SchedMxListSX16, ["MF4"]);
+defvar SchedMxListEEW32 = !listremove(SchedMxListEEW16, ["MF4"]);
// Used for indexed and strided loads of 64 bit lanes
-defvar SchedMxListSX64 = !listremove(SchedMxListSX32, ["MF2"]);
+defvar SchedMxListEEW64 = !listremove(SchedMxListEEW32, ["MF2"]);
class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
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