[llvm] 9c273dc - [RISCV] Correct the register class for the VL op check in RISCVInstrInfo::verifyInstruction. (#170751)

[via llvm-commits]

Author: Craig Topper
Date: 2025-12-04T22:16:26Z
New Revision: 9c273dc626f3585dff3093bf99c0045b9bc41d19

URL: https://github.com/llvm/llvm-project/commit/9c273dc626f3585dff3093bf99c0045b9bc41d19
DIFF: https://github.com/llvm/llvm-project/commit/9c273dc626f3585dff3093bf99c0045b9bc41d19.diff

LOG: [RISCV] Correct the register class for the VL op check in RISCVInstrInfo::verifyInstruction. (#170751)

The VL operand cannot be X0. We represent VLMAX with -1.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 2bd63e75d060b..3bd333b9f9414 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3063,7 +3063,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
     if (Op.isReg() && Op.getReg().isValid()) {
       const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
       auto *RC = MRI.getRegClass(Op.getReg());
-      if (!RISCV::GPRRegClass.hasSubClassEq(RC)) {
+      if (!RISCV::GPRNoX0RegClass.hasSubClassEq(RC)) {
         ErrInfo = "Invalid register class for VL operand";
         return false;
       }