[llvm] f02dc4d - [VPlan] Don't try to hoist multi-defs for first-order recurrences.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2025-12-04T21:09:16Z
New Revision: f02dc4d19869f91ac967f231abb35e221efba357

URL: https://github.com/llvm/llvm-project/commit/f02dc4d19869f91ac967f231abb35e221efba357
DIFF: https://github.com/llvm/llvm-project/commit/f02dc4d19869f91ac967f231abb35e221efba357.diff

LOG: [VPlan] Don't try to hoist multi-defs for first-order recurrences.

Currently the hoisting implementation expects single-defs. Bail out on
multi-defs (VPInterleaveRecipe), to fix an assertion.

Fixes https://github.com/llvm/llvm-project/issues/170666

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 018c2d21bf46f..a59c8cf9ea1ef 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -2149,8 +2149,13 @@ static bool hoistPreviousBeforeFORUsers(VPFirstOrderRecurrencePHIRecipe *FOR,
       if (Op == FOR)
         return false;
 
-      if (auto *R = NeedsHoisting(Op))
+      if (auto *R = NeedsHoisting(Op)) {
+        // Bail out if the recipe defines multiple values.
+        // TODO: Hoisting such recipes requires additional handling.
+        if (R->getNumDefinedValues() != 1)
+          return false;
         HoistCandidates.push_back(R);
+      }
     }
   }
 

diff  --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
index 20a4a617ae3dd..b0350cd884af1 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -enable-interleaved-mem-accesses -S %s | FileCheck %s
 
 
 @p = external local_unnamed_addr global [257 x i32], align 16
@@ -1109,3 +1109,51 @@ loop:
 exit:
   ret void
 }
+
+define i8 @needs_hoist_interleave_group_op(ptr noalias %src, ptr %dst, i32 %n) {
+; CHECK-LABEL: @needs_hoist_interleave_group_op(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[FOR_0:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[XOR:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[FOR_1:%.*]] = phi i8 [ 0, [[ENTRY]] ], [ [[FSHL1:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[TMP0:%.*]] = sext i32 [[IV]] to i64
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i8, ptr [[SRC:%.*]], i64 [[TMP0]]
+; CHECK-NEXT:    [[FSHL:%.*]] = call i8 @llvm.fshl.i8(i8 [[FOR_1]], i8 2, i8 3)
+; CHECK-NEXT:    [[FSHL1]] = call i8 @llvm.fshl.i8(i8 [[FOR_0]], i8 3, i8 2)
+; CHECK-NEXT:    [[LD:%.*]] = load i8, ptr [[GEP]], align 1
+; CHECK-NEXT:    [[XOR]] = xor i8 [[LD]], [[FSHL]]
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr i8, ptr [[GEP]], i64 1
+; CHECK-NEXT:    [[LD1:%.*]] = load i8, ptr [[GEP1]], align 1
+; CHECK-NEXT:    [[IV_NEXT]] = add i32 [[IV]], 4
+; CHECK-NEXT:    store i8 [[XOR]], ptr [[DST:%.*]], align 1
+; CHECK-NEXT:    [[EC:%.*]] = icmp slt i32 [[IV]], 100
+; CHECK-NEXT:    br i1 [[EC]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK:       exit:
+; CHECK-NEXT:    [[LD1_LCSSA:%.*]] = phi i8 [ [[LD1]], [[LOOP]] ]
+; CHECK-NEXT:    ret i8 [[LD1_LCSSA]]
+;
+entry:
+  br label %loop
+
+loop:
+  %for.0 = phi i8 [ 0, %entry ], [ %xor, %loop ]
+  %for.1 = phi i8 [ 0, %entry ], [ %fshl1, %loop ]
+  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+  %0 = sext i32 %iv to i64
+  %gep = getelementptr i8, ptr %src, i64 %0
+  %fshl = call i8 @llvm.fshl.i8(i8 %for.1, i8 2, i8 3)
+  %fshl1 = call i8 @llvm.fshl.i8(i8 %for.0, i8 3, i8 2)
+  %ld = load i8, ptr %gep, align 1
+  %xor = xor i8 %ld, %fshl
+  %gep1 = getelementptr i8, ptr %gep, i64 1
+  %ld1 = load i8, ptr %gep1, align 1
+  %iv.next = add i32 %iv, 4
+  store i8 %xor, ptr %dst
+  %ec = icmp slt i32 %iv, 100
+  br i1 %ec , label %loop, label %exit
+
+exit:
+  ret i8 %ld1
+}